JP2003519833A - 依存性連鎖の発行および再発行が可能なスケジューラ - Google Patents

依存性連鎖の発行および再発行が可能なスケジューラ

Info

Publication number
JP2003519833A
JP2003519833A JP2001550546A JP2001550546A JP2003519833A JP 2003519833 A JP2003519833 A JP 2003519833A JP 2001550546 A JP2001550546 A JP 2001550546A JP 2001550546 A JP2001550546 A JP 2001550546A JP 2003519833 A JP2003519833 A JP 2003519833A
Authority
JP
Japan
Prior art keywords
instruction
instruction operation
store
scheduler
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001550546A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003519833A5 (https=
Inventor
ケラー，ジェイムズ・ビィ
ハダッド，ラムゼイ・ダブリュ
マイアー，ステファン・ジィ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/476,578 external-priority patent/US6542984B1/en
Priority claimed from US09/476,204 external-priority patent/US6622235B1/en
Priority claimed from US09/476,322 external-priority patent/US6564315B1/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2003519833A publication Critical patent/JP2003519833A/ja
Publication of JP2003519833A5 publication Critical patent/JP2003519833A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
JP2001550546A 2000-01-03 2000-08-16 依存性連鎖の発行および再発行が可能なスケジューラ Pending JP2003519833A (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US47657000A 2000-01-03 2000-01-03
US09/476,578 US6542984B1 (en) 2000-01-03 2000-01-03 Scheduler capable of issuing and reissuing dependency chains
US09/476,204 US6622235B1 (en) 2000-01-03 2000-01-03 Scheduler which retries load/store hit situations
US09/476,578 2000-01-03
US09/476,204 2000-01-03
US09/476,322 2000-01-03
US09/476,570 2000-01-03
US09/476,322 US6564315B1 (en) 2000-01-03 2000-01-03 Scheduler which discovers non-speculative nature of an instruction after issuing and reissues the instruction
PCT/US2000/022458 WO2001050253A1 (en) 2000-01-03 2000-08-16 Scheduler capable of issuing and reissuing dependency chains

Publications (2)

Publication Number Publication Date
JP2003519833A true JP2003519833A (ja) 2003-06-24
JP2003519833A5 JP2003519833A5 (https=) 2007-09-06

Family

ID=27504212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001550546A Pending JP2003519833A (ja) 2000-01-03 2000-08-16 依存性連鎖の発行および再発行が可能なスケジューラ

Country Status (6)

Country Link
EP (1) EP1244962B1 (https=)
JP (1) JP2003519833A (https=)
KR (1) KR100747128B1 (https=)
CN (1) CN1210649C (https=)
DE (1) DE60005860T2 (https=)
WO (1) WO2001050253A1 (https=)

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JP2007529833A (ja) * 2004-07-15 2007-10-25 株式会社ソニー・コンピュータエンタテインメント アウト・オブ・オーダーのｄｍａコマンドキューにおけるコマンド順序の設定に関する技術
KR20140113304A (ko) * 2013-03-14 2014-09-24 삼성전자주식회사 디펜던시들을 정리하고 리빌딩하는 시스템 및 방법

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US20020138714A1 (en) * 2001-03-22 2002-09-26 Sun Microsystems, Inc. Scoreboard for scheduling of instructions in a microprocessor that provides out of order execution
US7165167B2 (en) 2003-06-10 2007-01-16 Advanced Micro Devices, Inc. Load store unit with replay mechanism
US8327115B2 (en) 2006-04-12 2012-12-04 Soft Machines, Inc. Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode
WO2008061154A2 (en) 2006-11-14 2008-05-22 Soft Machines, Inc. Apparatus and method for processing instructions in a multi-threaded architecture using context switching
CN103250131B (zh) 2010-09-17 2015-12-16 索夫特机械公司 包括用于早期远分支预测的影子缓存的单周期多分支预测
CN103562866B (zh) 2011-03-25 2018-03-30 英特尔公司 用于通过使用由可分割引擎实例化的虚拟核来支持代码块执行的寄存器文件段
KR101966712B1 (ko) 2011-03-25 2019-04-09 인텔 코포레이션 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 메모리 프래그먼트
WO2012135031A2 (en) 2011-03-25 2012-10-04 Soft Machines, Inc. Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
EP2710481B1 (en) 2011-05-20 2021-02-17 Intel Corporation Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines
WO2012162189A1 (en) 2011-05-20 2012-11-29 Soft Machines, Inc. An interconnect structure to support the execution of instruction sequences by a plurality of engines
WO2013077876A1 (en) 2011-11-22 2013-05-30 Soft Machines, Inc. A microprocessor accelerated code optimizer
IN2014CN03678A (https=) 2011-11-22 2015-09-25 Soft Machines Inc
EP2972836B1 (en) 2013-03-15 2022-11-09 Intel Corporation A method for emulating a guest centralized flag architecture by using a native distributed flag architecture
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
CN105190541A (zh) * 2013-03-15 2015-12-23 索夫特机械公司 利用具有寄存器视图、源视图、指令视图以及多个注册模板的微处理器体系架构执行指令块的方法
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
WO2014151018A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for executing multithreaded instructions grouped onto blocks
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
JP7428689B2 (ja) 2021-12-17 2024-02-06 華邦電子股▲ふん▼有限公司 メモリシステム

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WO1998033116A2 (en) * 1997-01-29 1998-07-30 Advanced Micro Devices, Inc. A line-oriented reorder buffer for a superscalar microprocessor
US5987594A (en) * 1997-06-25 1999-11-16 Sun Microsystems, Inc. Apparatus for executing coded dependent instructions having variable latencies

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US5546554A (en) * 1994-02-02 1996-08-13 Sun Microsystems, Inc. Apparatus for dynamic register management in a floating point unit
US5655115A (en) 1995-02-14 1997-08-05 Hal Computer Systems, Inc. Processor structure and method for watchpoint of plural simultaneous unresolved branch evaluation
US5710902A (en) * 1995-09-06 1998-01-20 Intel Corporation Instruction dependency chain indentifier
US6098166A (en) * 1998-04-10 2000-08-01 Compaq Computer Corporation Speculative issue of instructions under a load miss shadow
JP3866921B2 (ja) * 1998-08-24 2007-01-10 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド ストアアドレス生成およびユニバーサルな依存性ベクトルに基づくロードブロックのためのメカニズム

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WO1998033116A2 (en) * 1997-01-29 1998-07-30 Advanced Micro Devices, Inc. A line-oriented reorder buffer for a superscalar microprocessor
JP2002513486A (ja) * 1997-01-29 2002-05-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド スーパースカラマイクロプロセッサ用ライン指向型リオーダバッファ
US5987594A (en) * 1997-06-25 1999-11-16 Sun Microsystems, Inc. Apparatus for executing coded dependent instructions having variable latencies

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007529833A (ja) * 2004-07-15 2007-10-25 株式会社ソニー・コンピュータエンタテインメント アウト・オブ・オーダーのｄｍａコマンドキューにおけるコマンド順序の設定に関する技術
KR20140113304A (ko) * 2013-03-14 2014-09-24 삼성전자주식회사 디펜던시들을 정리하고 리빌딩하는 시스템 및 방법
JP2014179101A (ja) * 2013-03-14 2014-09-25 Samsung Electronics Co Ltd ディペンデンシーを整理し、リビルディングするシステム及び方法
KR102010312B1 (ko) 2013-03-14 2019-08-13 삼성전자주식회사 디펜던시들을 정리하고 리빌딩하는 시스템 및 방법
US10552157B2 (en) 2013-03-14 2020-02-04 Samsung Electronics Co., Ltd. System and method to clear and rebuild dependencies

Also Published As

Publication number Publication date
EP1244962B1 (en) 2003-10-08
CN1451115A (zh) 2003-10-22
KR20020097149A (ko) 2002-12-31
DE60005860D1 (de) 2003-11-13
WO2001050253A1 (en) 2001-07-12
DE60005860T2 (de) 2004-08-05
KR100747128B1 (ko) 2007-08-09
EP1244962A1 (en) 2002-10-02
CN1210649C (zh) 2005-07-13

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