JP2003512673A - マルチプロセッサシステムおよびデータアクセス方法 - Google Patents

マルチプロセッサシステムおよびデータアクセス方法

Info

Publication number
JP2003512673A
JP2003512673A JP2001532400A JP2001532400A JP2003512673A JP 2003512673 A JP2003512673 A JP 2003512673A JP 2001532400 A JP2001532400 A JP 2001532400A JP 2001532400 A JP2001532400 A JP 2001532400A JP 2003512673 A JP2003512673 A JP 2003512673A
Authority
JP
Japan
Prior art keywords
memory
processor
directory
data
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001532400A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003512673A5 (enExample
Inventor
マイケル ビー ギャレス
ジェフリー エス カスキン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Graphics Properties Holdings Inc
Original Assignee
Silicon Graphics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Graphics Inc filed Critical Silicon Graphics Inc
Publication of JP2003512673A publication Critical patent/JP2003512673A/ja
Publication of JP2003512673A5 publication Critical patent/JP2003512673A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0824—Distributed directories, e.g. linked lists of caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/082—Associative directories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
JP2001532400A 1999-10-15 2000-09-19 マルチプロセッサシステムおよびデータアクセス方法 Pending JP2003512673A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/418,520 1999-10-15
US09/418,520 US6651157B1 (en) 1999-10-15 1999-10-15 Multi-processor system and method of accessing data therein
PCT/US2000/025596 WO2001029674A1 (en) 1999-10-15 2000-09-19 Multi-processor system and method of accessing data therein

Publications (2)

Publication Number Publication Date
JP2003512673A true JP2003512673A (ja) 2003-04-02
JP2003512673A5 JP2003512673A5 (enExample) 2007-11-08

Family

ID=23658459

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001532400A Pending JP2003512673A (ja) 1999-10-15 2000-09-19 マルチプロセッサシステムおよびデータアクセス方法

Country Status (4)

Country Link
US (2) US6651157B1 (enExample)
EP (1) EP1224553B1 (enExample)
JP (1) JP2003512673A (enExample)
WO (1) WO2001029674A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6651157B1 (en) * 1999-10-15 2003-11-18 Silicon Graphics, Inc. Multi-processor system and method of accessing data therein
US6810467B1 (en) 2000-08-21 2004-10-26 Intel Corporation Method and apparatus for centralized snoop filtering
US20020161453A1 (en) * 2001-04-25 2002-10-31 Peltier Michael G. Collective memory network for parallel processing and method therefor
US6959364B2 (en) 2002-06-28 2005-10-25 Intel Corporation Partially inclusive snoop filter
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7089372B2 (en) * 2003-12-01 2006-08-08 International Business Machines Corporation Local region table for storage of information regarding memory access by other nodes
US8516179B2 (en) * 2003-12-03 2013-08-20 Digital Rna, Llc Integrated circuit with coupled processing cores
US8131975B1 (en) 2008-07-07 2012-03-06 Ovics Matrix processor initialization systems and methods
US7870365B1 (en) 2008-07-07 2011-01-11 Ovics Matrix of processors with data stream instruction execution pipeline coupled to data switch linking to neighbor units by non-contentious command channel / data channel
US8327114B1 (en) 2008-07-07 2012-12-04 Ovics Matrix processor proxy systems and methods
US8145880B1 (en) 2008-07-07 2012-03-27 Ovics Matrix processor data switch routing systems and methods
US7958341B1 (en) 2008-07-07 2011-06-07 Ovics Processing stream instruction in IC of mesh connected matrix of processors containing pipeline coupled switch transferring messages over consecutive cycles from one link to another link or memory
US10235295B1 (en) * 2015-08-25 2019-03-19 Integrated Device Technology, Inc. Scalable coherent apparatus and method

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5307477A (en) * 1989-12-01 1994-04-26 Mips Computer Systems, Inc. Two-level cache memory system
US5303362A (en) * 1991-03-20 1994-04-12 Digital Equipment Corporation Coupled memory multiprocessor computer system including cache coherency management protocols
US5522058A (en) * 1992-08-11 1996-05-28 Kabushiki Kaisha Toshiba Distributed shared-memory multiprocessor system with reduced traffic on shared bus
US5394555A (en) * 1992-12-23 1995-02-28 Bull Hn Information Systems Inc. Multi-node cluster computer system incorporating an external coherency unit at each node to insure integrity of information stored in a shared, distributed memory
US5829052A (en) * 1994-12-28 1998-10-27 Intel Corporation Method and apparatus for managing memory accesses in a multiple multiprocessor cluster system
JP3872118B2 (ja) * 1995-03-20 2007-01-24 富士通株式会社 キャッシュコヒーレンス装置
US5802578A (en) * 1996-06-12 1998-09-01 Sequent Computer Systems, Inc. Multinode computer system with cache for combined tags
US5864671A (en) * 1996-07-01 1999-01-26 Sun Microsystems, Inc. Hybrid memory access protocol for servicing memory access request by ascertaining whether the memory block is currently cached in determining which protocols to be used
US5734922A (en) * 1996-07-01 1998-03-31 Sun Microsystems, Inc. Multiprocessing system configured to detect and efficiently provide for migratory data access patterns
US5829034A (en) 1996-07-01 1998-10-27 Sun Microsystems, Inc. Method and apparatus for a coherence transformer with limited memory for connecting computer system coherence domains
US6088769A (en) 1996-10-01 2000-07-11 International Business Machines Corporation Multiprocessor cache coherence directed by combined local and global tables
US5784394A (en) * 1996-11-15 1998-07-21 International Business Machines Corporation Method and system for implementing parity error recovery schemes in a data processing system
US5944780A (en) * 1997-05-05 1999-08-31 At&T Corp Network with shared caching
FR2763714B1 (fr) 1997-05-26 1999-07-02 Bull Sa Compteurs de remplacement pour machine avec memoire a acces non uniforme
US6044438A (en) * 1997-07-10 2000-03-28 International Business Machiness Corporation Memory controller for controlling memory accesses across networks in distributed shared memory processing systems
US6092155A (en) * 1997-07-10 2000-07-18 International Business Machines Corporation Cache coherent network adapter for scalable shared memory processing systems
US6073216A (en) * 1997-11-25 2000-06-06 Intel Corporation System and method for reliable system shutdown after coherency corruption
US6480975B1 (en) * 1998-02-17 2002-11-12 International Business Machines Corporation ECC mechanism for set associative cache array
US6374331B1 (en) * 1998-12-30 2002-04-16 Hewlett-Packard Company Distributed directory cache coherence multi-processor computer architecture
US6487685B1 (en) * 1999-09-30 2002-11-26 Silicon Graphics, Inc. System and method for minimizing error correction code bits in variable sized data formats
US6651157B1 (en) * 1999-10-15 2003-11-18 Silicon Graphics, Inc. Multi-processor system and method of accessing data therein

Also Published As

Publication number Publication date
US6651157B1 (en) 2003-11-18
EP1224553A1 (en) 2002-07-24
EP1224553B1 (en) 2013-05-15
WO2001029674A1 (en) 2001-04-26
US20040098561A1 (en) 2004-05-20

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