JP2003502736A - 動的なパーティショニングおよびオンデマンド評価を使用した回路シミュレーション - Google Patents

動的なパーティショニングおよびオンデマンド評価を使用した回路シミュレーション

Info

Publication number
JP2003502736A
JP2003502736A JP2001503098A JP2001503098A JP2003502736A JP 2003502736 A JP2003502736 A JP 2003502736A JP 2001503098 A JP2001503098 A JP 2001503098A JP 2001503098 A JP2001503098 A JP 2001503098A JP 2003502736 A JP2003502736 A JP 2003502736A
Authority
JP
Japan
Prior art keywords
dynamic
partition
circuit
dynamic partition
partitions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001503098A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003502736A5 (enExample
Inventor
ダール，サンジャイ
Original Assignee
メンター・グラフィクス・コーポレーション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by メンター・グラフィクス・コーポレーション filed Critical メンター・グラフィクス・コーポレーション
Publication of JP2003502736A publication Critical patent/JP2003502736A/ja
Publication of JP2003502736A5 publication Critical patent/JP2003502736A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2001503098A 1999-06-14 2000-04-28 動的なパーティショニングおよびオンデマンド評価を使用した回路シミュレーション Pending JP2003502736A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/333,124 US6480816B1 (en) 1999-06-14 1999-06-14 Circuit simulation using dynamic partitioning and on-demand evaluation
US09/333,124 1999-06-14
PCT/US2000/011508 WO2000077693A1 (en) 1999-06-14 2000-04-28 Circuit simulation using dynamic partitioning and on-demand evaluation

Publications (2)

Publication Number Publication Date
JP2003502736A true JP2003502736A (ja) 2003-01-21
JP2003502736A5 JP2003502736A5 (enExample) 2010-02-25

Family

ID=23301391

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001503098A Pending JP2003502736A (ja) 1999-06-14 2000-04-28 動的なパーティショニングおよびオンデマンド評価を使用した回路シミュレーション

Country Status (5)

Country Link
US (1) US6480816B1 (enExample)
EP (1) EP1192569A1 (enExample)
JP (1) JP2003502736A (enExample)
AU (1) AU4676900A (enExample)
WO (1) WO2000077693A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011528839A (ja) * 2009-07-28 2011-11-24 シノプシイス インコーポレイテッド 電子回路の階層的次数ランキングされたシミュレーション

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US7000202B1 (en) * 1998-07-22 2006-02-14 Magma Design Automation, Inc. Method of vector generation for estimating performance of integrated circuit designs
US6937969B1 (en) * 1999-06-10 2005-08-30 Interuniversitair Microelektronica Centrum (Imec) Method for determining signals in mixed signal systems
US7120877B2 (en) * 2001-04-10 2006-10-10 National Instruments Corporation System and method for creating a graphical program including a plurality of portions to be executed sequentially
US7076416B2 (en) * 2001-08-20 2006-07-11 Sun Microsystems, Inc. Method and apparatus for evaluating logic states of design nodes for cycle-based simulation
US7328195B2 (en) * 2001-11-21 2008-02-05 Ftl Systems, Inc. Semi-automatic generation of behavior models continuous value using iterative probing of a device or existing component model
US20030149962A1 (en) * 2001-11-21 2003-08-07 Willis John Christopher Simulation of designs using programmable processors and electronically re-configurable logic arrays
US7127384B2 (en) * 2002-08-27 2006-10-24 Freescale Semiconductor, Inc. Fast simulation of circuitry having SOI transistors
US7110930B2 (en) * 2002-11-15 2006-09-19 International Business Machines Corporation Integrated circuit and package modeling
DE10303684B4 (de) * 2003-01-30 2005-11-24 Infineon Technologies Ag Verfahren und Vorrichtung zur formalen Schaltungsverifikation einer digitalen Schaltung
WO2006007474A2 (en) * 2004-06-23 2006-01-19 Sioptical, Inc. Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits
US7617465B1 (en) 2004-09-16 2009-11-10 Cadence Design Systems, Inc. Method and mechanism for performing latch-up check on an IC design
US8448096B1 (en) 2006-06-30 2013-05-21 Cadence Design Systems, Inc. Method and system for parallel processing of IC design layouts
US8806426B2 (en) * 2008-06-04 2014-08-12 Microsoft Corporation Configurable partitioning of parallel data for parallel processing
US8527257B2 (en) 2011-07-01 2013-09-03 Fujitsu Limited Transition-based macro-models for analog simulation
CN103034750B (zh) * 2011-09-30 2016-06-15 济南概伦电子科技有限公司 可重复电路仿真的方法和系统
US8903698B2 (en) 2012-05-15 2014-12-02 Fujitsu Limited Generating behavioral models for analog circuits
CN103970604B (zh) * 2013-01-31 2017-05-03 国际商业机器公司 基于MapReduce架构实现图处理的方法和装置
US9053278B1 (en) 2013-03-15 2015-06-09 Gear Design Solutions System and method for hybrid cloud computing for electronic design automation
US9286427B1 (en) 2013-03-15 2016-03-15 Gear Design Solutions System and method for netlist extraction and circuit simulation
TWI614686B (zh) * 2015-12-15 2018-02-11 財團法人工業技術研究院 系統模擬方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5305229A (en) 1991-09-06 1994-04-19 Bell Communications Research, Inc. Switch-level timing simulation based on two-connected components
US5446676A (en) 1993-03-29 1995-08-29 Epic Design Technology Inc. Transistor-level timing and power simulator and power analyzer
EP1008075B1 (de) 1996-11-18 2003-04-02 Infineon Technologies AG Rechnergestütztes verfahren zur partitionierung einer elektrischen schaltung
US6112022A (en) * 1996-12-13 2000-08-29 Legend Design Technology, Inc. Method for simulating ULSI/VLSI circuit designs
US6049662A (en) * 1997-01-27 2000-04-11 International Business Machines Corporation System and method for model size reduction of an integrated circuit utilizing net invariants

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011528839A (ja) * 2009-07-28 2011-11-24 シノプシイス インコーポレイテッド 電子回路の階層的次数ランキングされたシミュレーション

Also Published As

Publication number Publication date
US6480816B1 (en) 2002-11-12
EP1192569A1 (en) 2002-04-03
WO2000077693A1 (en) 2000-12-21
AU4676900A (en) 2001-01-02

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