JP2003347501A - Semiconductor module and wiring board used therein, and method of manufacturing semiconductor module and wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of components to be used and a manufacturing cost of a semiconductor module wherein a plurality of semiconductor chips are stacked using wiring boards (interposers). <P>SOLUTION: The wiring board has such a structure that a first principal plane of an insulation substrate is formed with a conductor wiring having a prescribed pattern, and a second principal plane opposite to the first principal plane is formed with connection terminals connected to the conductor wiring. A semiconductor chip is mounted on the wiring board to form a semiconductor device. A plurality of such semiconductor devices are stacked to fabricate the semiconductor module, wherein the conductor wiring formed on the wiring board of the first semiconductor device is electrically connected to the connection terminals formed on the wiring board of the second semiconductor device stacked on the first semiconductor device. In the semiconductor module, the conductor wiring formed on the wiring board of the first semiconductor device is directly connected to the connection terminals formed on the wiring board of the second semiconductor device. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor module, a wiring board used therefor, and a method of manufacturing a semiconductor module and a method of manufacturing a wiring board. The present invention relates to a technology effective when applied to a semiconductor module.

[0002]

2. Description of the Related Art Conventionally, a semiconductor module provided with a specific function using a plurality of semiconductor chips and electronic components includes:
There is a semiconductor module having a three-dimensional structure in which the semiconductor chips are stacked. At this time, the semiconductor module may be, for example, a dynamic random access memory (DRAM) as the semiconductor chip.
ccess Memory) or SRAM (Static Random Access Memor)
y), EEPROM (Electrically Erasable and Programmabl
e ROM) and other memory chips with a large capacity by stacking multiple memory chips of the same or multiple types,
There is a module such as a system LSI that is systemized by combining chips having different functions such as a U, a memory chip, and a communication chip. Hereinafter, the semiconductor module having the three-dimensional structure is referred to as a three-dimensional module.

In the three-dimensional module, a plurality of semiconductor devices each having a semiconductor chip mounted on a wiring board (tape carrier) in which conductor wiring is provided on the surface of a tape-shaped insulating substrate, such as a tape carrier package, are stacked. For example, as shown in FIG.
Semiconductor device D1 on which semiconductor chip 502 is mounted, second semiconductor device D2 on which semiconductor chip 502 is mounted, and semiconductor chip 503
There is a device in which a third semiconductor device D3 on which is mounted is stacked.

In the first semiconductor device D1, as shown in FIGS. 43 and 44, a conductor wiring 201 having a predetermined pattern is provided on a first main surface of an insulating substrate 101.
A semiconductor chip 501 is flip-chip mounted on a wiring board provided with connection terminals 1701 electrically connected to the conductor wiring 201 on the second main surface of the semiconductor chip 501. here,
FIG. 44 is a sectional view taken along line EE ′ of FIG.

At this time, for example, a copper plating film 1801 is provided in the opening (via hole) provided in the surface of the connection terminal 1701 and the insulating substrate 101, and the connection terminal 1701 and the conductor wiring are provided. 201 is connected by a copper plating film (via) 1801A in the via hole.

At this time, the external electrodes (bonding pads) 501A of the semiconductor chip 501 and the conductor wiring 201 on the wiring board are connected by gold bumps (stud bumps).
6, an insulator 7 such as NCF (Non Conductive Film) is provided between the wiring board and the semiconductor chip 501, and a connection portion by the gold bump 6 is sealed.

At this time, in addition to the conductor wiring 201 connected to the external electrode 501A of the semiconductor chip 501 to be mounted, the wiring board of the first semiconductor device D1
As shown in the figure, via the wiring board, another semiconductor device, that is, the semiconductor chip 502 of the second semiconductor device D2 or the semiconductor chip 503 of the third semiconductor device D3
Are provided with dummy terminals 901 for transmitting signals.

Although detailed description is omitted, the second
The configuration of the semiconductor device D2 and the third semiconductor device D3 is as follows.
The configuration is almost the same as that of the first semiconductor device D1.

Further, when a second semiconductor device D2 having the same configuration as the first semiconductor device D1 is stacked on the first semiconductor device D1 as shown in FIGS.
The first semiconductor device D1 is provided between the conductor wiring 201 and the dummy terminal 901 provided on the wiring board of the semiconductor device D1 and the connection terminal 1702 of the wiring board of the second semiconductor device D2.
A gap corresponding to the height of one semiconductor chip 501 is formed, and direct connection cannot be made. Therefore, in order to electrically connect the conductor wiring 201 or the dummy terminal 901 of the first semiconductor device D1 and the connection terminal 1702 of the second semiconductor device, for example, as shown in FIG. It is necessary to provide such connection wiring boards SB1, SB2 and SB3.

[0010] The conductor wiring 201 of the first semiconductor device D1
And a first connection wiring board SB for electrically connecting the dummy terminal 901 and the connection terminal 1702 of the second semiconductor device D2.
1 is an insulating substrate 190, as shown in FIGS.
1 on the first main surface, the connection terminal 1 of the second semiconductor device D2.
A first terminal 2001 connected to the first semiconductor device D is provided on a second main surface of the insulating substrate 1901.
A second terminal 2101 connected to one conductor wiring 201 is provided. Here, FIG. 46 is a cross-sectional view taken along line FF ′ of FIG.

At this time, openings (via holes) provided on the surface of the second terminal 2101 and the insulating substrate 1901 are provided.
Is provided with, for example, a copper plating film 2201.
The second terminal 2101 and the first terminal 2001 are electrically connected by a copper plating film (via) 2201A in the via hole.

At this time, the first connection wiring board SB
The first insulating substrate 1901 has an opening in a region that overlaps the semiconductor chip 501 of the first semiconductor device D1 in a plan view. When the insulating substrate 1901 is placed on the first semiconductor device D1, FIG.
As shown in FIG. 2, the semiconductor chip 501 is accommodated in the opening 1901A.

That is, by laminating the second semiconductor device D2 on the first semiconductor device D1 with the first connection wiring board SB1 interposed therebetween, as shown in FIG.
The conductor wiring 201 of the first semiconductor device D1 includes a plating film 8 and a second terminal 2101 of the first connection wiring board SB1.
(Copper plating film 2201), the via 2201A, and the first terminal 2001 through the second semiconductor device D2.
Is connected to the connection terminal 1702 (copper plating film 1802).

Each of the semiconductor devices is stacked on a base substrate BB as shown in FIG. The base substrate BB is a wiring substrate used for matching a connection terminal drawn out from each of the semiconductor devices with a wiring (terminal) on a mounting substrate or for grid conversion. As shown in FIG. A conductor wiring 11 having a predetermined pattern is provided on the surface of the insulating substrate 10. As means for connecting the conductor wiring 11 and the wiring on the mounting board, for example, as shown in FIG.
There is a method of providing an opening at a predetermined position and connecting the ball-shaped terminal 12 such as Sn-Pb-based solder. In addition, for example, there is a method in which a flat terminal (land) is formed on the back surface of the surface on which the semiconductor devices are stacked using a double-sided wiring board, and the terminals are connected by the land.

Further, as shown in FIG. 42, a cover plate CP is provided on the third semiconductor device D3 to protect the semiconductor chip of the third semiconductor device D3. Also at this time, since there is a gap between the wiring board of the third semiconductor device D3 and the cover plate CP, the connection is made via the third connection wiring board SB3.

The process of manufacturing a three-dimensional module as shown in FIG. 42 can be roughly divided into a semiconductor device forming process of forming semiconductor devices D1, D2 and D3 as shown in FIGS. Forming the connection wiring boards SB1, SB2, and SB3 as shown in FIGS. 45 and 46; forming the base substrate BB and the cover plate CP as shown in FIG. 48; B
Stacking the semiconductor device and the connection wiring board on B, and electrically connecting the base substrate, the semiconductor device, and the respective conductor wirings and connection terminals of the connection wiring board to form a module There is a step to do.

The steps of forming the semiconductor device will be described with reference to the first semiconductor device D1 as an example.
As shown in FIG. 9A, a first conductor film 201 ′ is formed on a first main surface of the insulating substrate 101, and a second conductive film 201 ′ is formed on the insulating substrate 101.
After forming the second conductive film 1701 ′ on the main surface, a via hole H1 is formed at a predetermined position on the insulating substrate 101.

As the insulating substrate 101, for example, a polyimide tape or the like which is long in one direction as used for manufacturing a tape carrier is used, and the first conductive film 201 'is used.
The formation of the second conductor film 1701 ′ and the formation of the via hole H1 are performed, for example, by a reel method. At this time, for example, as shown in FIG. 49A, a predetermined position outside the cutting line L2 at the time of singulation, such as an end in the longitudinal direction of the insulating substrate 101,
An opening H2 such as a sprocket hole for positioning in each step is provided.

The first conductor film 201 'and the second conductor film 1701' may be formed by, for example, a method of bonding a copper foil such as an electrolytic copper foil or a rolled copper foil, or a method of forming a surface of the insulating substrate. There is a method of forming a copper thin film by sputtering or electroless copper plating. In addition, the via hole H1
Is formed by, for example, laser etching using a carbon dioxide gas laser, an excimer laser, or the like.

Next, as shown in FIG. 49B, for example, an electrolytic copper plating film 1801 is formed on the second conductor film 1701 ′ and inside the via hole H1, and the first conductor film 201 is formed. ′ And the second conductive film 1701 ′ with the via hole H
1 are electrically connected by an electrolytic copper plating film (via) 1801A.

Next, as shown in FIG. 49C, the first conductor film 201 'is subjected to an etching process to form a conductor wiring 201 having a predetermined pattern.
1 ′ is etched to form connection terminals 1701 that are electrically connected to the conductor wiring 201. Thereafter, although not shown, for example, solder plating is formed on the surfaces of the conductor wiring and the connection terminal.

According to the above procedure, in the step of mounting the semiconductor chip 501 on the wiring board on which the conductor wiring 201 and the connection terminals 1701 are formed, the surface of the wiring board on which the semiconductor chip 501 is mounted may be, for example, an NCF. After forming such an insulator 7, the semiconductor chip 501 is flip-chip mounted as shown in FIG. At this time, the NCF
Is, for example, a semi-cured epoxy resin processed into a film shape, and the semiconductor chip 50
Gold bumps (stud bumps) on the first external electrode 501A
By providing the semiconductor chip 501, the gold bump 6 pushes the NCF 7 and comes into contact with the conductor wiring 201 when the semiconductor chip 501 is pressed. In this state, the NCF 7 is completely cured by heating, so that the gold bump 6 and the conductor wiring 201 are electrically connected.

Thereafter, a test of the electrical characteristics and the like of each semiconductor device is performed, and individual semiconductor devices are separated and only non-defective products are selected. Although not described, the second semiconductor device D2 and the third semiconductor device D3 are also formed in the same procedure as the first semiconductor device D1.

On the other hand, when the first wiring board SB1 is used as an example, the connection wiring board is shown in FIG. 51A in the same procedure as the method of manufacturing the wiring board used in each of the semiconductor devices. Thus, an electrolytic copper plating film 2201 is formed on the sixth conductor film 2101 ′ formed on the surface of the insulating substrate 1901, and the fifth conductor film 2001 ′ and the sixth conductor film 210 are formed.
After connecting the 1 ′ with the via 2201A, as shown in FIG. 50B, the sixth conductor film 2101 ′ is etched to form the second terminal 2101, and the insulating substrate 1901 is formed.
An opening 1901A is formed by, for example, a carbon dioxide laser or an etching process using a solution in a portion overlapping the semiconductor chip 501 in a plane.

Thereafter, as shown in FIG. 50 (c), the fifth conductor film 2001 'is subjected to an etching treatment so that the first terminal 2
001 is formed. Thereafter, although not shown, for example,
The surfaces of the first terminal 2001 and the second terminal 2101 (electrolytic copper plating film 2201) are plated with solder. Although detailed description is omitted, the second connection wiring board S
B2 and the third connection wiring board SB3 are also formed in the same procedure as the first connection wiring board SB1.

Although not described in detail, the base substrate BB is also formed by a reel method using a tape-shaped insulating substrate 10 as in a conventional tape carrier manufacturing method.

After the semiconductor devices D1, D2, D3 and the connection wiring boards SB1, SB2, SB3 are formed, the process for assembling the three-dimensional module is started.

When assembling the three-dimensional module, as shown in FIG. 52, first, the base substrate BB formed by the reel method is set on the stage 16 provided with the positioning pins 16A, and 1 semiconductor device D
1 and the first connection wiring board SB1. At this time, an opening H2 for positioning as shown in FIG. 52 is provided in the outer peripheral portion of the base substrate BB, the first semiconductor device D1, and the first connection wiring board SB1,
The positioning pin 16 of the stage 16 is inserted into the opening H2.
A, the conductor wiring 201 of the first semiconductor device D1 and the first connection wiring board S
The positioning of the second terminal 2101 of B1 is performed.

Next, as shown in FIG. 53, when the positioning pins 16A are stacked so as to be inserted into the openings H2 of the wiring board of the second semiconductor device D2, the first connection wiring board SB1 is removed. One terminal 2001 and the second semiconductor device D
2 are aligned, and as shown in FIG. 54, the conductor wiring 20 of the first semiconductor device D1 is aligned.
1 and the connection terminal 1702 (copper plating film 1802) of the second semiconductor device D2 can be electrically connected.

Thereafter, the second connection wiring board SB2, the third semiconductor device D3, the third connection wiring board SB3,
After sequentially laminating the cover plate CP, heating,
The solder plating 8 formed on the surface of each terminal
Is melted, connected and fixed.

Thereafter, as shown in FIG. 55, a ball-shaped terminal 1 made of Sn-Pb-based solder or the like is placed in the opening of the base substrate BB.
2 are connected to each other, and cut into individual pieces by a cutting line L2.
A three-dimensional module as shown in FIG. 2 is obtained.

[0032]

However, according to the conventional technique, each of the stacked semiconductor devices D1, D2, D3
In order to electrically connect the conductor wiring and connection terminals of
Connection wiring board SB1, as shown in FIGS. 45 and 46.
Since SB2 and SB3 are required, there is a problem that the number of components required for manufacturing the three-dimensional module increases.

The connection wiring board is formed using a material having a two-metal structure such as a double-sided copper-clad laminate, similarly to the wiring boards used for the semiconductor devices D1, D2, and D3. As the number of semiconductor devices (semiconductor chips) increases, the manufacturing cost of the connection wiring boards SB1, SB2, and SB3 increases, and the manufacturing cost of the three-dimensional module increases.

Also, for example, the conductor wiring 201 of the first semiconductor device D1 and the connection terminal 1702 of the second semiconductor device D2
Are electrically connected via the first connection wiring board SB1, the connection between the wiring board of the first semiconductor device D1 and the first connection wiring board SB1, and the first connection wiring board SB1
And the wiring board of the second semiconductor device D2 are required,
Since there are many places to be connected, there is a problem that connection failure is likely to occur and connection reliability is likely to be reduced.

The connection wiring boards SB1, SB2,
Each of the semiconductor devices D1, D2, D3 without using SB3
As a method of laminating, for example, as shown in FIG.
A connection method using a solder ball 23 has been proposed. In this case, the second semiconductor device D2 laminated on the first semiconductor device D1 as shown in FIGS. 44, 45 and 56 is, for example, as shown in FIG.
2 on a wiring board provided with conductor wiring 202 on one main surface,
After the semiconductor chip 502 is flip-chip mounted via the insulator 7, the solder ball 23 is connected to an opening provided at a predetermined position of the insulating substrate 102, as shown in FIG. After laminating a plurality of semiconductor devices, the solder balls 23 are melted by heating and connected.

However, in the case of the second semiconductor device D2 shown in FIG. 57, the heating (reflow) at the time of connecting the solder balls 23 to the wiring board causes the insulating substrate 1
If the semiconductor device 02 is warped, poor connection is likely to occur when the semiconductor devices are stacked and connected. Therefore, there is a problem that it is difficult to reduce the thickness of the insulating substrate 102, and it is difficult to reduce the thickness of the three-dimensional module.

An object of the present invention is to provide a technique capable of reducing the number of components used in a semiconductor module in which a plurality of semiconductor chips are stacked using a wiring board (interposer) and reducing the manufacturing cost of the semiconductor module. To provide.

Another object of the present invention is to provide a technique capable of improving the connection reliability between wiring boards in a semiconductor module in which a plurality of semiconductor chips are stacked using the wiring boards. .

Another object of the present invention is to provide a technique capable of reducing the thickness of a semiconductor module in which a plurality of semiconductor chips are stacked using a wiring board.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0041]

The summary of the invention disclosed in the present application is as follows.

(1) A conductor pattern having a predetermined pattern is provided on a first main surface of an insulating substrate, and a connection connected to the conductor wiring is provided on a second main surface of the insulating substrate facing the first main surface. A plurality of semiconductor devices each having a semiconductor chip mounted on a wiring board provided with terminals are stacked, and the conductor wiring provided on the wiring board of the first semiconductor device and the second semiconductor device stacked on the first semiconductor device. A semiconductor module in which a connection terminal provided on a wiring board of a semiconductor device is electrically connected to a conductor wiring provided on a wiring board of the first semiconductor device and a wiring board of the second semiconductor device. The connection module provided is a semiconductor module directly connected.

According to the means (1), the conductor wiring of the first semiconductor device and the connection terminal of the second semiconductor device are directly connected to each other, so that the connection is made via the conventional connection wiring board. The number of connection points can be reduced as compared with the case where the connection is made by connecting with each other, so that a decrease in connection reliability can be prevented.

At this time, the connecting portion between the conductor wiring of the first semiconductor device and the connection terminal of the second semiconductor device may be, for example, a conductor wiring provided on a wiring board of the first semiconductor device. The semiconductor device has a protrusion having a predetermined height in a region connected to the connection terminal provided on the wiring board of the semiconductor device, and the protrusion and the connection terminal are directly connected. It is conceivable that the insulating substrate of the wiring board is provided with a concave portion (counterbore) that can accommodate the semiconductor chip of the first semiconductor device.

At this time, the semiconductor chip may be flip-chip mounted or face-up mounted on the wiring board.

(2) A predetermined pattern of conductor wiring is provided on the first main surface of the insulating substrate, and the second main surface of the insulating substrate facing the first main surface is electrically connected to the conductor wiring. A wiring board for forming a semiconductor module by laminating a plurality of semiconductor chips, wherein the conductor wiring is provided in a region connected to the connection terminal of another wiring board. Having a height of 10 mm, and a second portion laminated on the first wiring board and the projection of the conductor wiring of the first wiring board.
A wiring board provided with a space for accommodating a semiconductor chip between the first wiring board and the second wiring board when the connection terminals of the wiring board are directly connected.

According to the means (2), when the conductor wiring has a projection, the first wiring board and the second wiring board are stacked when the second wiring board is laminated on the first wiring board. Since a space that can accommodate the semiconductor chip is provided between the wiring boards,
After the semiconductor chip is mounted on the first wiring board, even when the second wiring board is laminated, the conductor wiring of the first wiring board can be directly connected to the connection terminal of the second wiring board. Therefore, when manufacturing a semiconductor module, there is no need to connect using other components, and the number of connection points can be reduced.

(3) A conductor wiring of a predetermined pattern is provided on the first main surface of the insulating substrate, and is electrically connected to the conductor wiring on a second main surface of the insulating substrate opposite to the first main surface. A wiring board for forming a semiconductor module by laminating a plurality of semiconductor chips, wherein the insulating substrate has a recess (seat) having a predetermined shape on the second main surface side. The first wiring board and the second wiring board are provided when the conductor wiring of the first wiring board is directly connected to the connection terminal of the second wiring board laminated on the first wiring board.
This is a wiring board in which a space capable of accommodating a semiconductor chip is provided between the wiring boards.

According to the means (3), the concave portion is provided on the insulating substrate, and the second substrate is provided on the first wiring board.
When the wiring boards are stacked, a space capable of accommodating the semiconductor chip is provided between the first wiring board and the second wiring board. After the semiconductor chip is mounted, even when the second wiring board is stacked, the conductor wiring of the first wiring board and the connection terminal of the second wiring board can be directly connected. for that reason,
When manufacturing a semiconductor module, there is no need to connect using other components, and the number of connection points can be reduced.

(4) A conductor wiring of a predetermined pattern is formed on the first main surface of the insulating substrate, and is electrically connected to the conductor wiring on a second main surface of the insulating substrate opposite to the first main surface. Forming a semiconductor device by mounting a semiconductor chip on a wiring board having connection terminals formed thereon, and a semiconductor stacking a second semiconductor device on the first semiconductor device formed in the semiconductor device forming step A semiconductor device connecting step of electrically connecting the conductor wiring formed on the wiring board of the first semiconductor device and the connection terminal formed on the wiring board of the second semiconductor device. In the method for manufacturing a semiconductor module, the semiconductor device connecting step includes: connecting the conductor wiring of the wiring board of the first semiconductor device and the connection terminal of the wiring board of the second semiconductor device;
This is a method for manufacturing a semiconductor module to be directly connected.

According to the means (4), the second semiconductor device is stacked on the first semiconductor device, and the conductor wiring of the wiring board of the first semiconductor device and the wiring board of the second semiconductor device are stacked. By directly connecting the connection terminals with, for example, thermocompression bonding, a semiconductor module can be manufactured with a smaller number of parts than the number of parts required for the semiconductor module using a conventional wiring board for connection. In addition, the manufacturing cost of the semiconductor module can be reduced.

As a method of directly connecting the conductor wiring of the first semiconductor device and the connection terminal of the second semiconductor device, for example, tin or tin-silver alloy, There are a method in which solder plating such as a tin-lead alloy is formed and thermocompression bonding, and a method in which a conductive paste such as solder paste is applied to the surface of the conductor wiring or the connection terminal and thermocompression bonded.

The conductor wiring of the wiring board of the first semiconductor device and the connection terminal of the wiring board of the second semiconductor device are
By connecting by thermocompression bonding, even if the wiring board of each of the semiconductor devices is warped, the connection can be surely made, and a decrease in connection reliability can be prevented. Therefore, the thickness of the wiring board can be easily reduced, and the semiconductor module can be reduced in thickness.

In order to directly connect the conductor wiring of the wiring board of the first semiconductor device and the connection terminal of the wiring board of the second semiconductor device, for example, when forming the first semiconductor device, The semiconductor chip is mounted on a wiring board having a projection of a predetermined height at a predetermined position of the conductor wiring, and in the semiconductor device connecting step, the projection of the conductor wiring of the wiring board of the first semiconductor device is provided. And the connection terminal of the wiring board of the second semiconductor device.

Further, instead of forming a first semiconductor device in which a semiconductor chip is mounted on a wiring board having the protrusions,
For example, when forming the second semiconductor device,
Mounting a semiconductor chip on a wiring board having a recess (borebore) having a depth substantially equal to the height of the semiconductor chip of the first semiconductor device in a region overlapping with the semiconductor chip of the semiconductor device in a plane; Then, there is a method of stacking the semiconductor chips of the first semiconductor device so as to be accommodated in the recesses of the wiring board of the second semiconductor device.

(5) A step of forming a predetermined pattern of conductor wiring on the first main surface of the insulating substrate, and a step of electrically connecting the conductor wiring to the second main surface of the insulating substrate opposite to the first main surface. Forming a connection terminal to be connected, a method of manufacturing a wiring board for forming a semiconductor module by laminating a plurality of semiconductor chips, a step of opening a predetermined position of the insulating substrate, Forming a conductor film on the first main surface of the insulating substrate, forming a connection terminal by embedding a conductor in an opening of the insulating substrate, and projecting a protrusion having a predetermined height at a predetermined position on the conductor film; And a step of etching the conductor film to form a conductor wiring having the protrusions.

According to the means of (5), when the wiring boards are stacked and the protruding portion of the conductor wiring is directly connected to the connection terminal of another wiring board, a predetermined distance is provided between the wiring boards. Space can be provided. Therefore, the protrusion is
For example, by forming the semiconductor chip mounted on the wiring board at substantially the same height as that of the semiconductor chip, when a plurality of wiring boards on which the semiconductor chip is mounted are stacked, each wiring board can be directly connected to each other. it can.

(6) A step of forming a conductor wiring of a predetermined pattern on the first main surface of the insulating substrate, and a step of electrically connecting the conductor wiring to the second main surface of the insulating substrate opposite to the first main surface. Forming a connection terminal to be connected, comprising: laminating a plurality of semiconductor chips to form a semiconductor module; and forming a first conductor on a first main surface of the insulating substrate. Forming a film, forming a second conductive film on a second main surface of the insulating substrate opposite to the first main surface, opening a predetermined position of the insulating substrate, Forming a via for electrically connecting the two conductor films;
Forming a projection having a predetermined height at a predetermined position on the first conductor film; etching the first conductor film to form a conductor wiring having the projection; Forming a connection terminal by etching.

According to the above-mentioned means (6), similar to the above-mentioned means (5), the wiring boards are laminated, and the protruding portions of the conductor wiring are directly connected to the connection terminals of another wiring board. Then, a predetermined space can be provided between the wiring boards. Therefore, by forming the protrusions at, for example, substantially the same height as the height of the semiconductor chip mounted on the wiring board, when a plurality of wiring boards on which the semiconductor chip is mounted are stacked, They can be directly connected to each other.

In the means of (5) and (6), the step of forming the projecting portion includes forming a projecting portion having a predetermined height by electrolytic copper plating, and then flattening the tip of the projecting portion. By doing so, the height of each protrusion formed on one wiring board can be made uniform, and it is possible to prevent a decrease in connection reliability when the wiring boards are stacked and connected.

When the projection is formed by the electrolytic copper plating, for example, a plating film of tin or a tin-silver alloy is formed on the surface of the projection and the surface of the connection terminal. When a plurality of wiring boards on which semiconductor chips are mounted are stacked, the protrusions and the connection terminals can be connected by thermocompression bonding.

(7) A step of forming a conductor wiring of a predetermined pattern on the first main surface of the insulating substrate, and electrically connecting the conductor wiring to the second main surface of the insulating substrate opposite to the first main surface. Forming a connection terminal to be connected, comprising: laminating a plurality of semiconductor chips to form a semiconductor module; and forming a first conductor on a first main surface of the insulating substrate. Forming a film, forming a second conductive film on a second main surface of the insulating substrate opposite to the first main surface, opening a predetermined position of the insulating substrate, Forming a via for electrically connecting the two conductor films;
Forming a connection terminal by etching the second conductor film; and forming a recess (counterbore) having a predetermined depth from the second main surface side in a predetermined region of the insulating substrate;
Forming a conductor wiring electrically connected to the connection terminal by etching the first conductor film.

According to the means of (7), the wiring board is laminated by forming a recess having a predetermined depth in the wiring board, and the conductor wiring is connected to the connection terminal of another wiring board. When these are directly connected, a predetermined space can be provided between the wiring boards. Therefore, by forming the concave portion at a depth substantially equal to the height of the semiconductor chip mounted on the wiring board, for example, when a plurality of wiring boards mounting the semiconductor chip are stacked, The plates can be connected directly.

Hereinafter, the present invention will be described in detail along with embodiments (examples) with reference to the drawings.

In all the drawings for describing the embodiments, parts having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

[0066]

(Embodiment 1) FIGS. 1 to 9 are schematic views showing a schematic configuration of a semiconductor module according to Embodiment 1 of the present invention, and FIG. 1 is a schematic cross section showing an entire configuration of the semiconductor module. FIG. 2 is a schematic plan view of a first semiconductor device used in the semiconductor module. FIG. 3 is a cross-sectional view taken along line AA ′ in FIG. 2. FIG.
FIG. 5 is a schematic plan view of a third semiconductor device used in a semiconductor module, and FIG. 6 is an enlarged cross-sectional view of a connection portion of FIG. 1 and a cross section corresponding to line AA ′ of FIG. FIG. 7 is an enlarged cross-sectional view of the connecting portion shown in FIG.
FIG. 8 is a schematic plan view of a base substrate used in the semiconductor module, and FIG. 9 is a schematic plan view of a cover plate used in the semiconductor module.

1 to 9, D1 denotes the first semiconductor device, 101 denotes the insulating substrate of the first semiconductor device, 201 denotes the conductor wiring of the first semiconductor device, 301 denotes the connection terminal of the first semiconductor device, and 401 denotes the first semiconductor device. 1, a projection of the semiconductor device; 501, a semiconductor chip of the first semiconductor device; 501A, an external electrode of the semiconductor chip of the first semiconductor device; D2, a second semiconductor device;
102 is an insulating substrate of the second semiconductor device, 202 is a conductor wiring of the second semiconductor device, 302 is a connection terminal of the second semiconductor device, 402 is a projection of the second semiconductor device, 502 is a semiconductor chip of the second semiconductor device, 502A is the external electrode of the semiconductor chip of the second semiconductor device; D3 is the third semiconductor device;
3 is an insulating substrate of the third semiconductor device, 203 is a conductor wiring of the third semiconductor device, 303 is a connection terminal of the third semiconductor device,
03 is a projection of the third semiconductor device, 503 is a semiconductor chip of the third semiconductor device, 503A is an external electrode of the semiconductor chip of the third semiconductor device, 6 is a gold bump, 7 is an insulator, 8 is a plating film, 901 902 and 903 are dummy wirings, BB is a base substrate, 10 is an insulating substrate of the base substrate, 11 is a conductor wiring of the base substrate, 12 is a ball-shaped terminal, CP is a cover plate, 13 is a cover plate substrate, and 14 is a dummy terminal. It is.

As shown in FIG. 1, the semiconductor module according to the first embodiment includes a semiconductor chip 501 on a base substrate BB.
Semiconductor device D1, semiconductor chip 502 on which is mounted
Semiconductor device D2 on which semiconductor chip 5 is mounted, and semiconductor chip 5
03 are mounted on the third semiconductor device D3 on which the third semiconductor device D3 is mounted.
This is a module having a three-dimensional structure in which a cover plate CP is stacked thereon.

In the semiconductor module of the first embodiment, the semiconductor chip 501 of the first semiconductor device D1, the semiconductor chip 502 of the second semiconductor device D2, and the semiconductor chip 503 of the third semiconductor device D3 are, for example, ,
A memory module having a large capacity by stacking the three semiconductor chips 501, 502, and 503 as a memory chip such as a DRAM, an SRAM, and an EEPROM will be described as an example.

At this time, as shown in FIGS. 1, 2 and 3, the first semiconductor device D1 has a predetermined pattern of conductor wiring 20 provided on the first main surface of the insulating substrate 101.
1. A connection terminal 3 provided in an opening H1 of the insulating substrate 101 and exposed on a second main surface side facing the first main surface.
01, a projection 401 provided at a predetermined position of the conductor wiring 201, and the conductor wiring 201 including the projection 401
A semiconductor chip 501 is flip-chip mounted on a wiring board made of a plating film 8 provided on the surface of the semiconductor chip 501. At this time, the external electrodes (bonding pads) 501A of the semiconductor chip 501 and the conductor wiring 201 are connected by gold bumps (stud bumps) 6, and an NCF or the like is provided between the wiring board and the semiconductor chip 501. Is sealed with the insulator 7.

As shown in FIG. 2, a dummy wiring 901 not connected to the external electrode 501A of the semiconductor chip 501 is provided at a predetermined position on the insulating substrate 101. At this time, also on the dummy wiring 901,
A protrusion 401 is provided as in the case of the conductor wiring 201. The dummy wiring 901 and the protrusion 40
The plating film 8 is also provided on the surface of the substrate 1. Although not shown, the insulating substrate 1 is also provided with the opening H1 below the dummy wiring 901 and the connection terminal 301 is provided in the opening H1.

As shown in FIG. 3, the height T1 of the projection 401 provided on the conductor wiring 201 and the dummy wiring 901 is smaller than that of the first semiconductor device D1. The semiconductor chip 501 is provided so as to have substantially the same height as the height T2 from the conductor wiring 201. At this time, the height T1 of the protrusion 401
More specifically, when the height T1 of the protrusion 401 and the height T3 of the connection terminal 301 protruding from the insulating substrate 101 are added, the height T2 is greater than the height T2 of the semiconductor chip 501. For example, when the thickness of the semiconductor chip 501 is 100 μm and the height of the gold bump 6 connecting the external electrode 501A of the semiconductor chip and the conductor wiring 201 is 30 μm, the height of the semiconductor chip 501 is reduced. Since the height T2 is about 130 μm, the height T1 of the protrusion 401 is also about 130 μm.

Although the detailed description is omitted, the second
The semiconductor device D2 also has the same configuration as the first semiconductor device D1, for example, as shown in FIGS. 1 and 4, the conductor wiring 202 and the dummy wiring 902 are provided on the first main surface of the insulating substrate 102. Are provided, and the conductor wiring 20 is provided.
2 and the dummy wiring 902, a protrusion 402 having a height substantially equal to the height from the mounting surface of the semiconductor chip 502 of the second semiconductor device D2 is provided. The insulating substrate 102 of the second semiconductor device D2 also has an opening H1 below the conductor wiring 202 and the dummy wiring 902.
Are provided, and a connection terminal 302 is provided in the opening.

The third semiconductor device D3 also has the same configuration as the first semiconductor device D1.
As shown in FIGS. 1 and 5, the conductor wiring 203 and the dummy wiring 903 are provided on the first main surface of the insulating substrate 103, and the conductor wiring 203 and the dummy wiring 903 are provided.
Above the semiconductor chip 503 of the third semiconductor device D3
Is provided at a height substantially equal to the height from the mounting surface. The insulating substrate 103 of the third semiconductor device D3 also has an opening provided below the conductor wiring 203 and the dummy wiring 903, and a connection terminal 303 is provided in the opening.

In the case where a plurality of memory chips are stacked as in the semiconductor module of the first embodiment, each of the conductor wirings of each of the semiconductor devices includes, for example, an address signal such as an address signal. Chips 501, 502, 5
2 and FIG.
As shown in FIG. 5 and FIG. 5, the protrusions and the connection terminals are provided at positions overlapping each other in a plane, and are provided at positions overlapping each other in a plane. Therefore, when the semiconductor devices D1, D2, and D3 are stacked, FIGS.
As shown in the figure, the conductor wiring 20 of the first semiconductor device D1
1 and the connection terminal 302 of the second semiconductor device D2 are directly connected by the protrusion 401 and the plating film 8 of the first semiconductor device D1. Similarly, the conductor wiring 202 of the second semiconductor device D2 and the connection terminal 3 of the third semiconductor device D3
Numeral 03 is directly connected to the projection 402 of the second semiconductor device D2 and the plating film 8.

Further, each of the semiconductor devices D1, D2, D3
Of the first semiconductor device D1 and the second semiconductor device D
2 and the conductor wiring for identifying the third semiconductor device D3 and transmitting an individual signal to each of the semiconductor chips 501, 502 and 503, as shown in FIG. 2, FIG. 4 and FIG.
Each is pulled out so that it does not overlap in a plane. At this time, for example, the wiring board of the second semiconductor device D2 and the conductor wire 201 for the chip select signal of the first semiconductor device D1 and the conductor wire 203 for the chip select signal of the third semiconductor device D3 are flatly arranged. As shown in FIG. 4, dummy wirings 902 are provided at positions that overlap with each other. That is, as shown in FIG. 7, the conductor wiring 202 for the chip select signal of the second semiconductor device D2 is formed by connecting the connection terminal 302 to the projection 401 and the plating film on the dummy wiring 901 of the first semiconductor device D1. 8 is connected directly. At this time, the second semiconductor device D
The protrusion 402 on the second conductor wiring 201 is directly connected to the connection terminal 303 of the dummy wiring 903 of the third semiconductor device D3.

The first semiconductor device D 1 and the second semiconductor device D 1
The semiconductor device D2 and the third semiconductor device D3 are stacked on the base substrate BB as shown in FIGS. 1, 6, and 7. The base substrate BB is, for example, a wiring substrate used for matching a connection terminal of each of the semiconductor devices and a wiring (terminal) on a mounting substrate on which the semiconductor module is mounted, or performing grid conversion. As shown in FIGS. 7 and 8, for example, a conductor wiring 11 having a pattern for matching is provided on the surface of the insulating substrate 10. In addition, the insulating substrate 10 is provided with openings as shown in FIGS. 1, 6, and 7 at positions corresponding to wirings (terminals) on a mounting substrate on which the semiconductor module is mounted. A ball-shaped terminal 12 made of, for example, Sn-Pb solder is connected to the opening.

On the third semiconductor device D3, as shown in FIGS. 1, 6, and 7, a cover plate C is provided.
P is provided. The cover plate CP is intended to protect the semiconductor chip 503 of the third semiconductor device D3, and as shown in FIG. 9, for example, the conductor wiring 20 of the third semiconductor device D3 on the surface of the insulating substrate 13.
The dummy terminal 14 is provided at a position overlapping the projection 403 of the third semiconductor device D3 and the dummy wiring 903, and as shown in FIGS. 6 and 7, the projection 403 of the third semiconductor device D3 is The dummy terminal 14 is directly connected.

The method of manufacturing a semiconductor module according to the first embodiment is roughly divided into a step of forming a wiring board used for each of the semiconductor devices, and a step of forming each semiconductor device by mounting a semiconductor chip on the wiring board. And a step of stacking the semiconductor device on the base substrate, and a step of connecting the semiconductor device to the base substrate. Hereinafter, the method of manufacturing the semiconductor module according to the first embodiment will be described step by step along the above-described steps.

FIGS. 10 to 12 are schematic diagrams for explaining a method of manufacturing a wiring board used for the semiconductor module of the first embodiment. FIGS. 10 (a), 10 (b), and 10
(C), FIG. 11 (a), FIG. 11 (b), and FIG. 12 are schematic cross-sectional views in respective manufacturing steps of a wiring board used for the first semiconductor device D1.

As a method of manufacturing a semiconductor module according to the first embodiment, a process for forming a wiring board used for each of the semiconductor devices will be described first. The wiring board used for each of the semiconductor devices is manufactured in the same process. Since it is formed, a process of forming a wiring board used for the first semiconductor device D1 will be described as an example. The wiring substrate is manufactured by a reel method using a tape-shaped insulating substrate that is long in one direction such as a polyimide tape, such as a wiring substrate (tape carrier) used for a tape carrier package. I do.

First, as shown in FIG. 10A, the connection terminals are formed at predetermined positions on the tape-shaped insulating substrate 101 by punching using a die or laser processing using a carbon dioxide gas laser or the like. Opening H1 and opening (sprocket hole) H used for positioning, etc.
Form 2 At this time, the insulating substrate 101 is, for example, a polyimide tape having a thickness of about 50 μm, or a glass cloth base epoxy resin laminate (glass epoxy substrate) in which a cloth woven of glass fiber is impregnated with an epoxy resin. Used. Although not shown, an adhesive layer made of a semi-cured thermosetting resin or the like is provided on the first main surface of the insulating substrate 101.

Next, as shown in FIG. 10B, a first conductor film 201 'is formed on the first main surface of the insulating substrate 101 in which the openings H1 and H2 have been formed. At this time, the first
The conductive film 201 ′ is formed by bonding a copper foil having a thickness of about 12 μm, such as an electrolytic copper foil or a rolled copper foil, using the above-mentioned adhesive layer (not shown).

Next, as shown in FIG. 10C, a resist (plating resist) having a predetermined area opened on the first conductive film 201 ′ and on the second main surface side of the insulating substrate 101.
15 is formed, and copper is embedded in the opening H1 of the insulating substrate 101 by, for example, electrolytic copper plating to form connection terminals 30.
1 and a projection 401 is formed on the first conductive film 201 '. At this time, in the electrolytic copper plating, a strip-shaped anode is provided on each of the first main surface side and the second main surface side of the insulating substrate 101 using the first conductor film 201 ′ as a cathode. It is preferable to form the connection terminal 301 and the projection 401 at one time while transporting the substrate 101 in a certain direction. However, the connection terminal 3
01 is formed so as to protrude from the insulating substrate 101 by about 10 μm, that is, to have a thickness of about 60 μm;
The protrusion 401 has a height substantially equal to the height from the mounting surface of the semiconductor chip to be mounted, that is, a thickness (height) of 1.
It is formed to have a thickness of about 30 μm. Therefore, the anode on the connection terminal 301 side is shortened or a shield plate is provided so that the growth of the connection terminal 301 stops halfway.

At this time, since the connection terminals 301 and the projections 401 are formed by electrolytic copper plating, the height of the projections 401 varies after the formation, for example, as shown in FIG. ΔT occurs or the tip becomes concave or convex. Therefore, after the connection terminals 301 and the protrusions 401 are formed and the plating resist 15 is removed, the protrusions 401 are formed by using, for example, a roll method or a press method, as shown in FIG.
Height and make the tip flat.

Next, as shown in FIG. 12, the first conductor film 201 'is etched to form the conductor wiring 201 and the dummy wiring 901 having the pattern shown in FIG. A plating film 8 is formed on the surfaces of the conductor wiring 201 and the dummy wiring 901 including the surface 401 and the surface of the connection terminal 301. The plating film 8
Is formed using, for example, tin or a tin-silver alloy. For example, when formed by electroless tin plating, the thickness is 0.5
It is formed to have a thickness of about 1 μm to 1 μm. Further, in the case of forming a tin-silver alloy plating by electroplating instead of the electroless tin plating, for example, a tin-silver alloy having a silver weight percentage of about 3.5% is formed to a thickness of 0.5 μm or more and 5 μm or less. Formed. In the case of forming by electrolytic tin plating, the thickness is set to be 0.5 μm or more and 5 μm or less.

According to the above procedure, the first semiconductor device D
The wiring board used for 1 is formed. Although detailed description is omitted, the wiring board used for the second semiconductor device D2 and the wiring board used for the third semiconductor device D3 are formed in the same procedure as the above procedure.

After forming each of the wiring boards according to the above procedure, a semiconductor chip is mounted on the wiring board to form a semiconductor device. Here, a method of forming the first semiconductor device D1 using the wiring board will be described as an example.

FIGS. 13A and 13B are schematic views for explaining a method of manufacturing a semiconductor device used for the semiconductor module of the first embodiment. FIGS. 13A and 13B show the first semiconductor device, respectively. It is sectional drawing of each process which forms.

In the step of mounting the semiconductor chip 501 on the wiring board in order to form the first semiconductor device D1, first, as shown in FIG. Is formed on the surface on which the conductor wiring 201 and the protrusion 401 are formed. The insulator 7
For example, a thermosetting resin (B-stage resin) whose curing reaction has been advanced to an intermediate stage, such as NCF, is used.

Next, as shown in FIG. 13B, a semiconductor chip 501 is arranged on the insulator 7 and flip-chip mounted. At this time, for example, a gold bump (stud bump) 6 is formed on the external electrode 501A of the semiconductor chip 501, the semiconductor chip 501 is pressed, and the insulator 7 is pushed by the gold bump 6 to push the insulator 7 off. After the gold bump 6 and the conductor wiring 201 are brought into contact with each other, the conductor is heated to a predetermined temperature to completely cure the insulator (NCF) 7.

Thereafter, a continuity test, measurement of electrical characteristics, and the like of each semiconductor device are performed, and the semiconductor devices are singulated and only non-defective products are selected.

According to the above procedure, the first semiconductor device used for the semiconductor module of the first embodiment is formed. Although detailed description is omitted, the second semiconductor device D2
Also, the third semiconductor device D3 is formed by the same procedure as the method of forming the first semiconductor and the above procedure.

The semiconductor devices formed according to the above procedure are stacked in the following steps.

FIGS. 14 to 17 are schematic views for explaining the method of manufacturing the semiconductor module of the first embodiment.
FIGS. 14, 15, 16, and 17 are cross-sectional views of a process of stacking semiconductor devices and assembling a semiconductor module.

The first semiconductor device D1, the second semiconductor device D2, and the third semiconductor device D3 manufactured according to the above-described procedure have positioning pins 16 as shown in FIG.
A is laminated using the lamination stage 16 provided with A. At this time, as shown in FIG. 14, first, a base substrate BB formed in advance by a reel method is set on the stacking stage 16, and subsequently, the first semiconductor device D1, the second semiconductor device D2 , And the third semiconductor device D3 are sequentially stacked. At this time, as shown in FIGS. 14 and 15, by stacking the positioning pins 16A so as to be inserted into the openings H2 provided in the wiring board (insulating substrate 101) of the first semiconductor device D1, as shown in FIGS.
The alignment with the conductor wiring 11 of the base substrate BB is automatically performed.

Also, when the second semiconductor device D2 is stacked on the first semiconductor device D1, the positioning is performed in the opening H2 provided in the wiring board (insulating substrate 102) of the second semiconductor device D2. By stacking the pins 16A so as to be inserted, the protrusion 401 of the first semiconductor device D1 and the connection terminal 302 of the second semiconductor device D2 are automatically aligned as shown in FIGS. Done in At this time, the conductor wiring 11 of the base substrate BB is used.
And the connection terminal 301 of the first semiconductor device D1,
The protrusion 401 of the semiconductor device D1 and the second semiconductor device D
As shown in FIG. 15, the second connection terminals 302 are in a state where the plating films 8 formed on the respective surfaces are in contact with each other.

Thereafter, even when the third semiconductor device D3 and the cover plate CP are stacked, as shown in FIG. 16, the wiring board (insulating substrate 103) and the cover plate CP of the third semiconductor device D3 are stacked. The positioning is automatically performed by stacking the positioning pins 16A in the positioning openings H2 provided in the respective insulating substrates 13 so that the positioning pins 16A are inserted.

Next, while heating the laminate as shown in FIG. 16 to a predetermined temperature to melt the plating film 8 and applying a load in the vertical direction on the paper surface, the laminate shown in FIGS. As described above, the protrusion and the connection terminal, for example, the protrusion 401 of the first semiconductor device D1 and the connection terminal 302 of the second semiconductor device D2 are thermocompression-bonded. At this time, when, for example, tin plating is formed as the plating film 8, thermocompression bonding is performed by pressing for about 3 seconds in an atmosphere of 250 ° C. In the case of tin-silver alloy plating, 23
Thermocompression bonding is performed by pressing for about 2 seconds in an atmosphere of 0 ° C.

At this time, since the projections and the connection terminals are connected by thermocompression bonding, each of the semiconductor devices D1,
Even if the wiring boards D2 and D3 are warped, the connection can be surely made while returning the warping, and the connection failure can be reduced.

Then, the stacking stage 16 is removed,
As shown in FIG. 17, at the opening of the base substrate BB,
For example, when the ball-shaped terminals 12 such as Sn-Pb-based solder are connected, and the base substrate BB, the insulating substrate of each semiconductor device, and the cover plate CP are cut along the cutting line L2 into individual pieces, FIG. A semiconductor module as shown in FIG.

As described above, according to the semiconductor module of the first embodiment, by forming the conductor wiring having the projecting portion of the predetermined height on the wiring board used for laminating the semiconductor chips, When a semiconductor device in which the semiconductor chip is mounted on a wiring board is formed, and a second semiconductor device D2 is stacked on the first semiconductor device D1, the conductor wiring 201 of the first semiconductor device D1 and the second semiconductor device D2 The connection terminal 302 of the
1 and the plating film 8 can be directly connected. Therefore, like the conventional semiconductor module shown in FIG. 42, the conductor wiring 201 of the first semiconductor device D1 and the second
A semiconductor module can be manufactured without using a wiring board for connection to the connection terminal 302 of the semiconductor device D2, the number of components and the number of steps can be reduced, and the manufacturing cost of the semiconductor module can be reduced.

Further, the protrusion 4 of the first semiconductor device D1
01 and the connection terminal of the second semiconductor device D2, the number of connection points can be reduced as compared with the case where the connection is made via a conventional connection wiring board, so that a connection failure occurs. It is possible to reduce the probability and prevent the connection reliability from decreasing.

Further, the protrusions 401, 402, 403
Is formed by electrolytic copper plating, and tin plating or tin-silver alloy plating is formed on the surface, whereby the first
The protrusion 401 of the semiconductor device D1 and the second semiconductor device D
The two connection terminals 302 can be connected by thermocompression bonding. Therefore, even if the insulating substrate of each of the semiconductor devices has a warp, the connection can be made while returning the warp, so that the connection failure is reduced and the wiring board (insulating substrate) can be easily made thin. Accordingly, the thickness of the semiconductor module can be reduced.

Also, the protrusions 401, 402, 403
Is formed by electrolytic copper plating and the tip is flattened, so that the height of the protrusions can be easily made uniform. Therefore, the height of the semiconductor module can be made uniform, and the flatness of each stacked semiconductor device can be improved. Easiness is ensured.

(Embodiment 2) FIGS. 18 to 21 are schematic diagrams showing a schematic configuration of a semiconductor module according to Embodiment 2 of the present invention. FIG. 18 is a schematic sectional view showing the entire configuration of the semiconductor module. 19 is a schematic plan view of a first semiconductor device used for a semiconductor module, and FIG.
FIG. 21 is a cross-sectional view taken along the line C ′, and FIG. 21 is an enlarged cross-sectional view of the connecting portion in FIG.

In FIGS. 18 to 21, D1 is the first semiconductor device, 101 is the insulating substrate of the first semiconductor device, 201
Is a conductor wiring of the first semiconductor device, 401 is a projection of the first semiconductor device, 501 is a semiconductor chip of the first semiconductor device, 5
01A is an external electrode of the semiconductor chip of the first semiconductor device;
701 is a connection terminal (land) of the first semiconductor device, 180
1 is a copper plating film, 1801A is a via, D2 is a second semiconductor device, 102 is an insulating substrate of the second semiconductor device, 202 is a conductor wiring of the second semiconductor device, 402 is a projection of the second semiconductor device, and 502 is a second semiconductor device. 2 semiconductor chip of semiconductor device, 502
A is the external electrode of the semiconductor chip of the second semiconductor device, 170
2 is a connection terminal (land) of the second semiconductor device, 1802 is a copper plating film, 1802A is a via, D3 is a third semiconductor device, 103 is an insulating substrate of the third semiconductor device, and 203 is a third semiconductor device.
403, a semiconductor chip of the third semiconductor device; 503, a projection of the third semiconductor device;
Denotes an external electrode of the semiconductor chip of the third semiconductor device, 1703
Is a connection terminal (land) of the third semiconductor device, 1803 is a copper plating film, 1803A is a via, 6 is a gold bump, 7 is an insulator, 8 is a plating film, 901, 902, 903 are dummy wirings, and BB is a base substrate. 10 is an insulating substrate of the base substrate,
11 is a conductor wiring of the base substrate, 12 is a ball-shaped terminal, C
P is a cover plate, 13 is a cover plate substrate, 1
4 is a dummy terminal.

The semiconductor module according to the second embodiment is the same as the semiconductor module according to the first embodiment. As shown in FIG. 18, a first semiconductor device D1 having a semiconductor chip 501 mounted on a base substrate BB, Three semiconductor devices (semiconductor chips) of a second semiconductor device D2 on which the chip 502 is mounted and a third semiconductor device D3 on which the semiconductor chip 503 is mounted are stacked, and a cover plate CP is stacked on the third semiconductor device D3. This is a module having a three-dimensional structure.

Further, the semiconductor module of the second embodiment also
Similarly to the semiconductor module of the first embodiment, the semiconductor chip 501 of the first semiconductor device D1, the semiconductor chip 502 of the second semiconductor device D2, and the third semiconductor device D
The third semiconductor chip 503 includes, for example, a DRAM, an SRAM, and an EEPROM.
A memory chip such as an OM, and the three semiconductor chips 5
A memory module having a large capacity by stacking 01, 502, and 503 will be described as an example.

At this time, as shown in FIGS. 18, 19 and 20, the first semiconductor device D1 is
1 is provided with a predetermined pattern of conductor wiring 201 on the first main surface, and a connection electrically connected to the conductor wiring 201 on a second main surface of the insulating substrate 101 opposite to the first main surface. A semiconductor chip 501 is provided on a wiring board on which a terminal 1701 is provided, a projection 401 is provided at a predetermined position of the conductor wiring 201, and a plating film 8 is provided on the surface of the conductor wiring 201 including the projection 401. Flip chip mounted. Further, an opening (via hole) H1 provided on the surface of the connection terminal 1701 and the insulating substrate 101
The connection terminal 1701 is connected to the conductor wiring 201 by a copper plating film (via) 1801A provided on the inner wall of the via hole H1, for example. . Also, an external electrode (bonding pad) 501A of the semiconductor chip 501 is provided.
And the conductor wiring 201 are gold bumps (stud bumps)
The space between the wiring board and the semiconductor chip 501 is sealed with an insulator 7 such as NCF.

As shown in FIG. 19, a dummy wiring 901 not connected to the external electrode 501A of the semiconductor chip 501 is provided at a predetermined position on the insulating substrate 101. At this time, the projection 401 is also provided on the dummy wiring 901 similarly to the conductor wiring 201, and the plating film 8 is provided on the surfaces of the dummy wiring 901 and the projection 401. Although not shown, the insulating substrate 1 includes the dummy wiring 901.
In the lower portion of the via 180, similarly to the conductor wiring 201,
It is assumed that the connection terminal 1701 connected at 1A is provided.

The height T1 of the projection 401 provided on the conductor wiring 201 and the dummy wiring 901 is:
The height is substantially the same as the height T2 of the semiconductor chip 501 of the first semiconductor device D1 from the conductor wiring 201, and more specifically, the height T1 of the protrusion 401 and the insulating substrate of the connection terminal 1701. The semiconductor chip 501 is provided to be higher than the height T2 of the semiconductor chip 501 when the height T3 from the base 101 is added. For example, the thickness of the semiconductor chip 501 is 100 μm, and the gold bump 6 connecting the external electrode 501A of the semiconductor chip and the conductor wiring 201 is provided.
Is 30 μm, the height obtained by adding the height T1 of the protrusion 401 and the height T3 of the connection terminal 1701 is about 130 μm.

Although detailed description is omitted, the second
The semiconductor device D2 also has the same configuration as the first semiconductor device D1. For example, on the first main surface of the insulating substrate 102, the conductor wiring 202 and the dummy wiring 902 as shown in FIG. The conductor wiring 202
In addition, on the dummy wiring 902, a projection 402 having a height substantially equal to the height from the mounting surface of the semiconductor chip 502 of the second semiconductor device D2 is provided. In addition, the insulating substrate 102 of the second semiconductor device D2 is also provided under the conductor wiring 202 and the dummy wiring 901 through the via 1802A as shown in FIGS. A connection terminal 1702 is provided to be connected to.

The third semiconductor device D3 has the same configuration as the first semiconductor device D1.
A conductor wiring 203 and a dummy wiring 903 as shown in FIG. 5 are provided on a first main surface of the insulating substrate 103, and the conductor wiring 203 and the dummy wiring 903 are provided.
Above the semiconductor chip 503 of the third semiconductor device D3
Is provided at a height substantially equal to the height from the mounting surface. In addition, the insulating substrate 103 of the third semiconductor device D3 also has the via 1 under the conductor wiring 203 and the dummy wiring 903 as shown in FIG.
A connection terminal 1703 connected to the conductor wiring 103 via 803A is provided.

In the case where a plurality of memory chips are stacked as in the semiconductor module of the second embodiment, for example, each of the semiconductor wirings, such as an address signal, of the conductor wiring of each of the semiconductor devices may be used. Chips 501, 502, 5
The conductor wiring for inputting a signal common to 03 is pulled out to a position overlapping each other in a plane, and the protrusion and the connection terminal are provided in positions overlapping each other in a plane. Therefore, when the semiconductor devices D1, D2, and D3 are stacked, for example, the conductor wiring 201 of the first semiconductor device D1 may be stacked.
And the connection terminal 1702 of the second semiconductor device D2
8 and FIG. 21, the first semiconductor device D1
Are directly connected by the protrusion 401 and the plating film 8.
Similarly, the conductor wiring 202 of the second semiconductor device D2 and the connection terminal 1703 of the third semiconductor device D3 are
It is directly connected by the protrusion 402 of the semiconductor device D2 and the plating film 8.

The semiconductor devices D1, D2, D3
Of the first semiconductor device D1 and the second semiconductor device D
2, and the conductor wiring for identifying the third semiconductor device D3 and transmitting an individual signal to each of the semiconductor chips 501, 502, and 503 does not overlap in a planar manner as described in the first embodiment. Have been pulled out. At this time, for example, the connection terminal 1 for the chip select signal of the first semiconductor device D1 of the second semiconductor device D2
A dummy wiring 901 is provided at a position overlapping with the chip selection signal connection terminal 1703 of the third semiconductor device D3 and the connection terminal 1702 of the second semiconductor device D2. It is directly connected to the projection 401 of the semiconductor device D1 and the plating film 8. At this time, the conductor wiring 201 of the second semiconductor device D2 is used.
The upper protrusion 402 is directly connected to the connection terminal 1703 of the dummy wiring 903 of the third semiconductor device D3.

Further, the first semiconductor device D1 and the second semiconductor device D1,
The semiconductor device D2 and the third semiconductor device D3 are shown in FIG.
As shown in FIG. 8, it is laminated on the base substrate BB. The base substrate BB is, for example, a wiring substrate used for matching a connection terminal of each of the semiconductor devices and a wiring (terminal) on a mounting substrate on which the semiconductor module is mounted, or performing a grid conversion. As shown in (1), on the surface of the insulating substrate 10, for example, a conductor wiring 11 having a matching pattern is provided. The insulating substrate 10 is provided with an opening as shown in FIG. 18 at a position corresponding to a wiring (terminal) on a mounting substrate on which the semiconductor module is mounted. -Pb
A ball-shaped terminal 12 such as a system solder is connected.

A cover plate CP is provided on the third semiconductor device D3, as shown in FIG. The cover plate CP is used for protecting the semiconductor chip 503 of the third semiconductor device D3, and as shown in FIG. 9, for example, a conductor of the third semiconductor device D3 on the surface of the insulating substrate 13. The dummy terminal 14 is provided at a position that overlaps the projection 203 of the wiring 203 and the dummy wiring 903 in a plane.
The projection 403 of the semiconductor device D3 and the dummy terminal 14 are directly connected.

The manufacturing method of the semiconductor module of the second embodiment is also the same as the manufacturing method of the semiconductor module of the first embodiment. The steps are divided into a step of mounting each semiconductor device by mounting a semiconductor chip on a board, a step of stacking each semiconductor device on the base substrate, and a step of connecting the base substrate and each semiconductor device. Hereinafter, the method of manufacturing the semiconductor module according to the second embodiment will be described step by step along the above-described steps. However, detailed description of the same parts as those in the method of manufacturing the semiconductor module of the first embodiment will be omitted.

FIGS. 22 and 23 are schematic diagrams for explaining a method of manufacturing a wiring board used for the semiconductor module of the second embodiment. FIGS. 22 (a), 22 (b), and 22
(C), FIG. 23 (a), and FIG. 23 (b)
It is a schematic cross section in each manufacturing process of the wiring board used for the said 1st semiconductor device D1.

As a method of manufacturing a semiconductor module according to the second embodiment, a process of forming a wiring board used for each of the semiconductor devices D1, D2, and D3 will be described. First, a wiring board used for each of the semiconductor devices will be described. Are formed in the same process, the process for forming the wiring board used in the first semiconductor device D1 will be described as an example. The wiring substrate is manufactured by a reel method using a tape-shaped insulating substrate that is long in one direction, such as a wiring substrate (tape carrier) used for a tape carrier package.

First, as shown in FIG. 22A, a first conductor film 201 'is formed on a first main surface of a tape-shaped insulating substrate 101, and a second conductor film 201' is formed on a second main surface of the insulating substrate 101. Membrane 1
After forming an opening (sprocket hole) H2 used for positioning or the like by punching using a mold or laser processing using a carbon dioxide laser or the like at a predetermined position of the laminated plate on which 701 ′ is formed, for example, An opening (via hole) H1 is formed from the second conductive film 1701 'side. At this time, the insulating substrate 101 is, for example, a polyimide tape having a thickness of about 50 μm, or a glass cloth base epoxy resin laminate (glass epoxy substrate) in which a cloth woven of glass fiber is impregnated with an epoxy resin. Used, the first conductive film 201 'and the second conductive film 170
For 1 ′, a copper foil having a thickness of about 12 μm is used.

Next, as shown in FIG. 22B, an electrolytic copper plating film 1801 is formed on the surface of the second conductor film 1701 ′ and inside the via hole H1. At this time, the first conductive film 201 ′ and the second conductive film 1701 ′ are formed by the electrolytic copper plating film (via) formed inside the via hole H1.
It is electrically connected by 1801A.

Next, as shown in FIG. 22C, a resist (plating resist) 15 having a predetermined area opened is formed on the first conductive film 201 ', and the first conductive film 201' is formed by, for example, electrolytic copper plating. The protrusion 401 is formed on the conductor film 201 '. At this time, although not shown, a plating resist is formed on the surface of the electrolytic copper plating film 1801. The protrusion 401 is formed to have a height substantially equal to the height from the mounting surface of the semiconductor chip to be mounted, that is, a thickness (height) of about 130 μm.

At this time, since the protrusion 401 is formed by electrolytic copper plating, after the formation, for example, as described in the first embodiment, a variation ΔT occurs in the height of the protrusion 401, The tip becomes concave or convex. For this reason, after the protrusions 401 are formed and the plating resist 15 is removed, the height of the protrusions 401 is made uniform and the tip is flattened by using, for example, a roll method or a press method.

Next, as shown in FIG. 23A, the first conductor film 201 'is etched to form the conductor wiring 201 and the dummy wiring 901 having the pattern shown in FIG. The second conductor film 1701 'and the electrolytic copper plating film 1801 are subjected to an etching process to form connection terminals (lands) 1701 with other semiconductor devices.

Next, as shown in FIG. 23B, plating is performed on the surfaces of the conductor wiring 201 and the dummy wiring 901 including the protrusion 401 and the surface of the connection terminal 1701 (electrolytic copper plating film 1801). A film 8 is formed.
The plating film 8 is formed using, for example, tin or a tin-silver alloy. For example, when formed by electroless tin plating, the plating film 8 is formed to have a thickness of about 0.5 μm to 1 μm. Also, instead of the electroless tin plating, for example,
When forming tin silver alloy plating by electroplating,
0.5% tin-silver alloy having a silver weight percentage of about 3.5%
It is formed in a thickness of not less than μm and not more than 5 μm. When formed by electrolytic tin plating, the thickness is 0.5 μm or more and 5 μm or more.
It is formed as follows.

By the above procedure, the first semiconductor device D
The wiring board used for 1 is formed. Although detailed description is omitted, the wiring board used for the second semiconductor device D2 and the wiring board used for the third semiconductor device D3 are formed in the same procedure as the above procedure.

After forming each of the wiring boards according to the above procedure, a semiconductor chip is mounted on the wiring board to form a semiconductor device. Here, a method of forming the first semiconductor device D1 using the wiring board will be described as an example.

FIGS. 24A and 24B are schematic diagrams for explaining a method of manufacturing a semiconductor device used in the semiconductor module of the second embodiment. FIGS. 24A and 24B show the first semiconductor device, respectively. It is sectional drawing of each process which forms.

In the step of mounting a semiconductor chip on the wiring board to form the first semiconductor device D1,
First, as shown in FIG.
The chip mounting insulator 7 is formed on the surface on which the semiconductor chip is mounted, in other words, on the surface on which the conductor wiring 201 and the protrusion 401 are formed. In the insulator 7,
For example, a thermosetting resin, such as NCF, having a curing reaction advanced to an intermediate stage is used.

Next, as shown in FIG. 24B, a semiconductor chip 501 having gold bumps (stud bumps) 6 formed on external electrodes (bonding pads) 501A is disposed on the wiring board, and After the wiring 201 and the gold bumps 6 of the semiconductor chip 6 are aligned and pressed against each other, they are heated to a predetermined temperature to completely cure the insulator (NCF) 7.

Thereafter, a continuity test, measurement of electrical characteristics, and the like of each semiconductor device are performed, and the semiconductor devices are singulated and only non-defective products are selected.

According to the above procedure, the first semiconductor device D1 used for the semiconductor module of the second embodiment is formed. Although not described in detail, the second semiconductor device D2 and the third semiconductor device D3 are also formed by the same method as the method of forming the first semiconductor device D1 and the above-described procedure.

Each semiconductor device formed by the above procedure is stacked in the following steps.

FIGS. 25 to 28 are schematic views for explaining a method of manufacturing a semiconductor module according to the first embodiment.
FIG. 25, FIG. 26, FIG. 27, and FIG. 28 are cross-sectional views of a process of assembling a semiconductor module by stacking semiconductor devices.

As shown in FIG. 25, the first semiconductor device D1, the second semiconductor device D2, and the third semiconductor device D3 manufactured according to the above-described procedure are provided with a positioning pin 16A. The layers are stacked using the stage 16. At this time, first, the base substrate BB formed in advance by the reel method is placed on the lamination stage 16, and subsequently, the first semiconductor device D1 is laminated. At this time, the wiring board (insulating substrate 1) of the first semiconductor device D1 is used.
01), the positioning pins 16A are laminated so as to be inserted into the positioning openings H2,
As shown in FIGS. 25 and 26, the first semiconductor device D
Positioning of the first connection terminal 1701 and the conductor wiring 11 of the base substrate BB is automatically performed. After that,
As shown in FIG. 25, when the positioning pins 16A are inserted into openings H2 provided in the wiring board (insulating substrate 102) of the second semiconductor device D2, the wiring of the first semiconductor device D1 is formed. The alignment between the projection 401 of the plate and the connection terminal 1702 of the wiring board of the second semiconductor device D2 is automatically performed. At this time, the base substrate BB
Conductor wiring 11 and connection terminal 1 of the first semiconductor device D1
701, the projection 401 of the first semiconductor device D1 and the connection terminal 1702 of the second semiconductor device D2 are in a state in which the plating films 8 formed on the respective surfaces are in contact as shown in FIG. become.

Subsequently, as shown in FIG. 27, the positioning pins 16A are inserted into the openings H2 provided in the wiring board (insulating substrate 103) of the third semiconductor device D3 and the insulating substrate 13 of the cover plate CP. After laminating so as to insert, while heating the plating film 8 at a predetermined temperature and melting the plating film 8, for example, by applying a load in the vertical direction on the paper surface, as shown in FIG. A terminal, for example, the protrusion 401 of the first semiconductor device D1 and the connection terminal 1702 of the second semiconductor device D2 are thermocompression bonded. At this time, when, for example, tin plating is formed as the plating film 8, thermocompression bonding is performed by pressing for about 3 seconds in an atmosphere of 250 ° C. In the case of tin-silver alloy plating, thermocompression bonding is performed by pressing for about 2 seconds in an atmosphere at 230 ° C.

At this time, since the connection is made by thermocompression bonding, even if the insulating substrate of each of the semiconductor devices has a warp, the connection can be surely made while returning the warp.
Connection failure can be reduced.

After that, the stacking stage 16 is removed,
As shown in FIG. 28, at the opening of the base substrate BB,
For example, the ball-shaped terminals 12 such as Sn-Pb solder are connected, and the base substrate BB and the semiconductor devices D1, D
The semiconductor module as shown in FIG. 18 is obtained by cutting the insulating substrate of D2 and the cover plate CP into individual pieces by cutting along the cutting line L2.

As described above, according to the semiconductor module of the second embodiment, similarly to the semiconductor module of the first embodiment, the protrusion having a predetermined height is formed on the wiring board used for stacking the semiconductor chips. When a semiconductor device having the semiconductor chip mounted on the wiring board is formed by forming a conductor wiring having the following structure, and the second semiconductor device D2 is stacked on the first semiconductor device D1, the first semiconductor device D1 Conductor wiring 201 and connection terminal 1 of the second semiconductor device D2
702 can be directly connected by the protrusion 401 on the conductor wiring 201 and the plating film 8. for that reason,
As in the conventional semiconductor module shown in FIG. 42, a semiconductor module can be manufactured without using a wiring board for connecting the conductor wiring 201 of the first semiconductor device D1 and the connection terminal 1702 of the second semiconductor device D2. The number of components and the number of steps can be reduced, and the manufacturing cost of the semiconductor module can be reduced.

Further, the projection 4 of the first semiconductor device D1
01 and the connection terminal 1702 of the second semiconductor device D2, the number of connection points can be reduced as compared with the case where connection is made via a conventional connection wiring board, so that a connection failure occurs. Connection probability is reduced, and a decrease in connection reliability can be prevented.

The projections 401, 402, 403
Is formed by electrolytic copper plating, and a plating film 8 such as tin plating or tin silver alloy plating is formed on the surface, for example, to connect the projection 401 of the first semiconductor device D1 to the second semiconductor device D2. The terminal 1702 can be connected by thermocompression bonding. Therefore, each of the semiconductor devices D1, D2,
Even if the wiring board (insulating substrate) of D3 is warped, the connection can be made while returning the warping.
In addition to reducing connection failure, the wiring board (insulating substrate)
The thickness of the semiconductor module can be easily reduced, and the semiconductor module can be reduced in thickness.

The projections 401, 402, 403
Is formed by electrolytic copper plating, and the tip is flattened, so that the height of the projections can be easily made uniform. Therefore, the height of the semiconductor module can be made uniform, and each of the semiconductor devices D1, D2, It is easy to ensure the flatness of D3.

(Embodiment 3) FIGS. 29 to 32 are schematic views showing a schematic configuration of a semiconductor module according to Embodiment 3 of the present invention. FIG. 29 is a schematic sectional view showing the entire configuration of the semiconductor module. 30 is a schematic plan view of a second semiconductor device used for the semiconductor module, and FIG.
FIG. 32 is an enlarged cross-sectional view of the connecting portion in FIG. 29 along the line D ′.

29 to 32, D1 is the first semiconductor device, 101 is the insulating substrate of the first semiconductor device, 201
Is a conductor wiring of the first semiconductor device, 501 is a semiconductor chip of the first semiconductor device, 501A is an external electrode of the semiconductor chip of the first semiconductor device, 1701 is a connection terminal (land) of the first semiconductor device, 1801 is a copper plating film , 1801A is a via, D2 is a second semiconductor device, 102 is an insulating substrate of the second semiconductor device, 102A is a concave portion (spot) of the insulating substrate, 20A
2 is a conductor wiring of the second semiconductor device, 502 is a semiconductor chip of the second semiconductor device, 502A is an external electrode of the semiconductor chip of the second semiconductor device, 1702 is a connection terminal (land) of the second semiconductor device, and 1802 is copper plating Film, 1802A is a via, D3 is a third semiconductor device, 103 is an insulating substrate of the third semiconductor device, 103A is a concave portion (spot) of the insulating substrate, 20
3 is a conductor wiring of the third semiconductor device, 503 is a semiconductor chip of the third semiconductor device, 503A is an external electrode of the semiconductor chip of the third semiconductor device, 1703 is a connection terminal (land) of the third semiconductor device, and 1803 is copper plating Film, 1803A is a via, 6 is a gold bump, 7 is an insulator, 8 is a plating film, 90
1, 902, 903 are dummy wirings, BB is a base substrate,
10 is an insulating substrate of the base substrate, 11 is a conductor wiring of the base substrate, 12 is a ball-shaped terminal, CP is a cover plate, 1
3 is a cover plate substrate, and 14 is a dummy terminal.

The semiconductor module of the third embodiment is the same as the semiconductor module of the first embodiment. As shown in FIG. 29, a first semiconductor device D1 having a semiconductor chip 501 mounted on a base substrate BB, Three semiconductor devices (semiconductor chips) of a second semiconductor device D2 on which the chip 502 is mounted and a third semiconductor device D3 on which the semiconductor chip 503 is mounted are stacked, and a cover plate CP is stacked on the third semiconductor device D3. This is a module with a three-dimensional structure.

The semiconductor module of the third embodiment is also
Similarly to the semiconductor modules of the first and second embodiments, the semiconductor chip 501 of the first semiconductor device D1 and the second
The semiconductor chip 502 of the semiconductor device D2 and the semiconductor chip 503 of the third semiconductor device D3 are, for example, DRAM,
A memory module having a large capacity by stacking the three semiconductor chips 501, 502, and 503 as a memory chip such as an SRAM or an EEPROM will be described as an example.

At this time, as shown in FIG. 29, in the first semiconductor device D1, a conductor wiring 201 having a predetermined pattern is provided on the first main surface of the insulating substrate 101, and the first A semiconductor chip 501 is flip-chip mounted on a wiring board provided with a connection terminal 1701 electrically connected to the conductor wiring 201 on a second main surface opposite to the main surface. A copper plating film 1801 is provided on the surface of the connection terminal 1701 and on the inner wall of the opening (via hole) provided in the insulating substrate 101.
The connection terminal 1701 is connected to the conductor wiring 2 by a copper plating film (via) 1801A provided on the inner wall of the via hole.
01 is electrically connected. At this time, the external electrodes (bonding pads) 501 of the semiconductor chip 501 are formed.
A and the conductor wiring 201 are connected by gold bumps (stud bumps) 6, and the space between the wiring board and the semiconductor chip 501 is sealed with an insulator 7 such as NCF.

As described in the first and second embodiments, the dummy wiring 901 not connected to the external electrode 501 of the semiconductor chip 501 is provided at a predetermined position on the insulating substrate 101. The plating film 8 is provided on the surface of the 901. Although not shown, the insulating substrate 1 includes the dummy wiring 90.
1, the connection terminal 1701 connected by the via 1801A is provided similarly to the conductor wiring 201.

Further, the second semiconductor device D2 is the same as that of FIG.
9, FIG. 30 and FIG. 31, the insulating substrate 1
02 on the first main surface of the second conductive layer 202,
And a dummy wiring 902 are provided. The insulating substrate 102 of the second semiconductor device D2 is electrically connected to the conductor wiring 102 or the dummy wiring 902 below the conductor wiring 202 and the dummy wiring 902 as shown in FIG. Connection terminal 1702 is provided. At this time, for example, a copper plating film 1802 is provided on the inner wall of the connection terminal 1702 and the opening (via hole) H1 of the insulating substrate 102, and the connection terminal 1702 is formed on the inner wall of the via hole H1. It is connected to the conductor wiring 202 by the provided copper plating film (via) 1802A.

In the wiring board of the second semiconductor device D2, as shown in FIG. 31, the insulating substrate 202 has a concave portion (counterbore) in a portion overlapping the semiconductor chip 501 of the first semiconductor device D1 in a plane. ) Is provided. At this time, the depth T4 of the concave portion 102A is provided so as to be substantially the same as the height T2 from the conductor wiring 201 of the semiconductor chip 501 of the first semiconductor device D1, and more specifically, The height T5, which is the sum of the depth T4 of the recess 102A and the height (thickness) of the connection terminal 1702 portion, is set to be higher than the height T2 of the semiconductor chip. At this time, when the second semiconductor device D2 is stacked on the first semiconductor device D1, as shown in FIGS. 29 and 32, the semiconductor chip 501 of the first semiconductor device D1 is replaced with the semiconductor chip 501 of the second semiconductor device. In this state, the conductor wiring 201 of the first semiconductor device D1 is directly connected to the connection terminal 1702 of the second semiconductor device D2.

The third semiconductor device D3 has the same configuration as the second semiconductor device D2.
The conductor wiring 203 and the dummy wiring 903 as shown in FIG. 5 are provided on the first main surface of the insulating substrate 103, and the second main surface of the insulating substrate 103 is provided via the via 1803A. A connection terminal 1703 connected to the conductor wiring 203 is provided. In addition, the insulating substrate 103 of the third semiconductor device D3 is also provided with a recess (spot) 103A having a depth substantially equal to the height from the mounting surface of the semiconductor chip 502 of the second semiconductor device D2. When the third semiconductor device D3 is stacked on the second semiconductor device D2, as shown in FIGS. 29 and 32, the semiconductor chip 502 of the second semiconductor device D2 is housed in the recess 103A of the third semiconductor device. In this state, the conductor wiring 202 of the second semiconductor device D1 is directly connected to the connection terminal 1703 of the third semiconductor device D3.

In the case where a plurality of memory modules are stacked as in the semiconductor module of the third embodiment, the conductor wiring of each of the semiconductor devices D1, D2, and D3 includes, for example, an address signal such as an address signal. Semiconductor chips 501 and 5
As described in the first embodiment, the conductor wiring for inputting a common signal to the second and third wirings 503 is drawn out to a position where they overlap in a plane, and the protrusions and the connection terminals are provided in positions where they overlap in a plane. Have been.

The semiconductor devices D1, D2, D3
Among the conductor wirings described above, for example, like the chip select signal, the conductor wirings for identifying the semiconductor chips 501, 502, and 503 and transmitting individual signals are respectively provided as described in the first embodiment. It is pulled out so that it does not overlap in a plane. At this time, for example, the connection terminal 1702 of the first semiconductor device D1 for the chip select signal of the second semiconductor device D2 and the connection terminal 1703 of the third semiconductor device D3 for the chip select signal are planarly overlapped. A dummy wiring 901 is provided at the position, and the connection terminal 1702 of the second semiconductor device D2 is directly connected to the protrusion 401 of the first semiconductor device D1 and the plating film 8. At this time, the projection 402 on the conductor wiring 201 of the second semiconductor device D2 is
Connection terminal 1703 of dummy wiring 903 of semiconductor device D3
Directly connected to

In addition, the first semiconductor device D1, the second
The semiconductor device D2 and the third semiconductor device D3 are shown in FIG.
As shown in FIG. 9 and FIG. 32, they are stacked on the base substrate BB. The base substrate BB is, for example, a wiring substrate used for matching a connection terminal of each of the semiconductor devices and a wiring (terminal) on a mounting substrate on which the semiconductor module is mounted, or performing a grid conversion. As shown in (1), on the surface of the insulating substrate 10, for example, a conductor wiring 11 having a matching pattern is provided. The insulating substrate 10 is provided with an opening at a position corresponding to the wiring (terminal) on the mounting substrate on which the semiconductor module is mounted. As shown in FIG. A ball-shaped terminal 12 such as a -Pb-based solder is connected.

Further, a cover plate CP is provided on the third semiconductor device D3 as shown in FIGS. 29 and 32. The cover plate CP is connected to the third
For the purpose of protecting the semiconductor chip 503 of the semiconductor device D3 and the like, as shown in FIG. 9, for example, the conductor wiring 2 of the third semiconductor device D3 on the surface of the insulating substrate 13
The dummy terminal 14 is provided at a position that overlaps the projection portion 403 of the dummy wiring 03 and the dummy wiring 903 in a plane.
Further, as shown in FIGS. 29 and 32, the insulating substrate 13 of the cover plate CP used in the semiconductor module of the third embodiment has the semiconductor chip 50 of the third semiconductor device D3.
3 is provided with a depth substantially equal to the height from the mounting surface of the third semiconductor device D3. When the semiconductor chip 503 of the third semiconductor device D3 is housed in the concave portion 13A when the layers are stacked, The protrusion 403 of the third semiconductor device D3 and the dummy terminal 14 are directly connected.

The manufacturing method of the semiconductor module of the third embodiment is the same as the manufacturing method of the semiconductor module of the first embodiment. A semiconductor chip is mounted on a board to form each semiconductor device, a semiconductor device is stacked on the base substrate, and a semiconductor device is connected to the base substrate.
Hereinafter, the method of manufacturing the semiconductor module according to the third embodiment will be described step by step along the above-described steps. However,
The detailed description of the same parts as those in the method of manufacturing the semiconductor module according to the first and second embodiments will be omitted.

FIG. 33 is a schematic view for explaining a method of manufacturing a wiring board used for the semiconductor module of the third embodiment. FIGS. 33 (a), 33 (b), and 33 (c) It is a typical sectional view in each manufacturing process of a wiring board used for the first semiconductor device D1.

As a method of manufacturing a semiconductor module according to the third embodiment, first, a step of forming a wiring board used in the first semiconductor device D1 will be described. The wiring board is, for example,
Like a wiring board (tape carrier) used in a tape carrier package, it is manufactured by a reel method using a tape-shaped insulating substrate that is long in one direction.

First, as shown in FIG. 33 (a), a first conductor film 201 'is formed on a first main surface of a tape-shaped insulating substrate 101, and a second conductor film 201' is formed on a second main surface of the insulating substrate 101. Membrane 1
After forming an opening (sprocket hole) H2 used for positioning or the like by punching using a mold or laser processing using a carbon dioxide laser or the like at a predetermined position of the laminated plate on which 701 ′ is formed, for example, A via hole H1 is formed from the second conductor film 1701 'side. At this time, the insulating substrate 101 has a thickness of, for example, 50 μm.
The first conductive film 20 is made of a polyimide tape, a glass cloth-based epoxy resin laminate (glass epoxy substrate) in which a glass cloth is impregnated with an epoxy resin, or the like.
1 ′ and the second conductive film 1701 ′ have a thickness of 12 μm.
A copper foil of about m is used.

Next, as shown in FIG. 33B, an electrolytic copper plating film 1801 is formed on the surface of the second conductor film 1701 'and inside the via hole H1. At this time, the first conductive film 201 ′ and the second conductive film 1701 ′ are formed by the electrolytic copper plating film (via) formed inside the via hole H1.
It is electrically connected by 1801A.

Next, as shown in FIG. 33C, the first conductor film 201 'is subjected to an etching process to form the conductor wiring 201 and the dummy wiring 901 having the pattern shown in FIG. The second conductor film 1701 ′ and the electrolytic copper plating film 1801 are subjected to an etching process to connect the terminal (land) 1701 with the conductor wiring 11 of the base substrate BB.
To form Thereafter, although not shown, a plating film 8 is formed on the surfaces of the conductor wiring 201 and the dummy wiring 901 and on the surface of the connection terminal 1701 (electrolytic copper plating film 1801). The plating film 8 is, for example,
Formed using tin or tin-silver alloy, for example, when formed by electroless tin plating, the thickness is 0.5 μm to 1 μm.
m. In the case where, for example, a tin-silver alloy plating is formed by electroplating instead of the electroless tin plating, the weight percentage of silver is 3.5%.
A tin-silver alloy having a thickness of about 0.5 μm or more and 5 μm or less is formed. In the case of forming by electrolytic tin plating, the thickness is set to be 0.5 μm or more and 5 μm or less.

By the above procedure, the first semiconductor device D
The wiring board used for 1 is formed.

FIGS. 34 to 36 are schematic views for explaining a method of manufacturing a wiring board used for the semiconductor module of the third embodiment. FIGS. 34 (a), 34 (b), and 35
(A), FIG. 35 (b), and FIG. 36 are cross-sectional views of respective manufacturing steps of a wiring board used for the second semiconductor device D2.

The wiring board used for the second semiconductor device D2 and the third semiconductor device D3 stacked on the first semiconductor device D1 is formed in a different process from the wiring board of the first semiconductor device D1. Next, a method for forming a wiring board of the second semiconductor device D2 will be described as an example. The wiring board used in the second semiconductor device D2 is also manufactured by a reel method using a tape-shaped insulating substrate that is long in one direction, such as a tape carrier.

In the wiring board used for the second semiconductor device D2, first, as shown in FIG. 34A, a third conductor film 202 'is formed on a first main surface of a tape-shaped insulating substrate 102.
A fourth conductive film 1702 ′ is formed on the second main surface of the insulating substrate 102.
After forming an opening (sprocket hole) H2 used for positioning or the like at a predetermined position of the laminated plate formed by punching using a mold or laser processing using a carbon dioxide gas laser, for example, A via hole H1 is formed from the four conductor film 1702 'side. At this time, as the insulating substrate 102, for example, a polyimide tape having a thickness of about 200 μm, a glass cloth-based epoxy resin laminate (glass epoxy substrate) in which a glass cloth is impregnated with an epoxy resin, or the like is used. A copper foil having a thickness of about 12 μm is used for the third conductive film 202 ′ and the fourth conductive film 1702 ′.

Next, as shown in FIG. 34B, an electrolytic copper plating film 1802 is formed on the surface of the fourth conductor film 1702 ′ and inside the via hole H1. At this time, the third conductive film 202 ′ and the fourth conductive film 1702 ′ are formed by the electrolytic copper plating film (via) formed inside the via hole H1.
It is electrically connected by 1802A.

Next, as shown in FIG. 35A, the third conductor film 202 'is subjected to an etching process to form the conductor wiring 202 and the dummy wiring 902 having the pattern shown in FIG. Then, the fourth conductor film 1702 'and the electrolytic copper plating film 1802 are etched to form connection terminals (lands) 1702 with other semiconductor devices.

Next, as shown in FIG. 35B, a plating film 8 is formed on the surfaces of the conductor wiring 202 and the dummy wiring 902 and on the surface of the connection terminal 1702 (electrolytic copper plating film 1802). The plating film 8 is formed using, for example, tin or a tin-silver alloy. For example, when formed by electroless tin plating, the plating film 8 is formed to have a thickness of about 0.5 μm to 1 μm. Further, in the case where, for example, a tin-silver alloy plating is formed by electroplating instead of the electroless tin plating, the weight percentage of silver is 3.
A tin-silver alloy of about 5% is formed in a thickness of 0.5 μm or more and 5 μm or less. Also, when forming by electrolytic tin plating,
It is formed so that the thickness is 0.5 μm or more and 5 μm or less.

Next, as shown in FIG. 36, a concave portion 102A having a depth T4 is formed at a predetermined position on the surface of the insulating substrate 102 where the connection terminals 1702 are formed. The recess 102A is formed on the insulating substrate 1 using a router, for example.
02 is formed by cutting.

After forming the wiring board used for each of the semiconductor devices according to the above procedure, a semiconductor chip is mounted on the wiring board to form a semiconductor device. Although not described, the wiring board used for the third semiconductor device D3 is formed in the same procedure as the wiring board used for the second semiconductor device D2.

FIG. 37 is a schematic diagram for explaining a method for manufacturing a semiconductor device used for the semiconductor module of the third embodiment. FIG. 37A is a cross-sectional view for explaining a method for manufacturing the first semiconductor device D1. FIG. 37B is a cross-sectional view for explaining the method for manufacturing the second semiconductor device D2.

In the step of mounting a semiconductor chip on the wiring board to form the first semiconductor device D1,
As shown in FIG. 37 (a), the insulating substrate 101
After forming the insulator 7 on the surface on which the semiconductor chip is mounted, in other words, on the surface on which the conductor wiring 201 is formed,
A semiconductor chip 501 having gold bumps (stud bumps) 6 formed thereon is arranged on an external electrode (bonding pad) 501A, and the conductive wiring 201 and the gold bumps 6 of the semiconductor chip 6 are aligned and pressed. At this time, the insulator 7 is made of, for example, a thermosetting resin whose curing reaction is advanced to an intermediate stage, such as NCF, and is heated to a predetermined temperature when the semiconductor chip 501 is pressed into contact with the insulator 7. The insulator (NCF) 7 is completely cured.

In the step of mounting a semiconductor chip on the wiring board to form the second semiconductor device D2, as shown in FIG.
After the insulator 7 was formed on the surface on which the semiconductor chip was mounted, in other words, the surface on which the conductor wiring 202 was formed, a gold bump (stud bump) 6 was formed on the external electrode (bonding pad) 502A. Semiconductor chip 50
2 and the conductor wiring 201 and the semiconductor chip 6
The gold bumps 6 are aligned and pressed. At this time,
The insulator 7 is made of, for example, a thermosetting resin whose curing reaction has been advanced to an intermediate stage, such as NCF, and is heated to a predetermined temperature when the semiconductor chip 502 is pressed against the insulator ( NCF) 7 is completely cured. Although not described, the third semiconductor device is manufactured in the same procedure as the second semiconductor device.

After that, a continuity test, a measurement of electrical characteristics, and the like of each semiconductor device are performed to separate the semiconductor devices, and only non-defective products are selected.

According to the above procedure, the first semiconductor device D1, the second semiconductor device D2, and the third semiconductor device D3 used in the semiconductor module of the third embodiment are formed. Are laminated in the next step.

FIGS. 38 to 41 are schematic views for explaining a method of manufacturing a semiconductor module according to the third embodiment.
38, 39, 40, and 41 are cross-sectional views of a process of stacking semiconductor devices and assembling a semiconductor module.

As shown in FIG. 38, the first semiconductor device D1, the second semiconductor device D2, and the third semiconductor device D3 manufactured according to the above-described procedure have the positioning pins 16
A is laminated using the lamination stage 16 provided with A. At this time, first, the base substrate BB formed in advance by the reel method is placed on the lamination stage 16, and subsequently, the first semiconductor device D1 is laminated. At this time, the wiring board (insulating substrate 10) of the first semiconductor device D1 is used.
By stacking the positioning pins 16A so as to be inserted into the positioning openings H2 provided in 1), as shown in FIGS. 38 and 39, the first semiconductor device D1 is stacked.
Connection terminal 1701 and the conductor wiring 1 of the base substrate BB
1 is automatically performed. Thereafter, when the positioning pins 16A are further inserted into the openings H2 provided in the wiring board (insulating substrate 102) of the second semiconductor device D2, as shown in FIG. 38, the first semiconductor device D1 is stacked. The position of the projection 401 of the wiring board and the connection terminal 1702 of the wiring board of the second semiconductor device D2 are automatically adjusted. At this time, the conductor wiring 11 of the base substrate BB and the connection terminal 170 of the first semiconductor device D1 are connected.
1. The protrusion 401 of the first semiconductor device D1 and the second
As shown in FIG. 39, the connection terminals 1702 of the semiconductor device D2 come into contact with the plating films 8 formed on the respective surfaces.

Subsequently, as shown in FIG.
An opening H2 provided in the wiring board (insulating substrate 103) of the semiconductor device D3 and the insulating substrate 13 of the cover plate CP.
After stacking so that the positioning pins 16A are inserted into the plating film, by heating to a predetermined temperature and melting the plating film 8, for example, by applying a load in the vertical direction of the drawing,
As shown in FIG. 21, the protrusion and the connection terminal, for example, the protrusion 401 of the first semiconductor device D1 and the connection terminal 1702 of the second semiconductor device D2 are thermocompression-bonded. At this time, when, for example, tin plating is formed as the plating film 8, thermocompression bonding is performed by pressing for about 3 seconds in an atmosphere of 250 ° C. In the case of tin-silver alloy plating, thermocompression bonding is performed by pressing for about 2 seconds in an atmosphere at 230 ° C.

At this time, since the connection is made by thermocompression bonding, even if the insulating substrate of each of the semiconductor devices has a warp, the connection can be surely made while returning the warp.
Connection failure can be reduced.

After that, the stacking stage 16 is removed,
As shown in FIG. 41, at the opening of the base substrate BB,
For example, the ball-shaped terminals 12 such as Sn-Pb solder are connected, and the base substrate BB and the semiconductor devices D1, D
When the wiring board (insulating substrate) 2 and the cover plate CP are cut along the cutting line L2 into individual pieces, a semiconductor module as shown in FIG. 20 is obtained.

As described above, according to the semiconductor module of the third embodiment, a concave portion (a counterbore) having a predetermined depth is formed in a wiring board used for stacking semiconductor chips.
When a semiconductor device in which the semiconductor chip is mounted on the wiring board is formed, and the second semiconductor device D2 is stacked on the first semiconductor device D1, the concave portion 102 of the second semiconductor device D2 is formed.
By allowing the semiconductor chip 501 of the first semiconductor device D1 to be accommodated in A, the conductor wiring 201 of the first semiconductor device D1 can be directly connected to the connection terminal 1702 of the second semiconductor device D2. it can. for that reason,
Unlike the conventional semiconductor module shown in FIG. 42, the connection between the conductor wiring 201 of the first semiconductor device D1 and the connection terminal 1702 of the second semiconductor device D2 is performed without using the first connection wiring board SB1. A semiconductor module can be manufactured, the number of parts and the number of steps can be reduced, and the manufacturing cost of the semiconductor module can be reduced.

Also, the conductor wiring 201 of the first semiconductor device D1 and the connection terminal 1702 of the second semiconductor device D2
By directly connecting to the device, the number of connection points can be reduced as compared with the case where connection is made via a conventional connection wiring board, so that the probability of occurrence of connection failure is reduced and connection reliability is reduced. Can be prevented.

Further, since the concave portion 102A for accommodating the semiconductor chip of the first semiconductor device is formed like the insulating substrate 102 of the second semiconductor device D2, the portion where the semiconductor chip of each semiconductor device is mounted is formed. It is easy to make the insulating substrate thinner, and the semiconductor module can be made thinner.

As described above, the present invention has been specifically described based on the above-described embodiment. However, the present invention is not limited to the above-described embodiment, and may be variously modified without departing from the gist thereof. Of course.

For example, in the semiconductor module of each of the above embodiments, the semiconductor chip 501 of the first semiconductor device D1
As the semiconductor chip 502 of the second semiconductor device D2 and the semiconductor chip 503 of the third semiconductor device D3, a memory module having a large capacity by stacking memory chips such as a DRAM has been described as an example, but is not limited thereto. As each of the semiconductor chips, a module (multi-chip package) that is systemized by combining a CPU, a communication control chip, and the like in addition to the DRAM can also be manufactured. At this time, in the semiconductor modules of the first and second embodiments, the time taken for electrolytic copper plating when forming the protrusions 401, 402, and 403 is adjusted to adjust the protrusions formed on the conductor wiring. By adjusting the height of the semiconductor chip to the height from the mounting surface of each semiconductor chip, the protrusion can be directly connected to the connection terminal of another semiconductor device. In the case of the semiconductor module of the third embodiment, when manufacturing wiring boards used for the second semiconductor device D2 and the third semiconductor device D3, an insulating substrate having an appropriate thickness is used, and a predetermined depth is used. By forming the recess, the conductor wiring and the connection terminal can be directly connected.

Further, in the semiconductor module of each of the above embodiments, an example in which three semiconductor devices (semiconductor chips) are stacked has been described. However, the present invention is not limited to this, and four or more semiconductor devices (semiconductor chips) may be used. It goes without saying that they may be stacked.

Further, for example, in the semiconductor modules of the first and second embodiments, the protrusions are formed by electrolytic copper plating. However, the present invention is not limited to this. For example, the protrusions may be formed by nickel plating. Good.

Also, for example, in the first and second embodiments,
In the semiconductor module of (1), the connection between the protrusion and the connection terminal, for example, the protrusion 401 of the first semiconductor device D1
And the connection terminal 302 (170) of the second semiconductor device D2.
The connection with 2) is performed by thermocompression bonding using a plating film 8 made of tin plating or tin-silver alloy plating, but is not limited to this, and the plating film 8 may be, for example, a Sn-Pb solder or the like. May be formed, or a connection may be made using a conductive paste such as a solder paste instead of the plating film 8. In the case of the semiconductor module of the third embodiment, it is needless to say that solder plating may be provided as the plating film 8 or connection may be made using a conductive paste instead of the plating film 8. Absent.

[0191]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) In a semiconductor module in which a plurality of semiconductor chips are stacked using a wiring board (interposer), the number of components used can be reduced, and the manufacturing cost of the semiconductor module can be reduced.

(2) In a semiconductor module in which a plurality of semiconductor chips are stacked using a wiring board, the connection reliability between the wiring boards can be improved.

(3) A semiconductor module in which a plurality of semiconductor chips are stacked using a wiring board can be reduced in thickness.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view illustrating a schematic configuration of a semiconductor module according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a schematic configuration of the semiconductor module of the first embodiment, and is a plan view of the first semiconductor device of FIG. 1;

FIG. 3 is a schematic diagram illustrating a schematic configuration of the semiconductor module according to the first embodiment, and is a cross-sectional view taken along line AA ′ of FIG. 2;

FIG. 4 is a schematic diagram showing a schematic configuration of the semiconductor module of the first embodiment, and is a plan view of the second semiconductor device of FIG. 1;

FIG. 5 is a schematic diagram illustrating a schematic configuration of a semiconductor module according to the first embodiment, and is a plan view illustrating a schematic configuration of a third semiconductor device in FIG. 1;

FIG. 6 is a schematic diagram illustrating a schematic configuration of the semiconductor module according to the first embodiment, and is an enlarged cross-sectional view taken along a line AA ′ in FIG. 2;

FIG. 7 is a schematic diagram illustrating a schematic configuration of the semiconductor module according to the first embodiment, and is an enlarged cross-sectional view taken along a line corresponding to line BB ′ in FIG. 4;

FIG. 8 is a schematic diagram showing a schematic configuration of the semiconductor module of the first embodiment, and is a plan view of the base substrate of FIG. 1;

FIG. 9 is a schematic diagram showing a schematic configuration of the semiconductor module of the first embodiment, and is a plan view of the cover plate of FIG. 1;

FIG. 10 is a schematic diagram for explaining a method of manufacturing a wiring board used for the semiconductor module of the first embodiment;
(A), FIG. 10 (b), and FIG. 10 (c)
It is sectional drawing of each manufacturing process of the wiring board used for a 1st semiconductor device.

FIG. 11 is a schematic diagram for explaining a method of manufacturing a wiring board used for the semiconductor module of the first embodiment;
FIGS. 11A and 11B are cross-sectional views of respective manufacturing steps of a wiring board used for the first semiconductor device.

FIG. 12 is a schematic diagram for explaining a method of manufacturing a wiring board used for the semiconductor module of the first embodiment, and is a cross-sectional view of each manufacturing step of the wiring board used for the first semiconductor device.

FIG. 13 is a schematic view for explaining the method of manufacturing the semiconductor module according to the first embodiment; FIGS.
(B) is sectional drawing of each manufacturing process of a 1st semiconductor device.

FIG. 14 is a schematic view for explaining the method for manufacturing the semiconductor module of the first embodiment, and is a cross-sectional view of a step of stacking a plurality of semiconductor devices.

FIG. 15 is a schematic diagram for explaining the method for manufacturing the semiconductor module of the first embodiment, and is a partially enlarged view of FIG. 14;

FIG. 16 is a schematic diagram for explaining the method for manufacturing the semiconductor module of the first embodiment, and is a cross-sectional view of a step of stacking a plurality of semiconductor devices.

FIG. 17 is a schematic view for explaining the method for manufacturing the semiconductor module of the first embodiment, and is a cross-sectional view of a step of dividing into individual pieces.

FIG. 18 is a schematic sectional view illustrating a schematic configuration of a semiconductor module according to a second embodiment of the present invention.

FIG. 19 is a schematic diagram showing a schematic configuration of a semiconductor module of the second embodiment, and is a plan view of the first semiconductor device of FIG. 18;

FIG. 20 is a schematic diagram showing a schematic configuration of the semiconductor module of the second embodiment, and is a cross-sectional view taken along line CC ′ of FIG. 19;

21 is a schematic diagram illustrating a schematic configuration of a semiconductor module according to a second embodiment, and is an enlarged cross-sectional view of a connection portion in FIG. 18;

FIG. 22 is a schematic diagram for explaining a method for manufacturing a wiring board used for the semiconductor module of the second embodiment;
(A), FIG. 22 (b), and FIG. 22 (c)
It is sectional drawing of each manufacturing process of the wiring board used for a 1st semiconductor device.

FIG. 23 is a schematic diagram for explaining the method for manufacturing the wiring board used for the semiconductor module of the second embodiment;
(A) and FIG.23 (b) are sectional drawing of each manufacturing process of the wiring board used for a 1st semiconductor device.

FIG. 24 is a schematic view for explaining the method of manufacturing the semiconductor module according to the second embodiment; FIGS.
(B) is sectional drawing of each manufacturing process of a 1st semiconductor device.

FIG. 25 is a schematic view for explaining the method for manufacturing the semiconductor module of the second embodiment, and is a cross-sectional view of a step of stacking a plurality of semiconductor devices.

26 is a schematic view for explaining the method for manufacturing the semiconductor module of the second embodiment, and is a partially enlarged view of FIG. 25.

FIG. 27 is a schematic view for explaining the method for manufacturing the semiconductor module of the second embodiment, and is a cross-sectional view of a step of stacking a plurality of semiconductor devices.

FIG. 28 is a schematic view for explaining the method for manufacturing the semiconductor module of the second embodiment, and is a cross-sectional view of a step of dividing into individual pieces.

FIG. 29 is a schematic sectional view showing a schematic configuration of a semiconductor module according to Embodiment 3 of the present invention.

FIG. 30 is a schematic diagram showing a schematic configuration of a semiconductor module of Example 3 and is a plan view of a second semiconductor device of FIG. 29;

FIG. 31 is a schematic diagram showing a schematic configuration of a semiconductor module according to a third embodiment, and is a cross-sectional view taken along line DD ′ of FIG. 30;

FIG. 32 is a schematic diagram showing a schematic configuration of a semiconductor module according to a third embodiment, and is an enlarged cross-sectional view of a connection portion in FIG. 29;

FIG. 33 is a schematic view for explaining the method for manufacturing the wiring board used for the semiconductor module of the third embodiment;
(A), FIG. 33 (b), and FIG.
It is sectional drawing of each manufacturing process of the wiring board used for a 1st semiconductor device.

FIG. 34 is a schematic view for explaining the method for manufacturing the wiring board used for the semiconductor module of the third embodiment;
(A) and FIG.34 (b) are sectional views of each manufacturing process of the wiring board used for a 2nd semiconductor device.

FIG. 35 is a schematic diagram for explaining the method of manufacturing the wiring board used for the semiconductor module of the third embodiment;
(A) and FIG. 35 (b) are cross-sectional views of each manufacturing process of the wiring board used for the second semiconductor device.

FIG. 36 is a schematic view for explaining the method of manufacturing the wiring board used for the semiconductor module of the third embodiment, and is a cross-sectional view of each manufacturing step of the wiring board used for the second semiconductor device.

FIG. 37 is a schematic view for explaining the method of manufacturing the semiconductor module according to the third embodiment. FIG. 37 (a) is a cross-sectional view of a manufacturing process of the first semiconductor device, and FIG. 37 (b) is a second semiconductor. It is sectional drawing of the manufacturing process of an apparatus.

FIG. 38 is a schematic view for explaining the method for manufacturing the semiconductor module of the third embodiment, and is a cross-sectional view of a step of stacking a plurality of semiconductor devices.

FIG. 39 is a schematic diagram for explaining the method for manufacturing the semiconductor module of the third embodiment, and is a partially enlarged view of FIG. 38.

FIG. 40 is a schematic view for explaining the method for manufacturing the semiconductor module of the third embodiment, which is a cross-sectional view of a step of stacking a plurality of semiconductor devices.

FIG. 41 is a schematic view for explaining the method for manufacturing the semiconductor module of the third embodiment, which is a cross-sectional view of a step of dividing into individual pieces.

FIG. 42 is a schematic sectional view showing a schematic configuration of a conventional semiconductor module.

FIG. 43 is a schematic diagram showing a schematic configuration of a conventional semiconductor module, and is a plan view of the first semiconductor device of FIG. 42.

FIG. 44 is a schematic diagram showing a schematic configuration of a conventional semiconductor module, and is a cross-sectional view taken along line EE ′ of FIG. 43.

FIG. 45 is a schematic diagram showing a schematic configuration of a conventional semiconductor module, and is a plan view of a connection wiring board.

FIG. 46 is a schematic diagram showing a schematic configuration of a conventional semiconductor module, and is a cross-sectional view taken along line FF ′ of FIG. 45.

FIG. 47 is a schematic diagram showing a schematic configuration of a conventional semiconductor module, and is an enlarged sectional view of a connection portion in FIG. 42.

FIG. 48 is a schematic diagram showing a schematic configuration of a conventional semiconductor module, and is a plan view of a base substrate.

FIG. 49 is a schematic diagram for explaining a method of manufacturing a wiring board used for a conventional semiconductor module, and FIGS.
FIGS. 49 (b) and 49 (c) are cross-sectional views of respective manufacturing steps of a wiring board used for the first semiconductor device.

FIG. 50 is a schematic diagram for explaining the conventional method of manufacturing a semiconductor module, and is a cross-sectional view of a manufacturing process of the first semiconductor device.

FIG. 51 is a schematic view for explaining a method of manufacturing a wiring board used for a conventional semiconductor module, and FIG.
FIGS. 51B and 51C are cross-sectional views of respective manufacturing steps of the connection wiring board.

FIG. 52 is a schematic view for explaining a conventional method for manufacturing a semiconductor module, and is a cross-sectional view of a step of stacking a plurality of semiconductor devices.

FIG. 53 is a schematic view for explaining a conventional method of manufacturing a semiconductor module, and is a cross-sectional view of a step of stacking a plurality of semiconductor devices.

FIG. 54 is a schematic view for explaining a conventional method for manufacturing a semiconductor module, and is a partially enlarged view of FIG. 53.

FIG. 55 is a schematic view for explaining the conventional method for manufacturing a semiconductor module, and is a cross-sectional view of a step of dividing into individual pieces.

FIG. 56 is a schematic sectional view showing another schematic configuration of a conventional semiconductor module.

FIG. 57 is a schematic diagram showing a schematic configuration of a conventional semiconductor module, and is a cross-sectional view showing a configuration of a semiconductor device used for the semiconductor module of FIG. 56.

[Explanation of symbols]

D1: first semiconductor device, 101: insulating substrate of first semiconductor device, 201: conductor wiring of first semiconductor device, 301: connection terminal of first semiconductor device, 401: protrusion of first semiconductor device, 501: first 1 semiconductor chip of semiconductor device, 501
A: External electrodes of the semiconductor chip of the first semiconductor device, 901
... Dummy wiring of the first semiconductor device, 1701 ... Land (connection terminal) of the first semiconductor device, 1801 ... Copper plating film of the first semiconductor device, 1801A ... Via of the first semiconductor device, D
2, a second semiconductor device, 102, an insulating substrate of the second semiconductor device, 202, a conductor wiring of the second semiconductor device, 302, a second
Connection terminals of the semiconductor device, 402: protrusions of the second semiconductor device, 502: semiconductor chips of the second semiconductor device, 502A
... external electrodes of the semiconductor chip of the second semiconductor device, 902 ...
Dummy wiring of the second semiconductor device, 1702: Land (connection terminal) of the second semiconductor device, 1802: Copper plating film of the second semiconductor device, 1802A: Via of the second semiconductor device, 10
2A: concave portion (counterbore) of insulating substrate of second semiconductor device, D
3 ... third semiconductor device, 103 ... insulating substrate of third semiconductor device, 203 ... conductor wiring of third semiconductor device, 303 ... third
Connection terminals of the semiconductor device, 403... Protrusions of the third semiconductor device, 503... Semiconductor chips of the third semiconductor device, 503A
... external electrodes of the semiconductor chip of the third semiconductor device, 903
Dummy wiring of the third semiconductor device, 1703: land (connection terminal) of the third semiconductor device, 1803: copper plating film of the third semiconductor device, 1803A: via of the third semiconductor device, 10
3A: concave portion (counterbore) of insulating substrate of third semiconductor device, 6
… Gold bump (stud bump), 7… insulator (NCF),
8: plating film, BB: base substrate, 10: base substrate insulating substrate, 11: base substrate conductor wiring, 12: ball-shaped terminal, CP: cover plate, 13: cover plate insulating substrate, 13A: cover plate Concave portion (counterbore) of insulating substrate, 14: dummy terminal, 15: resist (plating resist), 16: stacking stage, 16A: positioning pin, SB1: first connection wiring board, SB2: second connection wiring board , SB3... Third connection wiring board, 1901, 19
02, 1903 ... Insulating substrate of connection wiring board, 2001 ...
1st terminal, 2101 ... 2nd terminal, 2201 ... copper plating film, 2201A ... via, 23 ... solder ball.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Satoshi Kinda             1-6-1 Otemachi, Chiyoda-ku, Tokyo Sun             Standing wire company (72) Inventor Akihiko Abe             1-6-1 Otemachi, Chiyoda-ku, Tokyo Sun             Standing wire company (72) Inventor Ryo Matsuura             1-6-1 Otemachi, Chiyoda-ku, Tokyo Sun             Standing wire company (72) Inventor Hiroshi Shimoe             800, Nakaryu-gu, Yokkaichi, Mie Prefecture             Location: Toshiba Yokkaichi Plant (72) Inventor Hideo Taguchi             800, Nakaryu-gu, Yokkaichi, Mie Prefecture             Location: Toshiba Yokkaichi Plant (72) Inventor Riichi Mino             No. 1 Komukai Toshiba-cho, Kawasaki-shi, Kanagawa             Toshiba Microelectronics             Inside (72) Inventor Tomoaki Takubo             No. 1 Komukai Toshiba-cho, Kawasaki-shi, Kanagawa             Toshiba Microelectronics             Inside

Claims (12)

[Claims] A conductive pattern having a predetermined pattern provided on a first main surface of the insulating substrate; and a second main surface of the insulating substrate facing the first main surface, the conductive wiring being electrically connected to the conductive wiring. A plurality of semiconductor devices each having a semiconductor chip mounted on a wiring board provided with connection terminals provided thereon are stacked, and the conductor wiring provided on the wiring board of the first semiconductor device is superimposed on the first semiconductor device. A semiconductor module in which a connection terminal provided on a wiring board of a second semiconductor device is electrically connected, a conductor wiring provided on a wiring board of the first semiconductor device,
A semiconductor module, wherein the connection terminal provided on a wiring board of the second semiconductor device is directly connected. 2. The conductor wiring provided on the wiring board of the first semiconductor device has a projection having a predetermined height in a region connected to the connection terminal provided on the wiring board of the second semiconductor device. 2. The semiconductor module according to claim 1, wherein the protruding portion and the connection terminal are directly connected. 3. 3. The semiconductor device according to claim 1, wherein the insulating substrate of the wiring board of the second semiconductor device is provided with a concave portion (a counterbore) capable of accommodating the semiconductor chip of the first semiconductor device. The semiconductor module as described in the above. 4. A conductor wiring of a predetermined pattern is provided on a first main surface of the insulating substrate, and a second main surface of the insulating substrate facing the first main surface is electrically connected to the conductor wiring. A wiring board for forming a semiconductor module by laminating a plurality of semiconductor chips, wherein the conductor wiring is provided in a region connected to the connection terminal of another wiring board. A first protrusion having a height, wherein when the protrusion of the conductor wiring of the first wiring board is directly connected to the connection terminal of the second wiring board laminated on the first wiring board, the first wiring board A wiring board, wherein a space capable of accommodating a semiconductor chip is provided between the wiring board and the second wiring board. 5. A conductor wiring of a predetermined pattern is provided on a first main surface of an insulating substrate, and a second main surface of the insulating substrate facing the first main surface is electrically connected to the conductor wiring. A wiring board for forming a semiconductor module by laminating a plurality of semiconductor chips, wherein the insulating substrate has a recess (a counterbore) of a predetermined shape on the second main surface side. ) Is provided, and when the conductor wiring of the first wiring board is directly connected to the connection terminal of the second wiring board laminated on the first wiring board, the first wiring board and the second wiring are connected. A wiring board, wherein a space capable of accommodating a semiconductor chip is provided between the boards. 6. A conductor pattern having a predetermined pattern is formed on a first main surface of an insulating substrate, and is electrically connected to the conductor wiring on a second main surface of the insulating substrate facing the first main surface. Semiconductor device forming step of forming a semiconductor device by mounting a semiconductor chip on a wiring board on which connection terminals are formed, and a semiconductor stacking a second semiconductor device on the first semiconductor device formed in the semiconductor device forming step A semiconductor device connecting step of electrically connecting the conductor wiring formed on the wiring board of the first semiconductor device and the connection terminal formed on the wiring board of the second semiconductor device. In the method for manufacturing a semiconductor module, the semiconductor device connecting step may include directly connecting the conductor wiring of the wiring board of the first semiconductor device and the connection terminal of the wiring board of the second semiconductor device. The method of manufacturing a semiconductor module according to symptoms. 7. A semiconductor device forming step of forming the first semiconductor device, wherein the semiconductor device is formed on a wiring board having a protrusion at a predetermined position of the conductor wiring and having a height substantially equal to a height of a semiconductor chip to be mounted. A chip is mounted, and the semiconductor device connecting step is characterized in that a projecting portion of the conductor wiring of the wiring board of the first semiconductor device is connected to the connection terminal of the wiring board of the second semiconductor device. The method for manufacturing a semiconductor module according to claim 6. 8. A semiconductor device forming step of forming the second semiconductor device, wherein the semiconductor device of the first semiconductor device has a depth substantially equal to the height of the semiconductor chip of the first semiconductor device in a region overlapping with the semiconductor chip of the first semiconductor device. Mounting the semiconductor chip on a wiring board having a concave portion (counterbore), wherein the semiconductor device laminating step includes: housing the semiconductor chip of the first semiconductor device in the concave portion of the wiring board of the second semiconductor device. The method for manufacturing a semiconductor module according to claim 6, wherein the semiconductor modules are stacked so as to be stacked. 9. A step of forming conductor wiring of a predetermined pattern on a first main surface of an insulating substrate, and electrically connecting the conductor wiring to a second main surface of the insulating substrate opposite to the first main surface. A method of manufacturing a wiring board for forming a semiconductor module by laminating a plurality of semiconductor chips, comprising the steps of: forming a connection terminal, wherein the step of opening a predetermined position of the insulating substrate; Forming a conductor film on the first main surface of the insulating substrate, forming a connection terminal by burying a conductor in an opening of the insulating substrate, and forming a protrusion having a predetermined height at a predetermined position on the conductor film. A method of manufacturing a wiring board, comprising: forming a conductive film; and forming a conductive wiring having the protrusion by etching the conductive film. 10. A step of forming a conductor wiring of a predetermined pattern on a first main surface of an insulating substrate;
Forming a connection terminal electrically connected to the conductor wiring on a second main surface opposite to the main surface, manufacturing a wiring board for forming a semiconductor module by laminating a plurality of semiconductor chips. Forming a first conductive film on a first main surface of the insulating substrate, and forming a second conductive film on a second main surface of the insulating substrate opposite to the first main surface; Opening a predetermined position of the insulating substrate and forming a via for electrically connecting the first conductive film and the second conductive film; and a protrusion having a predetermined height at a predetermined position on the first conductive film. Forming a conductive wiring having the protrusion by etching the first conductive film, etching the second conductive film and forming a connection terminal connected to the conductive wiring by the via. Manufacturing a wiring board, comprising the steps of: Method. 11. The method according to claim 9, wherein in the step of forming the protrusion, a protrusion having a predetermined height is formed by electrolytic copper plating, and then a tip of the protrusion is flattened. The method for manufacturing a wiring board according to claim 10. 12. A step of forming a predetermined pattern of conductor wiring on a first main surface of an insulating substrate;
Forming a connection terminal electrically connected to the conductor wiring on a second main surface opposite to the main surface, manufacturing a wiring board for forming a semiconductor module by laminating a plurality of semiconductor chips. Forming a first conductive film on a first main surface of the insulating substrate, and forming a second conductive film on a second main surface of the insulating substrate opposite to the first main surface; Opening a predetermined position of the insulating substrate and forming a via for electrically connecting the first conductive film and the second conductive film; and forming a connection terminal by etching the second conductive film. Forming a recess (counterbore) having a predetermined depth from a side of the second main surface in a predetermined region of the insulating substrate; etching the first conductive film and forming the connection terminal by the via; Forming a conductor wiring connected to the A method for manufacturing a wiring board to be.