JP2003347315A - Semiconductor device, manufacturing method thereof, power amplifier, and radio communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a threshold voltage not lower than 0 V. <P>SOLUTION: A manufacturing method of the semiconductor device includes a process for growing the crystal of a GaN buffer layer 14 on a sapphire (0001) substrate 11 with a vertical axis relative to the principal surface of the substrate as a c-axis to form a GaN(1-101) facet plane 14a, a process for forming an electron-transit layer 15 and a barrier layer 16 on a facet plane 14a, a process for forming high-impurity-concentration n-type regions 20, 20 in source/drain- electrode forming regions, and a process for forming source, drain, and base electrodes 17, 19 and 18 on the barrier layer 16. In this case, the plane orientation of the interface between the electron-transit and barrier layers 15, 16 is directed to a (1-101) plane. Therefore, polarized charge generated at the interface is made small and the concentration of two-dimensional electron gas produced at the interface is made small, so that the threshold voltage of the semiconductor device is not lower than 0 V. Thereby, a heterojunction field effect transistor capable of being operated without using a negative voltage can be obtained. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device (specifically, a heterojunction field-effect transistor having a threshold voltage of 0 V or more), a method of manufacturing the same, and operation of the semiconductor device irrespective of a negative voltage. The present invention relates to a power amplifier that can be used and a wireless communication system using the power amplifier.

[0002]

2. Description of the Related Art In recent years, a heterojunction field effect transistor using a nitride semiconductor has a saturated electron velocity of GaN of about 2.
0 × 10 ⁷ cm / s, and the breakdown electric field strength is about 4.0 × 10 ⁶
V / cm, which is larger than Si or GaAs, has attracted attention as a semiconductor device which operates at high frequency, high withstand voltage and high temperature. In the heterojunction field-effect transistor using the nitride semiconductor, a polarization charge is generated in the heterojunction based on a polarization effect caused by a difference in lattice constant between the electron transit layer and the barrier layer. The concentration of the two-dimensional electron gas generated at the interface between the semiconductor layer and the barrier layer can be increased to 1 × 10 ¹³ cm ⁻² or more. Therefore, it is also attracting attention as a semiconductor element for a high-output amplifier and a large power.

FIG. 10 is a sectional view showing a schematic structure of a conventional heterojunction field effect transistor. FIG.
Heterojunction field effect transistors such as those described in, for example, Mishra et al., Proceedings of the 1998 Conference on Optoelectronic and Microelectronic Materials Devices (1999).
Pp. 73-79 (Proceedings 1998 Conference on
Optoelectronic andMicroelectronic Materials Devic
es (1999) pp. 73-79).

In FIG. 10, a GaN buffer layer 2 having a thickness of 20 nm, an undoped GaN electron transit layer 3 having a thickness of 2 μm and a film are formed on a sapphire (0001) substrate 1 by using a metalorganic vapor phase epitaxy method. AlGaN with a thickness of 20 nm
Four barrier layers are sequentially laminated. further,
On the barrier layer 4, a source electrode 5, a drain electrode 6, and a gate electrode 7 are formed.

[0005]

However, the above-mentioned conventional heterojunction field effect transistor has the following problems.

That is, in order to reduce the power consumption by reducing the size of a power amplifier used in a wireless communication system such as a mobile information terminal or a base station of a mobile phone, it is necessary to minimize the circuit scale and the number of components. However, in the above-described conventional heterojunction field effect transistor, the electron transit layer 3
The (0001) plane where the generated polarization charge is the largest or a plane substantially parallel thereto is used as the interface between the barrier layer 4 and the barrier layer 4. Therefore, the concentration of the two-dimensional electron gas generated at the interface increases, and it is very difficult to manufacture a so-called enhancement type field effect transistor that does not require a negative voltage as a gate voltage.

As a result, a power amplifier manufactured using the above-mentioned conventional heterojunction field-effect transistor requires a circuit for generating a negative voltage based on a negative power supply voltage or a positive power supply voltage, and components of the circuit. . For this reason, it becomes an obstacle to miniaturization and low power consumption of the power amplifier, and further to a miniaturization and low power consumption of the wireless communication system.

Therefore, an object of the present invention is to set the threshold voltage to zero.
It is an object of the present invention to provide a semiconductor device which can be operated regardless of a negative voltage which is equal to or higher than V and a method for manufacturing the same. Another object of the present invention is to provide a power amplifier which does not require a negative voltage and is suitable for miniaturization and low power consumption, and a wireless communication system using the same.

[0009]

In order to achieve the above object, in the semiconductor device of the first invention, the plane orientation of the interface between the electron transit layer and the barrier layer is the (1-101) plane. Therefore, since the polarization charge generated at the interface is reduced,
The concentration of the two-dimensional electron gas is reduced. As a result, the threshold voltage of the operation can be set to 0 V or more, and the operation can be performed without using a negative voltage.

In one embodiment of the present invention, at least one of the electron transit layer and the barrier layer is made of a nitride III-V compound semiconductor containing nitrogen as a group V element. . As described above, when one of the electron transit layer and the barrier layer is made of a nitride III-V compound semiconductor, the polarization charge generated at the interface between the electron transit layer and the barrier layer is reduced. growing. for that reason,
The effect of reducing the concentration of the two-dimensional electron gas due to the reduction of the polarization charge generated at the interface is also increased, and the effect of setting the threshold voltage to 0 V or more is further exhibited.

In one embodiment of the present invention, the electron transit layer is formed of In _x Ga ₁ -xN (0 ≦ x ≦ 1). Therefore, the polarization charge generated at the interface between the electron transit layer and the barrier layer is further increased, and the effect of reducing the concentration of the two-dimensional electron gas due to the reduction of the polarization charge generated at the interface is further increased.

In one embodiment of the present invention, the barrier layer is made of Al _y Ga _{1 -yN} (0 ≦ y ≦ 1). Therefore, the polarization charge generated at the interface between the electron transit layer and the barrier layer is further increased, and the effect of reducing the concentration of the two-dimensional electron gas due to the reduction of the polarization charge generated at the interface is further increased.

In one embodiment of the present invention, the electron transit layer and the barrier layer are formed on a substrate having a main surface having an off angle from the (1-101) plane of 0 ° or more and 10 ° or less. are doing. By doing so, the interface between the electron transit layer and the barrier layer becomes an extremely flat interface having a (1-101) plane, and the scattering of the two-dimensional electron gas at the interface is suppressed. Therefore, characteristics excellent in high-frequency characteristics can be obtained.

Further, in the semiconductor device of one embodiment,
A substrate having a main surface having an off angle from the (1-101) plane of 0 degree or more and 10 degrees or less is configured with gallium and nitrogen as main components. By doing this,
Scattering of the two-dimensional electron gas at the interface between the electron transit layer and the barrier layer is more effectively suppressed.

A power amplifier according to a second aspect uses the semiconductor device according to the first aspect as a power amplification element. As described above, by using a semiconductor device whose operation threshold voltage is 0 V or higher, operation can be performed without using a negative voltage. Therefore, a negative voltage generation circuit is not required, miniaturization is achieved, and power consumption is reduced.

Further, a wireless communication system according to a third aspect of the present invention includes:
It is configured using the power amplifier of the second invention.
Thus, by incorporating a power amplifier that does not require a negative voltage generation circuit, miniaturization is achieved and power consumption is reduced.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device, a buffer layer having a main surface having a plane orientation of (1-101) is formed, and at least an electron transit layer and a barrier layer are formed on the buffer layer. And the plane orientation of the interface between the electron transit layer and the barrier layer is set to the (1-101) plane. Thus, the threshold voltage of operation can be set to 0 V or higher, and a semiconductor device which can operate without using a negative voltage is manufactured.

In one embodiment of the method of manufacturing a semiconductor device, the buffer layer is formed on a substrate having a main surface having an off angle from the (1-101) plane of 0 ° or more and 10 ° or less. I am trying to do it. By doing this,
The interface between the electron transit layer and the barrier layer becomes an extremely flat interface having a (1-101) plane, and the scattering of the two-dimensional electron gas at the interface is suppressed. Therefore, characteristics excellent in high-frequency characteristics can be obtained.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

<First Embodiment> FIG. 1 shows a cross section of a heterojunction field effect transistor as a semiconductor device of the present embodiment. In FIG. 1, sapphire (00
01) On the undoped AlN buffer layer 12 having a thickness of 20 nm formed on the substrate 11,
Of the insulating film 13 is deposited. Then, a GaN (1-101) facet surface 14a is formed by growing a GaN buffer layer 14 in a region where the insulating film 13 has been removed by patterning. An undoped In _x Ga layer having a thickness of 20 nm is formed on the facet surface 14a.
_{A 1-x} N (x = 0.2) electron transit layer 15 and an undoped Al _y Ga _1-y N (y = 0.25) barrier layer 16 having a thickness of 10 nm are sequentially formed.

A source electrode 17, a gate electrode 18 and a drain electrode are formed on the sloped barrier layers 16 in the mountain-shaped laminated structure formed by the buffer layer 14, the electron transit layer 15 and the barrier layer 16 in order from the top. 19 are provided. Here, the source electrode 17 and the drain electrode 19 are formed by sequentially laminating, for example, titanium (Ti) and aluminum (Al) from the barrier layer 16 side.
The gate electrode 18 is formed, for example, by sequentially stacking nickel (Ni) and gold (Au) from the barrier layer 16 side. Further, a high-concentration n-type region 20 is formed in a region below the source electrode 17 and the drain electrode 19 by ion implantation of a donor-type impurity element such as Si.

FIG. 2 is a sectional view showing a procedure for manufacturing the heterojunction field effect transistor shown in FIG. Hereinafter, FIG.
, A method for manufacturing the present heterojunction field effect transistor will be described.

First, the sapphire (0001) substrate 11 is cleaned. Then, on this sapphire substrate 11, FIG.
As shown in FIG. 1A, an undoped AlN buffer layer 12 having a thickness of 20 nm is grown by using metalorganic vapor phase epitaxy or molecular beam epitaxy. Further, a 100 nm thick silicon oxide film or silicon nitride film is deposited thereon by plasma CVD (chemical vapor deposition) to form an insulating film 13.

Subsequently, as shown in FIG. 2B, the insulating film 13 is partially removed by patterning by photolithography and wet etching by hydrofluoric acid. After that, using metal organic vapor phase epitaxy or gas source molecular beam epitaxy, etc., as shown in FIG.
As shown in FIG. 5, a GaN buffer layer 14 is formed by selectively growing GaN in a region where the insulating film 13 has been removed. At this time, in the GaN buffer layer 14, crystal growth proceeds with an axis perpendicular to the main surface of the sapphire substrate 11 as the c-axis, and at the same time, a GaN (1-101) facet surface 14a is formed.

Subsequently, as shown in FIG.
(1-101) on the facet 14a, thickness 20nm undoped _{In x Ga 1-x N (} x = 0.2) electron transit layer 15 and the thickness of 10nm undoped Al _y Ga _1-y N ( y = 0.2
5) The barrier layers 16 are sequentially grown epitaxially. Thereby, the plane orientation of the interface between the electron transit layer 15 and the barrier layer 16 can be set to the (1-101) plane.

Next, as shown in FIG. 2E, Si is ion-implanted into the source electrode formation region and the drain electrode formation region to form high concentration n-type regions 20,20. Subsequently, a source electrode formation region and a drain electrode formation region are patterned on the AlGaN barrier layer 16 by photolithography. Then, as shown in FIG. 2 (f), the source electrode formation region and the drain electrode formation region have T
Source electrode 17 and drain electrode 19 are formed by sequentially depositing i / Al and lifting off. Subsequently, heat treatment is performed for 30 seconds in a nitrogen atmosphere at 890 ° C. to obtain ohmic contact.

After that, a gate electrode formation region is patterned on the AlGaN barrier layer 16 by photolithography. Then, as shown in FIG. 2 (g), a gate electrode 18 is formed by sequentially depositing Ni / Au on the gate electrode forming region and lifting off the film. Thus, the heterojunction field effect transistor according to the present embodiment is manufactured.

FIG. 3 shows a current-voltage characteristic between the source electrode 17 and the drain electrode 19 when the gate voltage of the present hetero junction field effect transistor is 0V. In the present embodiment, the plane orientation of the interface between the electron transit layer 15 and the barrier layer 16 is the (1-101) plane. Therefore, the plane orientation of the interface between the electron transit layer and the barrier layer is (0001)
The polarization charge generated at the interface between the electron transit layer 15 and the barrier layer 16 is smaller than that of the above-mentioned conventional heterojunction field-effect transistor, and the concentration of the two-dimensional electron gas generated at the interface is also smaller. As a result, the threshold voltage becomes 0 V or more, and when the gate voltage is 0 V, no drain current flows and an enhancement operation is performed.

As described above, according to the heterojunction field effect transistor of the present embodiment, the electron transit layer 15
The concentration of the two-dimensional electron gas can be reduced by lowering the polarization charge generated at the interface between the two-dimensional electron gas and the barrier layer 16. Therefore, it is possible to provide a hetero-junction field-effect transistor that can operate regardless of a negative voltage.

In this embodiment, InGaN having an In composition ratio x = 0.2 is used as the electron transit layer 15.
AlGaN having an Al composition ratio y = 0.25 is used as the barrier layer 16. However, the same effect can be obtained even when the In composition ratio x and the Al composition ratio y are set to values of 0 ≦ x ≦ 1 and 0 ≦ y ≦ 1 within a range that does not greatly exceed the critical film thickness of InGaN and AlGaN. Of course. Thus, the InGa layer 15 and the barrier layer 16 are made of InGa.
By using a nitride-based III-V compound semiconductor containing nitrogen as a group V element as well as N and AlGaN,
Since the polarization charge generated at the interface between the electron transit layer 15 and the barrier layer 16 increases, the effect of reducing the concentration of the two-dimensional electron gas due to the reduction of the polarization charge generated at the interface also increases. Therefore, the effect that the threshold voltage becomes 0 V or more can be further exhibited.

Further, in the present embodiment, the source electrode 17 and the drain electrode 19 are formed on the barrier layer 16. However, the present invention is not limited to this, and the source electrode and the drain electrode may be formed on the electron transit layer 15 in a region where the barrier layer 16 is removed. Further, an n-type conductive layer such as n ⁺ GaN may be provided between the barrier layer 16 and the source electrode 17 and between the barrier layer 16 and the drain electrode 19.

In the present embodiment, the source electrode 17, the gate electrode 18 and the drain electrode 19
Are formed on the barrier layers 16 on both slopes in the mountain-shaped laminated structure. However, the present invention is not limited to this, and the source electrode 17, the gate electrode 18 and the drain electrode 19 may be formed only on the barrier layer 16 on one of the slopes in the laminated structure.

In the present embodiment, the source electrode 17, the gate electrode 18 and the drain electrode 19 are formed in this order from the top of the chevron-shaped laminated structure. They may be formed in order.

In the present embodiment, the electron transit layer 15 and the barrier layer 16 are undoped layers. However, part or all of the electron transit layer 15 and the barrier layer 16 may be, for example, an n-type impurity doped layer to which Si is added.

In this embodiment, the sapphire (0001) substrate 11 is used as the substrate. However, a sapphire substrate having another plane orientation, an Si substrate, a GaAs substrate, an In substrate
Needless to say, the present invention can be similarly performed using a substrate made of another material such as a P substrate.

In this embodiment, the case where the electron transit layer 15 and the barrier layer 16 are made of a nitride III-V compound semiconductor containing nitrogen as a group V element has been described. The present invention can be similarly implemented using a non-nitride semiconductor such as ZnS or ZnS.

<Second Embodiment> FIG. 4 shows a longitudinal section of a heterojunction field effect transistor according to the present embodiment. In FIG. 4, for example, an undoped In _x Ga ₁ layer having a thickness of 20 nm is formed on a GaN substrate 21 having a principal plane of (1-101) plane via an undoped GaN buffer layer 22 having a thickness of 500 nm. _{The -xN} (x = 0.2) electron transit layer 23 is formed. On the electron transit layer 23, an undoped Al _y Ga _1-y N (y = 0.25) barrier layer 24 having a thickness of 10 nm is formed.

Further, a source electrode 25, a drain electrode 26 and a gate electrode 27 are provided on the barrier layer 24. Source electrode 25 and drain electrode 26
Is formed, for example, by sequentially laminating titanium (Ti) and aluminum (Al) from the GaN substrate 21 side. Also,
The gate electrode 27 is formed by sequentially stacking nickel (Ni) and gold (Au) from the GaN substrate 21 side, for example.
Further, a high-concentration n-type region 28 is formed in a region below the source electrode 25 and the drain electrode 26 by ion-implanting a donor-type impurity element such as Si.

FIG. 5 is a sectional view showing a procedure for manufacturing the heterojunction field effect transistor shown in FIG. Hereinafter, FIG.
, A method for manufacturing the present heterojunction field effect transistor will be described.

First, a semi-insulating GaN (1-101) substrate 2
Wash 1 Then, on the GaN substrate 21, FIG.
As shown in FIG. 1, the GaN buffer layers 22 and I are formed by using metalorganic vapor phase epitaxy or molecular beam epitaxy.
The nGaN electron transit layer 23 and the AlGaN barrier layer 24 are sequentially epitaxially grown. Thereby, the electron transit layer 23
The plane orientation of the interface between the barrier layer 24 and the barrier layer 24 can be the (1-101) plane.

Subsequently, as shown in FIG. 5B, the devices are separated by photolithography and reactive ion etching. Next, as shown in FIG. 5C, Si is ion-implanted into the source electrode formation region and the drain electrode formation region to form high-concentration n-type regions 28,28.
Subsequently, a source electrode formation region and a drain electrode formation region are patterned on the AlGaN barrier layer 24 by photolithography. Then, as shown in FIG.
The source electrode 25 and the drain electrode 26 are formed by sequentially depositing Ti / Al on the source electrode formation region and the drain electrode formation region and performing lift-off. Subsequently, heat treatment is performed for 30 seconds in a nitrogen atmosphere at 890 ° C. to obtain ohmic contact.

After that, a gate electrode forming region is patterned on the AlGaN barrier layer 24 by photolithography. Then, as shown in FIG. 5E, a gate electrode 27 is formed by sequentially depositing Ni / Au on the gate electrode forming region and lifting off the film. Thus, the heterojunction field effect transistor according to the present embodiment is manufactured.

FIG. 6 shows the relationship between the mobility of the two-dimensional electron gas and the off angle of the GaN substrate 21 in the present heterojunction field effect transistor. In this embodiment, Ga
An N (1-101) substrate 21 is used. Therefore, as compared with the above-mentioned conventional heterojunction field-effect transistor using a sapphire (0001) substrate, a remarkable improvement in mobility is seen when the off-angle is 10 degrees or less. This is because the GaN (1-101) substrate 21 having an off angle of 10 degrees or less.
Is used, the InGaN electron transit layer 23 and Al
This is because the interface with the GaN barrier layer 24 is an extremely flat interface having a (1-101) plane, and the scattering of the two-dimensional electron gas at the interface is suppressed.

FIG. 7 shows current-voltage characteristics between the source electrode 25 and the drain electrode 26 when the gate voltage of the present hetero junction field effect transistor is 0 V. In this embodiment, the polarization charge generated at the interface between the electron transit layer 23 and the barrier layer 24 is smaller than that of the conventional heterojunction field effect transistor using the sapphire (0001) substrate, and the polarization charge generated at the interface is reduced. Therefore, the concentration of the two-dimensional electron gas is also reduced. As a result, the threshold voltage becomes 0 V or more, and when the gate voltage is 0 V, no drain current flows and an enhancement operation is performed.

As described above, according to the hetero-junction field effect transistor of the present embodiment, the off angle is 10
By using the GaN (1-101) substrate 21 having a temperature of less than
It is possible to provide a heterojunction field-effect transistor that can suppress scattering of two-dimensional electron gas and has excellent high-frequency characteristics. Furthermore, the concentration of the two-dimensional electron gas can be reduced by reducing the polarization charge generated at the interface between the electron transit layer 23 and the barrier layer 24. Therefore, it is possible to provide a hetero-junction field-effect transistor that can operate regardless of a negative voltage.

In the present embodiment, InGaN having an In composition ratio x = 0.2 is used as the electron transit layer 23.
AlGaN having an Al composition ratio y = 0.25 is used as the barrier layer 24. However, the same effect can be obtained even when the In composition ratio x and the Al composition ratio y are set to values of 0 ≦ x ≦ 1 and 0 ≦ y ≦ 1 within a range that does not greatly exceed the critical film thickness of InGaN and AlGaN. Of course. Thus, the InGa layer 23 and the barrier layer 24 are made of InGa.
By using a nitride-based III-V compound semiconductor containing nitrogen as a group V element as well as N and AlGaN,
Since the polarization charge generated at the interface between the electron transit layer 23 and the barrier layer 24 increases, the effect of reducing the concentration of the two-dimensional electron gas due to the reduction of the polarization charge generated at the interface also increases. Therefore, the effect that the threshold voltage becomes 0 V or more can be further exhibited.

In the present embodiment, the source electrode 25 and the drain electrode 26 are formed on the barrier layer 24. However, the present invention is not limited to this, and the source electrode and the drain electrode may be formed on the electron transit layer 23 in a region where the barrier layer 24 has been removed. Further, an n-type conductive layer such as n ⁺ GaN may be provided between the barrier layer 24 and the source electrode 25 and between the barrier layer 24 and the drain electrode 26.

In this embodiment, the electron transit layer 23 and the barrier layer 24 are undoped layers. However, part or all of the electron transit layer 23 and the barrier layer 24 may be, for example, an n-type impurity doped layer to which Si is added.

In this embodiment, the GaN (1-101) substrate 21 is used as the substrate.
Needless to say, the present invention can be similarly implemented using a substrate made of another material such as a ZnO substrate.

In this embodiment, the case where the electron transit layer 23 and the barrier layer 24 are made of a nitride III-V compound semiconductor containing nitrogen as a group V element has been described. The present invention can be similarly implemented using a non-nitride semiconductor such as ZnS or ZnS.

<Third Embodiment> This embodiment relates to a power amplifier using the heterojunction field effect transistor according to the second embodiment.

FIG. 8 is a circuit diagram of a two-stage power amplifier according to the present embodiment. In FIG. 8, 31
Denotes a heterojunction field-effect transistor in the preceding stage, which is the heterojunction field-effect transistor in the second embodiment. Reference numeral 32 denotes a subsequent heterojunction field effect transistor, which is the heterojunction field effect transistor according to the second embodiment.

Reference numeral 33 denotes a high-frequency signal input terminal;
Is an input matching circuit for the preceding heterojunction field effect transistor, and 35 is a bias circuit for the preceding heterojunction field effect transistor. 36 is an interstage matching circuit, 3
Reference numeral 7 denotes a bias circuit for the subsequent-stage heterojunction field-effect transistor, and reference numeral 38 denotes an output matching circuit from the latter-stage heterojunction field-effect transistor 32. 39 is a high-frequency signal output terminal, and 40 and 40 are power supply voltage terminals.

In the power amplifier according to the present embodiment, a heterojunction field effect transistor excellent in high frequency characteristics and having a threshold voltage of 0 V or more is used as an amplifying transistor. Therefore, it is possible to operate without using a negative voltage, and to input a high-frequency input signal input to the gate electrode of the hetero-junction field-effect transistor 31 of the preceding stage or a gate electrode of the hetero-junction field-effect transistor 32 of the following stage. There is no need for a negative voltage generating circuit for biasing the high frequency amplified signal to a negative voltage. Therefore, it is possible to provide a high-frequency power amplifier that can be downsized and reduce power consumption.

In this embodiment, the heterojunction field effect transistor according to the second embodiment is
The case where the present invention is applied to a power amplifier having a stage configuration is shown. However, it goes without saying that the same effect can be obtained even when applied to a one-stage power amplifier or three or more stages of power amplifiers. Further, the heterojunction field-effect transistor according to the first embodiment can be applied.

<Fourth Embodiment> This embodiment relates to a radio communication system using the power amplifier according to the third embodiment.

FIG. 9 is a block diagram showing a system configuration of a portable telephone as an example of the radio communication system according to the present embodiment. In FIG. 9, 41 is an antenna, 4
2 is an RF (high frequency) block unit, 43 is a baseband unit,
44 is a handset, and 45 is a control unit.

The RF block section 42 includes a transmitting section 46,
It comprises a receiving section 47, an antenna switch 48 and a frequency synthesizer 49. Then, the transmitting unit 46
It comprises a transmission power amplifier 50 and a transmission mixer 51. Here, the transmission power amplifier 50 is configured by the power amplifier according to the third embodiment. Further, the receiving unit 47 includes a low-noise amplifier 52, a reception mixer 53
And an IF (intermediate frequency) amplifier 54.

The baseband section 43 includes a modulator 55,
It comprises a transmission signal processing section 56, a demodulator 57 and a reception signal processing section 58. In addition, the handset 44
It comprises a transmitter 59 and a receiver 60.
The control unit 45 includes a control circuit 61 and a display key 62.
It is constituted by.

The portable telephone having the above configuration operates as follows. That is, at the time of reception, the antenna switch 48 is switched to the receiving side under the control of the control circuit 61 of the control unit 45, and the high frequency signal from the antenna 41 is input to the receiving unit 47 of the RF block unit 42. Then, the signal is amplified by the low noise amplifier 52, mixed with the oscillation signal from the frequency synthesizer 49 by the reception mixer 53, converted into an intermediate frequency signal, and then amplified by the IF amplifier 54. The intermediate frequency signal thus obtained is transmitted to the baseband unit 4
3, the signal wave is extracted by the demodulator 57, and various processes are performed by the reception signal processing unit 58, and then the sound is output from the receiver 60 of the transmitter / receiver 44.

On the other hand, at the time of transmission, the voice signal is converted into a signal wave by the transmitter 59 of the transmitter / receiver 44 and input to the baseband unit 43. Then, the transmission signal processing unit 5
After various processes are performed by 6, the signal is modulated by the modulator 55 to generate an intermediate frequency signal. The intermediate frequency signal thus obtained is input to the transmission section 46 of the RF block section 42. After being mixed with the oscillation signal from the frequency synthesizer 49 by the transmission mixer 51 and converted into a high-frequency signal, the signal is amplified by the transmission power amplifier 50. The high-frequency signal thus obtained is transmitted to the antenna switch 4 switched to the transmitting side under the control of the control circuit 61 of the control unit 45.
Through the antenna 8, it is radiated from the antenna 41 as high-frequency radio waves.

In the above configuration, as described above, the transmission power amplifier 50 in the transmission section 46 of the RF block section 42 is configured by the power amplifier according to the third embodiment. Therefore, the transmission power amplifier 50
A negative voltage generation circuit is not required, and miniaturization and low power consumption can be achieved. That is, according to the present embodiment, it is possible to provide a mobile phone capable of reducing power consumption while reducing the size.

In the present embodiment, an example has been described in which the power amplifier of the third embodiment is applied to a transmission power amplifier of a portable telephone. However,
It goes without saying that the present invention is applicable to a power amplifier in other wireless communication systems such as a mobile phone base station other than the mobile phone.

[0064]

As is clear from the above, the semiconductor device according to the first aspect of the present invention has a plane orientation at the interface between the electron transit layer and the barrier layer.
Since the (1-101) plane is used, the concentration of the two-dimensional electron gas can be reduced by reducing the polarization charge generated at the interface. Therefore, the threshold voltage of the operation can be set to 0 V or more, and the operation can be performed without using a negative voltage.

That is, according to the present invention, it is possible to provide a semiconductor device which does not require a negative voltage generating circuit and can be reduced in size and power consumption.

Further, since the power amplifier of the second invention uses the semiconductor device of the first invention as a power amplifier, it can be operated without using a negative voltage.
Therefore, a negative voltage generation circuit is not required, miniaturization and
Power consumption can be reduced.

Further, a wireless communication system according to a third aspect of the present invention
Since the power amplifier of the second aspect is used, a negative voltage generating circuit is not required, and miniaturization and power consumption can be achieved.

In the method of manufacturing a semiconductor device according to a fourth aspect of the present invention, a buffer layer having a main surface having a plane orientation of (1-101) is formed, and at least an electron transit layer and a barrier layer are formed on the buffer layer. Is formed and the plane orientation of the interface between the electron transit layer and the barrier layer is set to the (1-101) plane, so that the operation threshold voltage can be made 0 V or more, and the operation can be performed without using a negative voltage. Semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a heterojunction field effect transistor as a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view showing a procedure for manufacturing the heterojunction field-effect transistor shown in FIG.

3 is a diagram showing current-voltage characteristics between a source and a drain when the gate voltage is 0 V in the heterojunction field effect transistor shown in FIG.

FIG. 4 is a cross-sectional view of a heterojunction field-effect transistor different from FIG.

5 is a cross-sectional view showing a procedure for manufacturing the heterojunction field effect transistor shown in FIG.

6 is a diagram showing the relationship between the mobility of a two-dimensional electron gas and the off-angle of a substrate in the heterojunction field-effect transistor shown in FIG.

7 is a diagram showing current-voltage characteristics between a source and a drain when the gate voltage of the heterojunction field-effect transistor shown in FIG. 4 is 0V.

FIG. 8 is a circuit diagram of the power amplifier according to the present invention.

FIG. 9 is a block diagram of a mobile phone as an example of the wireless communication system according to the present invention.

FIG. 10 is a longitudinal sectional view of a conventional heterojunction field effect transistor.

[Explanation of symbols]

11 ... sapphire (0001) substrate 12 ... undoped AlN buffer layer, 13 ... insulating film, 14,22 ... GaN buffer layer, 14a: GaN (1-101) facet surface, 15, 23 ... undoped InGaN electron transit layer, 16, 24 ... undoped AlGaN barrier layer, 17, 25 ... source electrode, 18, 27 ... gate electrode, 19, 26 ... drain electrode, 20, 28 ... high concentration n-type region, 21: GaN (1-101) substrate, 31, 32 ... heterojunction field effect transistor, 33 high frequency signal input terminal 34 input matching circuit, 35, 37 ... bias circuit, 36 ... Interstage matching circuit, 38 output matching circuit, 39 ... High-frequency signal output terminal 40: Power supply voltage terminal, 41 ... antenna, 42 ... RF block part, 43 ... baseband part, 44 ... handset, 45 ... Control unit, 46 ... transmitting unit, 50 ... Transmission power amplifier.

Claims (10)

[Claims] 1. A semiconductor device having at least an electron transit layer and a barrier layer, wherein a plane orientation of an interface between the electron transit layer and the barrier layer is (1-10).
1) A semiconductor device, characterized in that the threshold voltage for operation is 0 V or higher. 2. The semiconductor device according to claim 1, wherein at least one of the electron transit layer and the barrier layer is made of a nitride III-V compound semiconductor containing nitrogen as a group V element. A semiconductor device. 3. The semiconductor device according to claim 2, wherein said electron transit layer is made of In _x Ga ₁ -xN (0 ≦ x ≦ 1). 4. The semiconductor device according to claim 2, wherein the barrier layer is made of Al _y Ga _{1 -yN} (0 ≦ y ≦ 1). 5. The semiconductor device according to claim 1, wherein the electron transit layer and the barrier layer have an off angle from the (1-101) plane of 0 degree or more and 10 degrees. A semiconductor device formed on a substrate having the following main surface. 6. The semiconductor device according to claim 5, wherein said substrate is composed mainly of gallium and nitrogen. 7. A power amplifier using the semiconductor device according to claim 1 as a power amplification element. 8. A wireless communication system using the power amplifier according to claim 7. 9. A method for manufacturing a semiconductor device having at least an electron transit layer and a barrier layer, comprising: forming a buffer layer having a main surface having a (1-101) plane orientation; At least an electron transit layer and a barrier layer are formed, and the plane orientation of the interface between the electron transit layer and the barrier layer is changed.
A method for manufacturing a semiconductor device, comprising a step of forming a (1-101) plane. 10. The method for manufacturing a semiconductor device according to claim 9, wherein the buffer layer is formed on a substrate having a main surface having an off angle from the (1-101) plane of 0 ° or more and 10 ° or less. A method of manufacturing a semiconductor device.