JP2003344509A5 - - Google Patents

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Publication number
JP2003344509A5
JP2003344509A5 JP2003098935A JP2003098935A JP2003344509A5 JP 2003344509 A5 JP2003344509 A5 JP 2003344509A5 JP 2003098935 A JP2003098935 A JP 2003098935A JP 2003098935 A JP2003098935 A JP 2003098935A JP 2003344509 A5 JP2003344509 A5 JP 2003344509A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2003098935A
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JP2003344509A (ja
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Publication date
Priority claimed from US10/125,338 external-priority patent/US6762614B2/en
Application filed filed Critical
Publication of JP2003344509A publication Critical patent/JP2003344509A/ja
Publication of JP2003344509A5 publication Critical patent/JP2003344509A5/ja
Withdrawn legal-status Critical Current

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JP2003098935A 2002-04-18 2003-04-02 集積回路（ｉｃ）をテストする方法 Withdrawn JP2003344509A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/125,338 2002-04-18
US10/125,338 US6762614B2 (en) 2002-04-18 2002-04-18 Systems and methods for facilitating driver strength testing of integrated circuits

Publications (2)

Publication Number Publication Date
JP2003344509A JP2003344509A (ja) 2003-12-03
JP2003344509A5 true JP2003344509A5 (ja) 2006-04-13

Family

ID=29214776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003098935A Withdrawn JP2003344509A (ja) 2002-04-18 2003-04-02 集積回路（ｉｃ）をテストする方法

Country Status (4)

Country Link
US (2) US6762614B2 (ja)
JP (1) JP2003344509A (ja)
DE (1) DE10304880A1 (ja)
SG (1) SG115504A1 (ja)

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US7239170B2 (en) * 2003-07-08 2007-07-03 Lsi Corporation Apparatus and methods for improved input/output cells
JP3901151B2 (ja) * 2003-12-25 2007-04-04 セイコーエプソン株式会社 ドライバｉｃ並びにドライバｉｃ及び出力装置の検査方法
US7002365B2 (en) * 2003-12-30 2006-02-21 Intel Corporation Method and an apparatus for testing transmitter and receiver
WO2005073740A1 (ja) * 2004-01-29 2005-08-11 Advantest Corporation 試験装置及び試験方法
US6963212B2 (en) * 2004-03-23 2005-11-08 Agilent Technologies, Inc. Self-testing input/output pad
US7574634B2 (en) * 2004-06-21 2009-08-11 Micron Technology, Inc. Real time testing using on die termination (ODT) circuit
DE102004034606B4 (de) * 2004-07-16 2012-03-29 Infineon Technologies Ag Schaltungsanordnung aus einer elektronischen Testschaltung für einen zu testenden Transceiver und aus dem zu testenden Transceiver sowie Verfahren zum Prüfen eines Transceivers
US7323897B2 (en) * 2004-12-16 2008-01-29 Verigy (Singapore) Pte. Ltd. Mock wafer, system calibrated using mock wafer, and method for calibrating automated test equipment
US7342447B2 (en) * 2005-05-09 2008-03-11 Texas Instruments Incorporated Systems and methods for driving an output transistor
US20070124628A1 (en) * 2005-11-30 2007-05-31 Lsi Logic Corporation Methods of memory bitmap verification for finished product
US7881430B2 (en) * 2006-07-28 2011-02-01 General Electric Company Automatic bus management
US7541825B2 (en) * 2006-09-28 2009-06-02 Micron Technology, Inc. Isolation circuit
US7411407B2 (en) * 2006-10-13 2008-08-12 Agilent Technologies, Inc. Testing target resistances in circuit assemblies
US9391794B2 (en) * 2007-05-01 2016-07-12 Mentor Graphics Corporation Generating worst case test sequences for non-linearly driven channels
US7836372B2 (en) * 2007-06-08 2010-11-16 Apple Inc. Memory controller with loopback test interface
US7629849B1 (en) * 2008-06-02 2009-12-08 Mediatek Singapore Pte Ltd. Driving amplifier circuit with digital control
IT1392071B1 (it) * 2008-11-27 2012-02-09 St Microelectronics Srl Metodo per eseguire un testing elettrico di dispositivi elettronici
US8111564B2 (en) * 2009-01-29 2012-02-07 International Business Machines Corporation Setting controller termination in a memory controller and memory device interface in a communication bus
US8102724B2 (en) * 2009-01-29 2012-01-24 International Business Machines Corporation Setting controller VREF in a memory controller and memory device interface in a communication bus
US7974141B2 (en) * 2009-01-29 2011-07-05 International Business Machines Corporation Setting memory device VREF in a memory controller and memory device interface in a communication bus
US7978538B2 (en) * 2009-01-29 2011-07-12 International Business Machines Corporation Setting memory device termination in a memory device and memory controller interface in a communication bus
US7848175B2 (en) * 2009-01-29 2010-12-07 International Business Machines Corporation Calibration of memory driver with offset in a memory controller and memory device interface in a communication bus
US7990768B2 (en) * 2009-01-29 2011-08-02 International Business Machines Corporation Setting memory controller driver to memory device termination value in a communication bus
US20110140708A1 (en) * 2009-12-11 2011-06-16 William Henry Lueckenbach System, method, and apparatus for providing redundant power control using a digital output module
US8289784B2 (en) 2010-06-15 2012-10-16 International Business Machines Corporation Setting a reference voltage in a memory controller trained to a memory device
US8681571B2 (en) 2010-06-15 2014-03-25 International Business Machines Corporation Training a memory controller and a memory device using multiple read and write operations
KR20150026288A (ko) * 2013-09-02 2015-03-11 에스케이하이닉스 주식회사 반도체 장치 및 테스트 방법
DE102014113321B4 (de) * 2014-09-16 2023-06-01 Infineon Technologies Ag Chip und Verfahren zum Testen eines Chips
JP6438353B2 (ja) * 2015-05-27 2018-12-12 ルネサスエレクトロニクス株式会社 半導体装置及び診断テスト方法
US10319453B2 (en) * 2017-03-16 2019-06-11 Intel Corporation Board level leakage testing for memory interface
US11450378B2 (en) * 2020-09-29 2022-09-20 Micron Technology, Inc. Apparatuses and methods of power supply control for threshold voltage compensated sense amplifiers

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US5117129A (en) * 1990-10-16 1992-05-26 International Business Machines Corporation Cmos off chip driver for fault tolerant cold sparing
US5504432A (en) 1993-08-31 1996-04-02 Hewlett-Packard Company System and method for detecting short, opens and connected pins on a printed circuit board using automatic test equipment
US5682392A (en) 1994-09-28 1997-10-28 Teradyne, Inc. Method and apparatus for the automatic generation of boundary scan description language files
US5796260A (en) 1996-03-12 1998-08-18 Honeywell Inc. Parametric test circuit
DE19713748A1 (de) 1997-04-04 1998-10-08 Omicron Electronics Gmbh Verfahren und Vorrichtung zur Prüfung von Differentialschutzrelais/-systemen
US6275962B1 (en) 1998-10-23 2001-08-14 Teradyne, Inc. Remote test module for automatic test equipment
US6324485B1 (en) 1999-01-26 2001-11-27 Newmillennia Solutions, Inc. Application specific automated test equipment system for testing integrated circuit devices in a native environment
US6448865B1 (en) * 1999-02-25 2002-09-10 Formfactor, Inc. Integrated circuit interconnect system
US6397361B1 (en) 1999-04-02 2002-05-28 International Business Machines Corporation Reduced-pin integrated circuit I/O test
US6365859B1 (en) 2000-06-28 2002-04-02 Advanced Micro Devices Processor IC performance metric
US6556938B1 (en) * 2000-08-29 2003-04-29 Agilent Technologies, Inc. Systems and methods for facilitating automated test equipment functionality within integrated circuits
US6577980B1 (en) * 2000-11-28 2003-06-10 Agilent Technologies, Inc. Systems and methods for facilitating testing of pad receivers of integrated circuits
US6658613B2 (en) * 2001-03-21 2003-12-02 Agilent Technologies, Inc. Systems and methods for facilitating testing of pad receivers of integrated circuits

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