JP2003337157A - Dc test circuit and method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To turn a Pch transistor for controlling connection and disconnection of a pull-up resistor on and off by using an output of an update latch of an existing BSCAN circuit. <P>SOLUTION: A semiconductor device has a plurality of I/O buffers 200 connected between an internal logic circuit 102 and an external terminal, via the BSCAN circuit. In order to measure a value of the pull-up resistor 210, this DC test circuit for an LST switches states of the BSCAN circuit in a specified order, thereby setting a logic value of each of the I/O buffers 200 as a value having no influence on the measurement of the pull-up resistor 210. The on/off control of the Pch transistor 212 for connection and disconnection of the pull-up resistor 210 with a power source is enabled by using a measured value of the update latch 16a. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large number of external terminals for inputting / outputting signals (hereinafter, simply referred to as external terminals).
The present invention relates to an LSI DC test circuit and a test method for performing a DC test of a semiconductor device (hereinafter, referred to as an LSI) having the above.

[0002]

2. Description of the Related Art In recent years, the number of external terminals of an LSI is
Although the number of signal terminals is increasing, the current situation is that the increase in the number of signal terminals of LSI testers has not caught up with this.
In particular, LSI testers are extremely expensive, and have an extremely large number of pins.
The introduction of SI tester is not easy because it directly leads to an increase in product test cost. Therefore, a method of assigning a small number of LSI tester signal terminals to a plurality of LSI external terminals so that a test can be performed is under study.

For example, a first conventional example (Japanese Patent Laid-Open No. 10-13)
2902, Japanese Patent No. 3072718), in the "testing method of an integrated circuit having a large number of I / O signals", data is exchanged between the internal logic circuit 2 as shown in FIG. Side selector 4c, BSCAN
(Boundary Scan) register 5a, Update latch 6a, selector 4a, and EN (Enable) side BSCAN
Register 5a, Update latch 6a, Selector 4b
A plurality of input / output (I / O) buffers 20 connected to
LSI external terminals T1 and T
A method of performing a test by short-circuiting 2, T3 (hereinafter abbreviated as bundling) and connecting this LSI external terminal to one of the signal terminals of an LSI tester (not shown) is described.
According to this method, as shown in FIG. 32, the I / O buffer 20 to which a pull-up (or pull-down) resistor R1 is added is added.
If the LSI external terminals T1, T2, T3 that are used are bundled, the pull-up resistors connected to each I / O buffer are connected in parallel, so the resistance value is measured individually for each resistor. I can't.

Therefore, it is necessary to perform an alternative (indirect) test in which the individual resistance values are calculated from the measured values of the resistance groups connected in parallel. Even if such an alternative test is acceptable, even if an attempt is made to recalculate the standard value from the resistance value at the time of parallel connection to make a judgment, the parallel resistance value becomes low depending on the value and the number of resistors to be bundled. , When the impedance value on the LSI tester side is approached, it becomes difficult to perform stable measurement.

A second conventional example (Japanese Patent Laid-Open No. 2000-31)
In the "semiconductor integrated circuit device" disclosed in Japanese Laid-Open Patent Publication No. 4765), as shown in FIG. 33, a BSCAN register 5c, an Update latch 6c for turning on / off the PchTr12 for disconnecting the pull-up resistor R1, Since each circuit including the selector 24 is provided, each pull-up resistor R1 is individually turned on / off.
Therefore, although the problem of the method disclosed in the above-mentioned first conventional example has been solved, the case where a circuit for turning the pull-up resistor on and off is not provided for testing. In comparison, there is a problem that the test pattern becomes long during the test (= board test) by BSCAN in the device. This is the BSC in the board test.
Use the AN circuit to set the value of the LSI terminal and
The value set in the I terminal is observed, but in the board test, the BS for turning on / off the unused resistor
This is because the test pattern becomes long because the pattern is also shifted to the CAN register.

[0006]

As described above, the conventional LS is used.
The test circuit and test method of I have a problem that the values of the pull-up resistors cannot be individually measured or the test pattern at the time of measurement becomes long.

The present invention has been made in view of the above circumstances, and in an LSI having a large number of external terminals,
When performing a DC test to check the pull-up / pull-down resistance value, you can perform a test by bundling multiple external terminals and individually measure the pull-up / pull-down resistance value, as well as a test pattern during measurement. It is an object of the present invention to provide a DC test circuit and method for an LSI that does not need to be lengthened.

[0008]

In order to solve the above problems, the present invention relates to a DC test circuit of a semiconductor device, which is connected between an internal logic circuit and an external terminal via a boundary scan circuit. In a semiconductor device having a plurality of buffers, in order to measure the value of pull-up (or pull-down) resistance connected to each external terminal,
By switching the states of the boundary scan circuit in a predetermined order, the logical value of each buffer is set to a value that does not affect the measurement of the pull-up (or pull-down) resistance, and the pull-up (or pull-down) resistance is set. The control element for connecting or disconnecting the power supply (or ground) with the power supply (or ground) is configured to be on / off controllable by using a set value in the boundary scan circuit.

A second aspect of the present invention relates to the DC test circuit of the semiconductor device according to the first aspect, wherein the buffer is an input / output buffer or a three-state output buffer, and the set value in the boundary scan circuit is set. Is the logical value of the update latch on the data side in the boundary scan circuit.

The invention according to claim 3 relates to the DC test circuit of the semiconductor device according to claim 1, wherein the buffer is an input buffer or a two-state output buffer,
The set value in the boundary scan circuit is a logical value of an update latch in the boundary scan circuit.

Further, the invention according to claim 4 relates to the DC test circuit of the semiconductor device according to claim 1, wherein the buffer is an input / output buffer or a three-state output buffer, and the set value in the boundary scan circuit is set. Is a logical value of the boundary scan register on the data side in the boundary scan circuit.

The invention according to claim 5 relates to the DC test circuit of the semiconductor device according to claim 1, wherein the buffer is an input buffer or a two-state output buffer,
The set value in the boundary scan circuit is a logical value of a boundary scan register in the boundary scan circuit.

Further, the invention according to claim 6 relates to the DC test circuit of the semiconductor device according to claim 1, wherein the buffer is an input / output buffer or a three-state output buffer, and the set value in the boundary scan circuit is set. Is an inverted output value of the logical value of the boundary scan register on the enable side in the boundary scan circuit.

The invention according to claim 7 relates to the DC test circuit for a semiconductor device according to claim 1, wherein the buffer is an input buffer or a two-state output buffer,
The set value in the boundary scan circuit is an inverted output value of the logical value of the boundary scan register in the boundary scan circuit.

The invention according to claim 8 relates to the DC test circuit of the semiconductor device according to claim 1, wherein the buffer is an input / output buffer or a three-state output buffer, and the set value in the boundary scan circuit is set. Is the output value of the selector that selects the output of the update latch on the data side in the boundary scan circuit.

The invention according to claim 9 relates to the DC test circuit of the semiconductor device according to claim 1, wherein the buffer is an input buffer or a two-state output buffer,
The set value in the boundary scan circuit is an output value of a selector that selects the output of the update latch in the boundary scan circuit.

The invention according to claim 10 relates to a DC test method for a semiconductor device, wherein the semiconductor device has a plurality of buffers connected between an internal logic circuit and an external terminal via a boundary scan circuit, When measuring the value of the pull-up (or pull-down) resistance connected to each of the external terminals, by switching the states of the boundary scan circuit in a predetermined order, the logical value of each buffer is pulled up (or The pull-down resistance is set to a value that does not affect the measurement, and the control element for connecting or disconnecting the pull-up (or pull-down) resistance to the power supply (or ground) is set using the set value in the boundary scan circuit. It is characterized by performing on / off control.

The invention described in claim 11 is the same as claim 1.
0. A semiconductor device DC test method according to 0, wherein when the buffer is an input / output buffer or a 3-state output buffer, a logical value of an update latch on a data side in the boundary scan circuit is set in the boundary scan circuit. It is used as a value.

The invention of claim 12 is the same as claim 1
0. A semiconductor device DC test method according to 0, wherein, when the buffer is an input buffer or a two-state output buffer, a logical value of an update latch in the boundary scan circuit is used as a set value in the boundary scan circuit. Is characterized by.

The invention according to claim 13 is the same as claim 1.
0. In the semiconductor device DC test method according to 0, when the buffer is an input / output buffer or a three-state output buffer, the logical value of the boundary scan register on the data side in the boundary scan circuit is set to a value in the boundary scan circuit. The feature is that it is used as a set value.

The invention according to claim 14 is the same as claim 1.
0. A semiconductor device DC test method according to 0, wherein, when the buffer is an input buffer or a two-state output buffer, a logical value of a boundary scan register in the boundary scan circuit is used as a set value in the boundary scan circuit. It is characterized by that.

The invention of claim 15 is the same as claim 1
0. A semiconductor device DC test method according to 0, wherein when the buffer is an input / output buffer or a 3-state output buffer, an inverted output value of a logical value of a boundary scan register on the enable side in the boundary scan circuit is set to the boundary output value. It is characterized by being used as a set value in the scan circuit.

The invention of claim 16 is the same as that of claim 1
0. A semiconductor device DC test method according to 0, wherein, when the buffer is an input buffer or a 2-state output buffer, an inverted output value of a logical value of a boundary scan register in the boundary scan circuit is stored in the boundary scan circuit. The feature is that it is used as a set value.

The invention according to claim 17 is the same as claim 1.
0. A semiconductor device DC test method according to 0, wherein when the buffer is an input / output buffer or a 3-state output buffer, the output value of a selector that selects the output of the data side update latch in the boundary scan circuit is It is characterized by being used as a set value in the boundary scan circuit.

The invention according to claim 18 is the first aspect.
0. A semiconductor device DC test method according to 0, wherein when the buffer is an input buffer or a two-state output buffer, an output value of a selector for selecting an output of an update latch in the boundary scan circuit is set in the boundary scan circuit. It is characterized in that it is used as a set value of.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using the embodiments. First Embodiment FIG. 1 is a block diagram showing the configuration of a DC test circuit for an LSI according to the first embodiment of the present invention, in which the external terminals are input / output terminals, and FIG. FIG. 3 is a circuit diagram showing the configuration of the TAP in the DC test circuit of the LSI.
FIG. 4 is a circuit diagram showing the configuration of the instruction decoder in the DC test circuit of the LSI of this embodiment.
A diagram showing a state diagram of the AP circuit, FIG.
FIG. 6 is a circuit diagram showing a state in which the external terminals of three data input / output circuits are bundled in the LSI DC test circuit of the present embodiment. FIG. 6 shows the operation of the LSI DC test circuit of the present embodiment. FIG. 7 is a flowchart for explaining the LS of this embodiment.
In the DC test circuit of I, the circuit diagram showing the configuration in the case where the external terminal is the input terminal is shown in FIG.
FIG. 9 is a diagram showing the configuration of one data input circuit in the DC test circuit of FIG. 9, and FIG. 9 is a circuit diagram showing the configuration when the external terminal is a 3-state output buffer in the DC test circuit of the LSI of the present embodiment, FIG. 10 shows the LS of this embodiment.
FIG. 11 is a diagram showing the configuration of one 3-state data output circuit in the DC test circuit of I, and FIG. 11 is an LS of the present embodiment.
FIG. 12 is a circuit diagram showing a configuration of the DC test circuit of I when the external terminal is a 2-state output buffer.
It is a figure which shows the structure of one 2-state data output circuit in the DC test circuit of LSI of a present Example.

The DC test circuit of the LSI of this example shown in FIG. 1 shows a case where the external terminal is an input / output (I / O) terminal, and a desired function is provided on the LSI substrate 101. The case where the internal logic circuit 102 for realizing the above and the data input / output circuits 111a, 111b, and 111c are included is illustrated.

The first data input / output circuit 111a is an input / output (I / O) buffer 200 for exchanging logic signals between the internal logic circuit 102 and the outside of the LSI, and one end is an I / O.
Pull-up resistor 2 connected to the output terminal of buffer 200
10 and a Pch transistor (Tr) 212 for turning on / off the connection between the other end of the pull-up resistor 210 and the power supply.
, And one input for switching the signal for turning ON / OFF the PchTr212 is connected to "0" (= GND), and the other input is updated on the data side (Updat).
e) Selector 214 connected to the output of latch 16a
And a data side BSCAN register 15a of the boundary scan (BSCAN) circuit and a BSCAN register 15
Update latch 16 for holding the output state of a
It has a schematic configuration in which a and a are provided. I / O buffer 2
The LSI external terminal OT1 to which the output terminal A of 00 is connected is
It is short-circuited (bundled) with other external terminals by an LSI tester (not shown) outside the LSI substrate 101 or a jig (not shown) that connects the LSI substrate 101 and the LSI tester signal terminal.

Further, the I / O buffer 200 and the BSCA
The connection with the N circuit is as follows. First I /
In the O buffer 200, one end of the pull-up resistor 210 is connected to the bidirectional external terminal A, the output of the selector 14a is connected to the data input B, and the enable (EN) input C is connected.
Is connected to the output of the NOR circuit 17, and the data output D is connected to the input NO2 of the internal logic circuit 102 and the selector 14
The selection input whose switching input value of c is "0" is connected. The pull-up resistor 210 has one end connected to the bidirectional external terminal A of the I / O buffer 200 and the other end Pch.
It is connected to the drain of Tr212.

The selector 214 has a switching input value of "
"0" (= GND) is connected to the selection input of 0 ",
The output of the update latch 16a on the data side is connected to the selection input of "1", and the switching input has TAP (Test Access
Port) DC of circuit 10 TEST control signal MODE R
Is connected, the output is pulled up, and the connection of the resistor 212 is turned on.
It is connected to the gate of PchTr212 for turning on / off. The PchTr 212 has a selector 21 at the gate.
4 is connected, the power source (= VDD) is connected to the source, and the other end of the pull-up resistor 210 is connected to the drain. The AND gate 18 has one input (logical inversion) for the BSCAN control signal M of the TAP circuit 10.
The ODE1 is connected, the output of the selector 14b is connected to the other input, and the output is connected to the switching input of the selector 14c.

In the selector 14a, the switching input value is "
The output HO1 of the internal logic circuit 102 is connected to the selection input of "0", the output of the data side Update latch 16a is connected to the selection input of "1", and the BSCAN control signal MODE1 of the TAP circuit 10 is connected to the switching input. In the selector 14b, the output HO3 of the internal logic circuit 102 is connected to the selection input whose switching input value is "0",
Enable (EN) side Update for 1 ”selection input
The output of the latch 16b is connected, and the switching input is TAP
The BSCAN control signal MODE1 of the circuit 10 is connected.

In the NOR gate 17, one input (logical inversion) is connected to the output of the selector 14b, the other input is connected to the BSCAN control signal MODE2 of the TAP circuit 10, and the output is the EN terminal of the I / O buffer 200. It is connected to C. The selector 14c has a switching input value of "
Data output D of I / O buffer 200 for selection input of 0 "
, The output of the selector 14a is connected to the selection input of "1", and the output of the AND gate 18 is connected to the switching input.

The data side BSCAN register 15a is set to P
The output of the selector 14c is connected to the IN input, and SFDR
The BSCAN control signal SFDR of the TAP circuit 10 is connected to the input, and the BSCA of the TAP circuit 10 is connected to the CLKDR input.
The N control signal CLKDR is connected, the POUT output is connected to the data input of the data side Update latch 16a, the BSIN input is connected to the BSOUT of the EN side BSCAN register 15b, and the BSOUT output is the TAP circuit 1
BS of 0 Connected to SIN.

The EN side BSCAN register 15b is a PI
The output HO3 of the internal logic circuit 102 is connected to the N input,
The BSCAN control signal S of the TAP circuit 10 is input to the SFDR input.
The FDR is connected, the BSCAN control signal CLKDR of the TAP circuit 10 is connected to the CLKDR input, the POUT output is connected to the data input of the EN side Update latch 16b, and the second data input / output circuit 111 is connected to the BSIN input.
BSOUT of b is connected, and BSOUT output is connected to BSIN of the data side BSCAN register 15b.

The data-side Update latch 16a receives the POU of the data-side BSCAN register 15a for data input.
The T output is connected, the clock input (G = UPDDR) is connected to the UPDDR of the TAP circuit 10, and the output is connected to the switching input value of the selector 14a whose selection input value is "1". The EN side Update latch 16b has a data input connected to the POUT output of the EN side BSCAN register 15b, and a TAP input to a clock input (G = UPDDR).
The UPDDR of the circuit 10 is connected to the output of the selector 14
The switching input value of b is connected to the selection input of "1".

The circuit related to the second data input / output circuit 111b is such that the data side BSCAN register 15a is BS
OUT is a BS on the EN side of the first data input / output circuit 111a.
Connected to BSIN of CAN register 15b, EN side B
In the SCAN register 15b, BSIN of the third data input / output circuit 111c is connected to BSIN, and the bidirectional external terminal A of the I / O buffer 200 is the LSI external terminal OT2.
Other than that, it is connected similarly to the first data input / output circuit 111a. The circuit related to the third data input / output circuit 111c is a data side BSCA.
The N register 15a uses BSOUT as the BS of the EN side BSCAN register 15b of the second data input / output circuit 111b.
Connected to IN, the EN side BSCAN register 15b is
BSIN of TAP circuit 10 to BSIN OUT is connected,
The bidirectional external terminal A of the I / O buffer 200 is connected to the LSI external terminal OT3, but other than that, it is connected similarly to the first data input / output circuit 111a.

2 and 3 are MODEs for the DC test mode of this example in the TAP circuit of the BSCAN circuit defined by IEEE1149.1. 2 is a block diagram showing a circuit configuration when an R signal is added, and FIG. 2A is a symbol of the TAP circuit 10, and FIG.
3B is a circuit diagram of the TAP circuit 10, FIG. 3A is a symbol of the instruction decoder 11, and FIG.
3B is a circuit diagram of the instruction decoder 11, and FIG. 3C is a truth table of the instruction decoder. FIG. 4 shows the IEEE114.
TAP of BSCAN circuit as defined by 9.1
3 is a state diagram showing state transitions in a circuit.

The TAP circuit 10 is a state machine for controlling the state transition of the BSCAN circuit, and in response to the two signals of TCK and TMS, it transits the state diagram shown in FIG.
Send test and control signals to the BSCAN circuit. TCK (Test Clock Input) is for all test
This is a clock signal for clocking operation and scan operation. TMS (Test Mode Se
lect Input) is a control signal for selecting the test mode. TDI (Test Data Input) is an input of test data and is composed of serial shift data. TDO (Test Data Output) is an output of test data and is composed of serial shift data. TRST (Test ResetInput) is TA
This is a signal for asynchronously resetting the P circuit 10.

CLKDR (Clock DR) is the BSC
A clock signal for the AN circuit, which corresponds to TCK and changes in the same manner as TCK. UPDDR (Update DR
) Holds the latch in the BSCAN circuit in its current state during the shift operation. SFDR (Sh
ift DR) controls the loading and shifting cycles of data to the registers in the BSCAN circuit. E
N (Enable) controls the tri-state output buffer of TDO. BSCAN control signal MODE1,
MODE2 and DC TEST control signal MODE R is set according to the test mode by the instruction decoder 11 shown in FIG.

In the state diagram shown in FIG. 4, the present invention is concerned with Select. DR Sc
an and Capture DR and Shift DR
And Exit1 DR and Updatr It is DR.
The transition between the states occurs according to the "H" and "L" states of TMS. Select DR In Scan, a specific function is never executed,
Transition to the next state at the next TCK cycle. Captu
re In DR, if the selected register has a parallel input, the data is captured in the register, but if the register does not have a parallel input,
Or if the selected test does not require capturing, the register state does not change. Shift
In DR, the data passes through the selected register to T
Serially shifted from DI to TDO. Exit1
In DR, the shifting process ends. Updatr In DR, if the selected register has a parallel output, the data is updated during this state and the register retains its state.

For explaining the operation of this example, FIG. 5 shows a state in which the external terminals of the three data input / output circuits are bundled. From the circuit diagram shown in FIG. NOR gate 17 and AND gate 18 of the BSCAN circuit of the output circuit and respective control signals SFDR, CLKDR, UPD
DR, MODE R, MODE1 and MODE2 are omitted. In the following, each BSCA
"X" in the N register indicates that it takes a value of "1" or "0", and "1" or "0" in each Update latch indicates a value held during the DC test.
FIG. 6 is a flowchart showing the operation of the LSI in this example.

The operation of this example will be described below with reference to FIGS. First, the setting of the DC test mode in the DC test circuit having many I / O terminals will be described. In addition, BSCAN operation (TAP
IE for the circuit operation transition = including mode change)
Since it is defined in EE1149.1 and is well known to those skilled in the art, its details are omitted.

First, as shown at 400 in FIG. 6, the BSC
DC in the mode setting operation of AN Set to TEST mode
To do. As shown in FIG. 3C, DC TEST mode
Then, the BSCAN control signals MODE1 = 1 and MODE2
= 0, DC TEST control signal MODE R = 1
It Therefore, the BS of the I / O buffer 200 shown in FIG.
The CAN circuit has Upd on both the data side and the EN side.
The values of the ate latches 16a and 16b indicate the I / O buffer
The logical value is determined, and the PchTr212 is turned ON / O.
FF depends on the value of the data side Update latch 16a.
To decide.

Next, by the operation of mode setting of BSCAN, Shift Set to DR mode (40
1), Shift DR operation, TDI to BSCAN
Shift the value into the register. At this time, 40 in FIG.
By the judgment NO of 2, all I /
A value "0" is set in the BSCAN register 15b on the EN side so that the O buffer 200 is in the input mode, and Pc is set in all the BSCAN registers 15a on the data side.
Set the value "1" to turn off hTr212 (Fig. 6
403). That is, BSCAN on all data sides
Set "1" to the register and "1" to the BSCAN register on the EN side.
0 "is shifted and input. In the following, I / O will be performed.
The buffer (and the 3rd output buffer described later) is "
It is assumed that the input mode and the output value Z (Hi-Z = high impedance: hereinafter referred to as Z) are set to 0 ".

Shift input (Shift) DR) is completed, Shift DR → Exit1 DR → Upd
ate The mode of TAP is switched in the order of DR (405 in FIG. 6), and Update is performed. By the operation of DR, B
The value of the SCAN register 15a is updated by the update latch 16
It is taken into a (406 of FIG. 6). As a result, all the I / O buffers 200 are set to the input mode, and the PchTr 212 is turned off.
0 is in a separated state.

Next, Update DR → Select
DR scan → Capture DR → Shift
Switching the TAP mode in the order of DR (40 in FIG. 6)
7, determination NO of 408 in FIG. 6, determination YE of 402 in FIG.
S), EN side BSCAN register 15b all "
0 "and the data side BSCAN register 15a is set to the first
Data input / output circuit 111a is "0", other is "1"
Is shifted in (404 in FIG. 6).

Shift input (Shift) DR) is completed, Shift DR → Exit1 DR → Upda
te Switch the TAP mode in the order of DR (see FIG. 6).
405), Update By the operation of DR, BS
The value of the CAN register 15a is changed to the Update latch 16
It is taken into a (406 of FIG. 6). As a result, all the I / O buffers 200 are in the input mode and only the pull-up resistor 210 of the first I / O buffer 200 is connected. In this state, the value of the pull-up resistor is measured by the conventional method to
Of the pull-up resistor 212 of the I / O buffer 200 of
Defects can be determined.

Similarly, Update DR → Selec
t DR scan → Capture DR → Shif
t The TAP mode is switched in the order of DR (4 in FIG. 6).
07, judgment 408 of FIG. 6, judgment Y of 402 of FIG.
ES), all of the EN side BSCAN register 15 "
0 ", the data side BSCAN register 15 is set to" 0 "only for the second data input / output circuit 111b, and the other is set to" 0 ".
1 "is shift input (404 in FIG. 2). Shift input (Shift) DR) is completed, Shift DR
→ Exit1 DR → Update TAP in the order of DR
Switch the mode (405 in Fig. 2), Update
The value of the BSCAN register 15a is changed to Upd by the DR operation.
It is taken into the ate latch 16a (406 in FIG. 2). As a result, all the I / O buffers 200 are set to the input mode, and only the pull-up resistor 210 of the second I / O buffer 200 is connected. Therefore, in this state, the pull-up resistor 210 is used to pull-up. If the resistance value is measured, the pull-up resistor 21 of the second I / O buffer 200
It is possible to make a judgment of good / bad of 0.

The resistance value of the pull-up resistor 210 of the third I / O buffer 200 can also be measured by the same procedure.

The DC test circuit of the LSI of this example is not limited to the case where the external terminal is an input / output (I / O) terminal, but the external terminal is an input terminal and has an input buffer instead of the input / output buffer. It can also be applied in cases. Hereinafter, an example in this case will be described. The LS of this example shown in FIG.
The DC test circuit of I shows a case where the external terminal is an input terminal, and an internal logic circuit 102 that realizes a desired function and data input circuits 112a, 112b, and 112c are provided on the LSI substrate 101. It illustrates the case of having.

In FIG. 7, as compared with the case where the external terminal shown in FIG. 1 is an input / output terminal, in each data input circuit, the EN side BSCAN register, the Update latch, the selectors 14a, 14b, and the NOR gate. 1
7, AND gate 18 is omitted, and further, input buffer 2
The output of 01 is directly input to the BSCAN register 15, the output NO1 of the selector 14d is independently connected to the internal logic circuit 102, and the BSOUT output of the data input circuit of the previous stage is directly input to the data input circuit of the next stage. The difference is that it is connected to BSIN of.

FIG. 8 shows the configuration of one data input circuit in the DC test circuit of the LSI shown in FIG. Hereinafter, with reference to the partial circuit shown in FIG.
The operation of the DC test circuit of the LSI in this example will be described.

As shown in FIG. 7, each input buffer 201
As in the case of the I / O buffer 200 shown in FIG.
When bundled on the LSI tester side, "1" is shift-input to the BSCAN registers of all input buffers 201. Shift input (Shift DR) is completed, Shift DR → Exit 1 DR → Upd
ate TAP mode is switched in the order of DR, Upd
ate Depending on the operation of DR, the BSCAN register 15
The value of is fetched into the Update latch 16. As a result, in all input buffers 201, PchTr
Since 212 is OFF, the pull-up resistor 210 is disconnected.

Next, Update DR → Select
DR scan → Capture DR → Shift
The mode of TAP is switched in the order of DR and each BSCAN record is
For the register 15, the first data input circuit 112a
Only shift "0" to other data input circuit.
1 "shift input, shift input (Shift D
When R) is completed, Shift DR → Exit 1
DR → Update Turn off TAP mode in the order of DR
Change, Update By the operation of DR, BSCAN
The value of register 15 is fetched to Update latch 16
Mu. This allows the puller of the first input buffer 201 to
This is because only the resistor 210 is connected.
Then, measure the value of the pull-up resistance by the conventional method.
The pull-up resistor 2 of the first input buffer 201.
Ten good / bad judgments can be made.

In the same procedure, the second input buffer, the third
The resistance value of the pull-up resistor 210 of the input buffer can also be measured.

The DC test circuit of the LSI of this example can be applied not only when the external terminal is an input / output terminal but also when the external terminal is an output terminal and has an output buffer instead of the input / output buffer. . Hereinafter, an example in this case will be described.

The DC test circuit of the LSI of this example shown in FIG. 9 shows a case where the external terminal is an output terminal, and an internal logic circuit for realizing a desired function is provided on the LSI substrate 101. 10 illustrates a case where it has 102 and three-state (st) data output circuits 114a, 114b, 114c.

In FIG. 9, compared with the case where the external terminal shown in FIG. 1 is an input / output terminal, the AND gate 18 is omitted in each 3st data output circuit, and the EN side BSC is omitted.
The BSOUT output of the AN register 15b is directly connected to BSI.
The difference is that N is input to the BSCAN register 15a on the data side.

FIG. 10 shows the configuration of one 3-state (st) data output circuit in the DC test circuit of the LSI shown in FIG. The operation of the DC test circuit of the LSI in this example will be described below with reference to the partial circuit shown in FIG.

As shown in FIG. 9, each 3st output buffer 203 is similar to the I / O buffer 200 shown in FIG.
When bundled on the LSI tester side, all 3
The value of the st output buffer 203 is set in the BSCAN register 15b on the EN side so that the st output buffer 203 is in the "Z" (Hi-Z) state.
Set 0 "and set P to all Update latches 16a.
Set the value "1" to turn off chTr212. That is, all the data side BSCAN registers 15a
Shift input "1" to and shift input "0" to the BSCAN register 15b on the EN side.

Shift input (Shift) DR) is completed, Shift DR → Exit1 DR → Upda
te The mode of TAP is switched in the order of DR, and Up
date Depending on the operation of DR, BSCAN register 1
The value of 5a is fetched in the Update latch 16a. As a result, all the 3st output buffers 203 are set to the output value "Z" and the PchTr 212 is set to O.
Because of FF, the pull-up resistor 210 is in a disconnected state.

Next, Update DR → Select
DR scan → Capture DR → Shift
Change the TAP mode in the order of DR to
Shift input "0" to all BSCAN register 15b
However, for the data side BSCAN register 15a,
Shift "0" only for 1st 3st data output circuit 113a
Input and shift "1" to other 3st data output circuit
input. Then, the shift input (Shift DR)
When complete, Shift DR → Exit1 DR → Up
date Change the TAP mode in the order of DR, U
pdate Depending on the operation of DR, BSCAN register 15
The value of a is fetched in the Update latch 16a.

As a result, all the 3st output buffers 203 have the output value "Z" and the first 3st
Only the pull-up resistor 210 of the output buffer 203 is connected. In this state, if the value of the pull-up resistor is measured by a conventional method, it is possible to determine whether the pull-up resistor 210 of the first 3st output buffer 203 is good or bad.

Similarly, Update DR → Selec
t DR scan → Capture DR → Shif
t The TAP mode is switched in the order of DR, all "0" s are shift-inputted to the EN side BSCAN register 15b, and only the second 3st data output circuit 113b is "0" for the data side BSCAN register 15a.
Shift input to other 3st data output circuit,
1 "is shift-inputted, and shift-input (Shift
When R) is completed, Shift DR → Exit1
DR → Update Change the TAP mode in the order of DR, and then Update The value of the BSCAN register 15a is taken into the Update latch 16a by the DR operation.

As a result, all the 3st output buffers 203 have the output value "Z", and the second 3st output buffer 203 has the output value "Z".
Only the pull-up resistor 210 of the output buffer 203 is connected. In this state, if the value of the pull-up resistor is measured by a conventional method, it is possible to determine whether the pull-up resistor 210 of the second 3st output buffer 203 is good or bad.

Similarly, the third 3st output buffer 2
The value of the 03 pull-up resistor 210 can also be measured.

The DC test circuit of the LSI of this example shown in FIG. 11 shows a case where the external terminal is an output terminal, and an internal logic circuit for realizing a desired function is provided on the LSI substrate 101. In this example, the case 102 and the two-state (st) data output circuits 113a, 113b, and 113c are illustrated.

In FIG. 11, compared with the case where the external terminal shown in FIG. 1 is an input / output terminal, in each 2st data output circuit, the EN side BSCAN register, Upd.
The ATE latch, the selectors 14b and 14c, the NOR gate 17 and the AND gate 18 are omitted, and the output HO1 of the internal logic circuit 102 is directly connected to the BSCAN register 1.
5, and the BSOUT output of the 2nd data output circuit of the previous stage is directly connected to BSIN of the 2st data output circuit of the next stage.

FIG. 12 shows the DC of the LSI shown in FIG.
2 shows a configuration of one 2-state (st) data output circuit in the test circuit. Hereinafter, with reference to the partial circuit shown in FIG. 12, the DC of the LSI in this example
The operation of the test circuit will be described.

Each 2nd output buffer 202 shown in FIG.
The pull-up resistors 210 can also be turned ON / OFF individually, but since the outputs of the respective 2st output buffers 202 are not the same, a bus fight will occur, so they cannot be bundled. However, BSCAN register 15 and Up
It is possible to turn off the pull-up resistor 210 without adversely affecting other measurements by setting the value for turning off the PchTr 212 in the date latch 16, which allows the specific pull-up resistor 210 to be turned off. Only 210 is turned on, and each 2nd output buffer 202
It is possible to judge whether the pull-up resistor 210 is good or bad.

As described above, according to the LSI DC test circuit of this example, in order to turn ON / OFF the pull-up resistor 210, the logical value for controlling the PchTr 212 is obtained as the output of the Update latch of the existing BSCAN circuit. Since it is set to PchT
BSC of dedicated BSCAN circuit for control of r212
The AN register and Update latch can be eliminated. Furthermore, in the board test of the device, BS
Although the CAN circuit is used to set a value to the LSI external terminal or observe the value set to the LSI external terminal, it is not used in such a board test. PchTr2
It is not necessary to increase the number of shift patterns because the BSCAN register of the 12 control dedicated BSCAN circuit is unnecessary.

In the first embodiment, the case where the pull-up resistor is connected to the LSI external terminal is shown.
The present invention can be applied to the case where a pull-down resistor is used instead of the pull-up resistor. Hereinafter, an example in this case will be described.

Second Embodiment FIG. 13 is a circuit diagram of a DC test circuit for an LSI according to a second embodiment of the present invention, showing a state in which the external terminals of two data input / output circuits are bundled, and FIG. Is the LSI of this embodiment
15 is a diagram showing the configuration of one data input / output circuit in the DC test circuit of FIG. 15, FIG. 15 is a diagram showing the configuration of one data input circuit in the DC test circuit of the LSI of this embodiment, and FIG. FIG. 17 is a diagram showing the configuration of one 3-state data output circuit in the LSI DC test circuit of the present embodiment. FIG. 17 is a configuration of one 2-state data output circuit in the LSI DC test circuit of the present embodiment. FIG. 18 is a circuit diagram showing a DC test circuit of the LSI of the present embodiment, showing a state in which the external terminals of the data input / output circuit with pull-up resistor and the data input / output circuit with pull-down resistor are bundled. .

FIG. 13 shows a state in which the external terminals of the two data input / output circuits are bundled for explaining the operation of this example. The NOR gate 17 of the BSCAN circuit of each data input / output circuit is shown in FIG. AND gate 18 and each control signal S
FDR, CLKDR, UPDDR, MODE R, MO
It is shown by omitting DE1 and MODE2. In the LSI DC test circuit of this example, the pull-up resistor 210 is changed to a pull-down resistor 211 as shown in FIG.
The Tr212 is changed to the Nch transistor (Tr) 213, and one input of the selector 214 is "0" (= GN
The difference is that it is changed from D) to "1" (= VDD).

FIG. 14 shows the DC of the LSI shown in FIG.
3 shows a configuration of one data input / output circuit in the test circuit. In the following, in order to simplify the description, in the case of the first embodiment, the overall block configuration diagrams as shown in FIG. 1, FIG. 7, FIG. The description will be given using only the partial circuit diagram in this case.

When the external terminal is an input / output terminal, this
The example DC test circuit of the LSI is
DC omitted in FIG. TEST control signal MO
DE R is connected to the switching input of the selector 214
There is. Further, the AND gate 18 receives one input (logical
BSCAN control signal MODE1 is connected to
The output of the selector 14b is connected to the input of the
It is connected to the switching input of the actuator 14c. selector
The switching inputs of 14a and 14b are connected to MODE1.
Has been. The NOR gate 17 receives one input (logical
Output of selector 14b is connected to the other input
MODE2 is connected and output is from I / O buffer 200
It is connected to the EN terminal.

Hereinafter, with reference to the partial circuit shown in FIG.
The operation of the DC test circuit of the LSI in this example will be described. Depending on the mode setting operation of BSCAN, DC T
Set to EST mode. As shown in FIG. 3, DC
In TEST mode, BSCAN control signal MODE1
= 1, MODE2 = 0, DC TEST control signal MOD
E R = 1. Therefore, the BSCAN circuit of the data input / output circuit shown in FIG.
The logical value of the I / O buffer 200 is determined by the value of the Update latch, and the NchTr 213 is turned on / off.
Is determined by the value of the data side Update latch 16a.

Next, Shift DR operation causes T
Shift in values from DI to BSCAN register. At this time, a value "" is set in the BSCAN register 15b on the EN side so that all the I / O buffers 200 are in the input mode.
0 "is set and all data side BSCAN
Value that turns off NchTr 213 in register 15a
Set "0". That is, BS on all data side
"0" is shift-input to the CAN register 15a, and "0" is shift-input to the BSCAN register 15b on the EN side.

Shift input (Shift) DR) is completed, Shift DR → Exit1 DR → Upd
ate The mode of TAP is switched in the order of DR, and Up
date Depending on the operation of DR, BSCAN register 1
The value of 5a is fetched in the Update latch 16a. As a result, all the I / O buffers 200 are set to the input mode, and the NchTr 213 is turned off, so that the pull-down resistor 211 is disconnected.

Next, Update DR → Select
DR scan → Capture DR → Shift
The TAP mode is switched in the order of DR, and the BS on the EN side
All the CAN register 15b becomes "0", and the data side
First data input to the BSCAN register 15a
Only the output circuit becomes "1", and all other data input / output circuits
Shift-inputs so that it becomes "0". Shift input
(Shift DR) is completed, Shift D
R → Exit 1 DR → Update TA in the order of DR
Switch the P mode to Update For DR operation
Therefore, the value of the BSCAN register 15a is updated.
It is taken into the latch 16a.

As a result, all I / O buffers 2
00 becomes the input mode, and only the pull-down resistor 211 of the first I / O buffer 200 is connected. In this state, if the pull-down resistance value is measured by a conventional method, it is possible to determine whether the pull-down resistance 211 of the first I / O buffer 200 is good or bad.

Similarly, Update DR → Selec
t DR scan → Capture DR → Shif
t The TAP mode is switched in the order of DR, all "0" s are input to the BSCAN register 15b on the EN side, and only "1" is input to the second data input / output circuit for the BSCAN 15a on the data side. All data input / output circuits perform shift input so as to input "0". Shift input (Shift DR) is completed, Shif
t DR → Exit1 DR → Update Change the TAP mode in the order of DR, and then Update The value of the BSCAN 15a is taken into the Update latch 16a by the operation of DR. This allows all I / O
The buffer 200 is in the input mode and the second I
Since only the pull-down resistor 211 of the I / O buffer 200 is connected, if the value of the pull-down resistor is measured by the conventional method in this state, the pull-down resistor 211 of the second I / O buffer 200 is good / defective. Can be determined.

Similarly, the third I / O buffer 200
The value of the pull-down resistor 211 can also be measured.

The DC test circuit of the LSI of this example is not limited to the case where the external terminal is an input / output (I / O) terminal, but the external terminal is an input terminal and has an input buffer instead of the input / output buffer. It can also be applied in cases. Hereinafter, an example in this case will be described. The L of this example shown in FIG.
The SI DC test circuit shows one data input circuit when the external terminal is an input terminal.

Hereinafter, with reference to the partial circuit shown in FIG.
The operation of the DC test circuit of the LSI in this example will be described. The input buffer 201 shown in FIG.
Similar to the O buffer 200, when they are bundled on the LSI tester side, BSCA of all input buffers 201
Shift input "0" to the N register 15. Shift input (Shift DR) is completed, Shift D
R → Exit 1 DR → Update TA in the order of DR
Switch the P mode to Update The value of the BSCAN register 15 is taken into the Update latch 16 by the operation of DR. As a result, in all the input buffers 201, since the NchTr 213 is OFF, the pull-down resistor 211 is disconnected.

Next, Update DR → Select
DR scan → Capture DR → Shift
Switching the TAP mode in the order of DR,
For the transistor 15, only the first data input circuit "
1 "and all other data input circuits are" 0 ".
Shift input. Shift input (Shift
DR) is completed, Shift DR → Exit1
DR → Update Turn off TAP mode in the order of DR
Replace, Update By the operation of DR, BSC
The value of the AN register 15 is stored in the Update latch 16.
Put in. This allows the first input buffer 201 to pull
Since only the down resistance 211 is connected,
Under this condition, measure the pull-down resistance value by the conventional method.
If determined, the pull-down resistor of the first input buffer 201
It is possible to judge whether the 211 is good or bad.

Similarly, the values of the pull-down resistors 211 of the second and third input buffers can be measured.

The DC test circuit of the LSI of this example is not limited to the case where the external terminal is an input / output (I / O) terminal, but the external terminal is an output terminal and has an output buffer instead of the input / output buffer. It can also be applied in cases. Hereinafter, an example in this case will be described. L for this example shown in FIG.
The SI DC test circuit shows one 3-state (st) data output circuit when the external terminal is an output terminal. The operation of the DC test circuit of the LSI in this example will be described below with reference to the partial circuit diagram shown in FIG.

The 3rd output buffer 203 shown in FIG.
However, when they are bundled on the LSI tester side like the I / O buffer 200 of FIG. 13, all the 3st output buffers 203 are set to the "Z" (Hi-Z) state, and E
Set the value "0" to the BSCAN register 15b on the N side,
NchTr213 for all Update latches 16a
Set a value "0" that turns OFF. That is, "0" is shift-input to the BSCAN register 15a on all the data sides and "0" is input to the BSCAN register 15b on the EN side.
Shift input.

Shift input (Shift) DR) is completed, Shift DR → Exit1 DR → Upda
te The mode of TAP is switched in the order of DR, and Up
date Depending on the operation of DR, BSCAN register 1
The value of 5a is fetched in the Update latch 16a. As a result, all 3st output buffers 203 output values
When set to "Z", NchTr213 becomes OF
Because of F, the pull-down resistor 211 is in a disconnected state.

Next, Update DR → Select
DR scan → Capture DR → Shift
Change the TAP mode in the order of DR to
Shift input "0" to all BSCAN register 15b
However, for the data side BSCAN register 15a,
Shift input "1" only to the 1st 3st data output circuit,
Shift input "0" to other 3st data output circuit.
It Then, the shift input (Shift DR) is completed
Cod, Shift DR → Exit1 DR → Upda
te The TAP mode is switched in the order of DR, and Upd
ate Depending on the operation of DR, the BSCAN register 15a
The value of is fetched in the Update latch 16a.

As a result, all the 3st output buffers 203 have the output value "Z", and the first 3st
Only the pull-down resistor 211 of the output buffer 203 is connected. In this state, if the value of the pull-down resistor is measured by the conventional method, it is possible to determine whether the pull-down resistor 211 of the first 3st output buffer 203 is good or bad.

Similarly, Update DR → Selec
t DR scan → Capture DR → Shif
t The mode of TAP is switched in the order of DR, all "0" s are shift-inputted to the BSCAN register 15b on the EN side, and only "1" is input to the BSCAN register 15a on the data side for the second 3st data output circuit. Shift input, and shift input "0" to the other 3st data output circuit. And shift input (Shift When R) is completed, Shift DR → Exit1 DR → Upd
ate The mode of TAP is switched in the order of DR, and Up
date The value of the BSCAN register 15a is taken into the Update latch 16a by the DR operation.

As a result, all the 3st output buffers 203 have the output value "Z", and the second 3st output buffer 203 has the output value "Z".
Only the pull-down resistor 211 of the output buffer 203 is connected. In this state, if the value of the pull-down resistor is measured by a conventional method, it is possible to determine whether the pull-down resistor 211 of the second 3st output buffer 203 is good or bad.

Similarly, the third 3st output buffer 2
The value of the 03 pull-down resistor 211 can also be measured.

The DC test circuit of the LSI of this example shown in FIG. 17 shows one 2-state (st) data output circuit when the external terminal is an output terminal. The operation of the DC test circuit of the LSI in this example will be described below with reference to the partial circuit diagram shown in FIG.

Each 2nd output buffer 202 shown in FIG.
The pull-down resistors 211 can also be turned on / off individually, but the outputs of the respective 2st output buffers 202 are not the same, so a bus fight will occur, so they cannot be bundled. However, BSCAN register 15 and Upd
It is possible to turn off the pull-down resistor 211 without adversely affecting other measurements by setting the value at which the NchTr 213 is turned off in the ate latch 16, whereby the specific pull-down resistor 2 can be turned off.
It is possible to judge whether the pull-down resistor 211 of each 2st output buffer 202 is good or bad by turning on only 11 of the 2nd output buffers 202.

As described above, according to the DC test circuit of the LSI of this example, in order to turn on / off the pull-down resistor 211, the logical value for controlling the NchTr 213 is obtained as the output of the Update latch of the existing BSCAN circuit. Since it is set to Nch
BS of dedicated BSCAN circuit for controlling Tr213
The CAN register and Update latch are unnecessary.

In the first embodiment, only the case where the pull-up resistor is connected to the input / output terminal, the input terminal or the output terminal will be described. In the second embodiment, the pull-down resistor is also connected. Only the case has been described, but both cases may be mixed. Hereinafter, an example in this case will be described.

FIG. 18 shows an example of a case where pull-up resistors and pull-down resistors are mixedly connected to the input / output terminals in the DC test circuit of the LSI of the present invention. Circuit BSCAN circuit NOR
Gate 17, AND gate 18, and each control signal SFD
R, CLKDR, UPDDR, MODE R, MODE
1 and MODE 2 are omitted.

FIG. 18 shows a state in which the external terminals of the two data input / output circuits are bundled for explaining the operation of this example. The first data input / output circuit and the second data input circuit are shown in FIG. In the output circuit, the pull-up resistor 210 and the PchTr 212 are connected to the output terminal of the I / O buffer 200, and in the third data input / output circuit, the pull-down resistor 211 and the NchTr 212 are connected to the output terminal of the I / O buffer 200.
213 and 213 are connected.

In this case, the PchTr 212 that controls the connection between the pull-up resistor 210 of the I / O buffer 200 and the power supply (VDD), or the NchTr 213 that controls the connection between the pull-down resistor 211 of the I / O buffer 200 and the ground, ON only for the circuit to be measured
In the case of the circuit that is not the measurement target,
By setting the CAN register 15a and the Update latch 15a, the pull-up resistance or pull-down resistance of the circuit other than the measurement target can be separated, and only the pull-up resistance or pull-down resistance of the measurement target circuit can be connected. Therefore, as in the case of the first embodiment or the second embodiment, it is possible to determine whether the arbitrary pull-up resistor 210 or the pull-down resistor 211 is good or bad.

Although the case of having the data input / output circuit has been described with reference to FIG. 18, the pull-up resistor and the pull-down resistor also have the same in the case of having the data input circuit, the 3st data output circuit, or the 2st data output circuit. When mixed and connected, it is possible to disconnect the pull-up resistor or pull-down resistor of the circuit that is not the measurement target and leave only the pull-up resistor or pull-down resistor of the circuit that is the measurement target connected. Whether the pull-up resistor 210 or the pull-down resistor 211 of FIG.

In the first and second embodiments, in order to turn ON / OFF the pull-up resistor 210, Pch
The selector 214 connected to the NchTr 213 in order to turn on / off the other input of the selector 214 connected to the Tr212 or the pull-down resistor 211.
The other input of is connected to the output of the Update latch, but the output of the BSCAN register may be used as this input. An example of this case will be described below.

Third Embodiment FIG. 19 is a diagram showing the configuration of one data input / output circuit in the DC test circuit of the LSI of the third embodiment of the present invention, and FIG. 20 is a diagram of the LSI of this embodiment. FIG. 21 is a diagram showing the configuration of one data input circuit in the DC test circuit.
22 is a diagram showing the configuration of one 3-state data output circuit in the LSI DC test circuit of the present embodiment, FIG.
FIG. 6 is a diagram showing the configuration of one 2-state data output circuit in the LSI DC test circuit of the present embodiment.

FIG. 19 shows a case where the DC test circuit of the LSI of this example has an external terminal composed of an input / output terminal, and a data input / output circuit connected to the external terminal has an input / output (I / O) buffer 200. In comparison with the case of the first embodiment shown in FIG. 5, the other input of the selector 214 connected to the PchTr 212 is the BSC on the data side.
The difference is that it is connected to the output of the AN register 15a.

Hereinafter, with reference to the partial circuit shown in FIG.
The operation of the DC test circuit of the LSI of this example will be described. B
Depending on the operation of SCAN mode setting, DC TEST
Mode, set all I / O buffers 200 to input mode, and turn off PchTr212.
The operation of bringing the pull-up resistor 210 into the separated state by the above-mentioned state is the same as that of the first embodiment.

Next, Update DR → Select
DR scan → Capture DR → Shift
Switching the TAP mode in the order of DR, Shift D
Depending on the operation of R, the BSCAN register 15b on the EN side
Are all "1" and BSCAN register 15 on the data side
For a, only "0" is set to the first data input / output circuit.
Shift input, and other data input / output circuits shift in "1".
Force This allows all I / O buffers 200
Becomes the input mode, and the first I / O buffer 2
Only the 00 pull-up resistor 210 is connected.
In this state, the value of the pull-up resistor is
Is measured, the pull-up of the first I / O buffer 200
It is possible to judge whether the resistor 210 is good or bad.

Next, unlike the first embodiment, the TAP mode is Shift. It remains DR and internal logic circuit 1
Ca that takes the output of 02 into the BSCAN register 15a
pture Since the DR is not performed, the value of each BSCAN register 15a is held as the shifted input value. Therefore, set the input value "1" to TDI,
The value "0" of the data side BSCAN register 15a of the third data input / output circuit is shifted to the data side BSCAN register 15a of the second data input / output circuit. As a result, all the I / O buffers 200 are set to the input mode, and only the pull-up resistor 210 of the second I / O buffer 200 is connected. In this state, the pull-up resistors 210 are connected by the conventional method. If the value of 210 is measured, the pull-up resistor 21 of the second I / O buffer 200
It is possible to make a judgment of good / bad of 0.

Similarly, the third I / O buffer 200
The value of the pull-up resistor 210 can also be measured.

FIG. 20 shows a case where the LSI DC test circuit of this example has an external terminal which is an input terminal, and a data input circuit connected to the external terminal has an input buffer 201, which is shown in FIG. Compared to the case of the first embodiment, the selector 21 connected to the PchTr 212
The difference is that the other input of 4 is connected to the output of the BSCAN register 15.

Hereinafter, with reference to the partial circuit shown in FIG.
The operation of the DC test circuit of the LSI of this example will be described. If the input buffers 201 shown in FIG. 20 are bundled on the LSI tester side like the I / O buffers 200 in the first embodiment shown in FIG. 5, all the input buffers 201
The operation of bringing the pull-up resistor 210 of 1 to the disconnected state is the same as that of the first embodiment.

Next, Update DR → Select
DR scan → Capture DR → Shift
While switching the TAP mode in the order of DR, BS
For the CAN register 15, a first data input circuit
"0" is shift-input only for the input buffer 201 of
Shift "1" to the input buffer 201 of the data input circuit.
Shift input (Shift input (Shift D
R) is completed, the first input buffer 201 is pulled.
This is because only the up resistor 210 is connected.
The value of the pull-up resistance by the conventional method under
By pulling up the first input buffer 201.
Whether the resistor 210 is good or bad can be determined.

Next, unlike the case of the first embodiment, TA
P mode is Shift Remains DR and Capt
ure Since the DR is not performed, the shift-input value is held as it is as the value of each BSCAN register 15. Therefore, the input value "1" is set in TDI, and the value "1" in the BSCAN register 15 of the third data input circuit is set.
0 "is set to the BSCAN register 1 of the second data input circuit
Shift to 5. As a result, only the pull-up resistor 210 of the second input buffer 201 is connected. Therefore, in this state, the value of the pull-up resistor 210 is measured by the conventional method to obtain the second input buffer 201.
It is possible to judge whether the pull-up resistor 210 is good or bad.

Similarly, the value of the pull-up resistor 210 of the third input buffer 201 can be measured.

FIG. 21 shows the DC test circuit of the LSI of this example, in which the external terminals are output terminals, and the 3-state (st) data output circuit connected to the external terminals is 3 st
The case where the output buffer 203 is provided is shown. Compared with the case of the first embodiment shown in FIG. 10, the other input of the selector 214 connected to the PchTr 212 is connected to the output of the BSCAN register 15a on the data side. The point is different.

Hereinafter, with reference to the partial circuit shown in FIG. 21,
The operation of the DC test circuit of the LSI of this example will be described. The 3st output buffer 203 shown in FIG. 21 is an LSI similar to the I / O buffer 200 in the case of the first embodiment shown in FIG.
When bundled on the tester side, all the 3st output buffers 203 are set to "Z" (Hi-Z) and all pull-up resistors 210 are disconnected. The operation is the same as that of the first embodiment. Is.

Next, Update DR → Select
DR scan → Capture DR → Shift
The TAP mode is switched in the order of DR, and the BSC on the EN side is
The AN register 15b is all set to "0", and B on the data side is set.
For the SCAN register 15a, the first 3rd data
Only the data output circuit shifts "0" to the other 3st data
The data output circuit shifts in "1". Shift input
(Shift DR) is completed, TAP mode
Is Shift It remains DR, Update DR
Since it is not done, the value of Update latch 16a
Is unchanged, and all 3st output buffers 203 are output.
The force value becomes "Z", and further the first 3st output buffer 2
Only the pull-up resistor 210 of 03 is connected.
So, in this state, the value of the pull-up resistor is changed by the conventional method.
By measuring, the first 3st output buffer 20
To judge whether the pull-up resistor 210 of No. 3 is good or bad
You can

Next, unlike the case of the first embodiment, TA
P mode is Shift Remains DR and Capt
ure Since the DR is not performed, the value of each BSCAN register 15a holds the shifted input value as it is. Therefore, set the input value "1" to TDI,
The value "0" of the data side BSCAN register 15a of the third 3st data output circuit is shifted to the data side BSCAN register 15a of the second 3st data output circuit.
As a result, all the 3st output buffers 203 have the output value "Z", and the second 3st output buffer 2
Since only the pull-up resistor 210 of No. 03 is connected, the value of the pull-up resistor is measured by the conventional method in this state, and the second 3st output buffer 2
It is possible to judge whether the pull-up resistor 210 of No. 03 is good or bad.

Similarly, the third 3st output buffer 2
The value of the 03 pull-up resistor 210 can also be measured.

FIG. 22 shows a 2-state (st) data output circuit in which the external terminals are output terminals and are connected to the external terminals in the DC test circuit of the LSI of this example.
The case where the output buffer 202 is provided is shown. Compared with the case of the first embodiment shown in FIG. 10, the other input of the selector 214 connected to the PchTr 212 is the BSC.
The difference is that it is connected to the output of the AN register 15.

The operation of the DC test circuit of the LSI of this example will be described below with reference to the partial circuit diagram shown in FIG. The 2nd output buffer 202 shown in FIG. 22 is an LSI similar to the I / O buffer in the case of the first embodiment shown in FIG.
When bundled on the tester side, "1" is shift-input to the BSCAN register 15 of all the 2st data output circuits.

Shift input (Shift) DR) is completed, Shift DR → Exit1 DR → Upd
ate The mode of TAP is switched in the order of DR, and Up
date Depending on the operation of DR, BSCAN register 1
The value of 5 is loaded into the Update latch 16. This will cause all 2st output buffers 202 to output
At H ″, since the PchTr 212 is OFF, the pull-up resistor 210 is in a disconnected state.

Next, Update DR → Select
DR scan → Capture DR → Shift
Switch the TAP mode in the order of DR, and
Only the first 2nd data output circuit for the star 15
"0" is shift-inputted, and "2" is output to the other 2nd data output circuit.
1 "shift input. When the shift input is completed, T
AP mode is Shift Remaining DR, Upd
ate Update latch because DR is not performed
There is no change in the value of 16 and it is "1".
The output value of the output buffer 202 is "1",
Only the pull-up resistor 210 of the 2nd output buffer 202
It will be in the connected state, so in this state, the conventional method
By measuring the value of the pull-up resistor, the first two
Whether the pull-up resistor 210 of the st output buffer 202 is good or not
Defects can be determined.

Next, the TAP mode is Shift. DR
Remains and Capture Since the DR is not performed, the value of each BSCAN register 15 is held as it is after the shift input. Therefore, input value to TDI
Set "1" and BSC of the 3rd 2nd data output circuit
The value of the AN register 15 is shifted to the BSCAN register 15 of the second 2st data output circuit. As a result, all 2nd output buffers 202 output value "H".
Then, only the pull-up resistor 210 of the second 2st output buffer 202 is connected. Therefore, in this state, the value of the pull-up resistor is measured by the conventional method to obtain the second 2st output buffer 202. It is possible to judge whether the pull-up resistor 210 is good or bad.

Similarly, the third 2st output buffer 2
The value of the 02 pull-up resistor 210 can also be measured.

As described above, according to the DC test circuit of the LSI of this example, in order to turn on / off the pull-down resistor 210, the logical value for controlling the PchTr 212 is obtained as the output of the BSCAN register 15 of the existing BSCAN circuit. Therefore, the P
The BSCAN register of the dedicated BSCAN circuit for controlling the chTr212 becomes unnecessary. Also, the LS of this example
In the DC test circuit of I, the LSI external terminals of the 2nd output buffer 202 can be bundled, and in this state, the value of each pull-up resistor 210 can be measured.

In the third embodiment, the pull-up resistor 2
To turn ON / OFF 10, the other input of the selector 214 connected to the PchTr 212 is connected to the output of the BSCAN register on the data side. The output of the BSCAN register on the EN side is used as this input. Alternatively, the inverted outputs of the BSCAN registers may be used so that their outputs are the same as the outputs of the BSCAN registers on the data side. An example of this case will be described below.

Fourth Embodiment FIG. 23 is a diagram showing the configuration of one data input / output circuit in the DC test circuit of the LSI of the fourth embodiment of the present invention, and FIG. 24 is a diagram of the LSI of this embodiment. 25 is a diagram showing the configuration of one data input circuit in the DC test circuit, FIG.
FIG. 26 is a diagram showing the configuration of one 3-state data output circuit in the LSI DC test circuit of the present embodiment.
FIG. 6 is a diagram showing the configuration of one 2-state data output circuit in the LSI DC test circuit of the present embodiment.

FIG. 23 shows the DC test circuit of the LSI of this example, in which the external terminals are composed of input / output terminals, and the data input / output circuit connected to the external terminals is connected to the I / O buffer 200.
In comparison with the case of the third embodiment shown in FIG. 19, the other input of the selector 214 connected to the PchTr 212 is connected to the inverted output of the BSCAN register 15b on the EN side. The difference is that the inverted output of the BSCAN register 15b on the EN side is
BSCAN register 15 on the data side in the case of the third embodiment
If it becomes the same as the output of a, the operation is as shown in FIG.
This is the same as the case of the third embodiment shown in FIG. B on the EN side
The same applies when the output of the BSCAN register 15b on the EN side is used instead of the inverted output of the SCAN register 15b.

FIG. 24 shows a case where the LSI DC test circuit of this example has external terminals formed of input terminals, and the data input circuit connected to the external terminals has an input buffer 201, and is shown in FIG. Compared to the case of the third embodiment, the selector 2 connected to the PchTr 212
The difference is that the other input of 14 is connected to the inverted output of the BSCAN register 15, but the inverted output of the BSCAN register 15 is the BSCA in the case of the third embodiment.
If the output of the N register 15 is made the same, the operation is the same as in the case of the third embodiment shown in FIG. Instead of the inverted output of the BSCAN register 15, BS
The same applies when the output of the CAN register 15 is used.

FIG. 25 shows the DC test circuit of the LSI of this example, in which the external terminals are output terminals and the 3-state (st) data output circuit connected to the external terminals has the 3st output terminal.
The case where the output buffer 203 is provided is shown. Compared with the case of the third embodiment shown in FIG. 21, the other input of the selector 214 connected to the PchTr 212 becomes the inverted output of the BSCAN register 15b on the EN side. The difference is that they are connected, but the BSCAN register 1 on the EN side
The inverted output of 5b is the BS on the data side in the case of the third embodiment.
If it is the same as the output of the CAN register 15a,
The operation is the same as in the case of the third embodiment shown in FIG. The same applies when the output of the EN side BSCAN register 15b is used instead of the inverted output of the EN side BSCAN register 15b.

In FIG. 26, in the DC test circuit of the LSI of this example, the external terminal is composed of an output terminal, and the 2-state (st) data output circuit connected to the external terminal has a 2st data output circuit.
The case where the output buffer 202 is provided is shown. Compared with the case of the third embodiment shown in FIG. 22, the other input of the selector 214 connected to the PchTr 212 is BSC.
The difference is that it is connected to the inverted output of the AN register 15, but if the inverted output of the BSCAN register 15 is the same as the output of the BSCAN register 15 in the case of the third embodiment, the operation is The same as the case of the third embodiment shown in FIG. BSCAN register 15
The same applies when the output of the BSCAN register 15 is used instead of the inverted output of.

In the example shown in FIGS. 23 to 26, the I / O buffer 200 and the input buffer are controlled by the same procedure as in the example of FIGS. 19 to 22 in the case of the third embodiment. 201, 3st output buffer 203, 2st output buffer 202 have the same output state so that the LSI external terminals can be bundled in each case, and only a specific pull-up resistor 210 is connected. Therefore, it is possible to determine whether each pull-up resistor 210 is good or bad by using a conventional method.

In the first embodiment, the pull-up resistor 2
The other input of the selector 214 connected to the PchTr 212 is connected to the output of the Update latch on the data side in order to turn ON / OFF the 10, and is connected to the output of the Update latch as this input. The output of the selector may be used. An example of this case will be described below.

Fifth Embodiment FIG. 27 is a diagram showing the configuration of one data input / output circuit in the DC test circuit of the LSI of the fifth embodiment of the present invention, and FIG. 28 is the LSI of the present embodiment. FIG. 29 is a diagram showing the configuration of one data input circuit in the DC test circuit.
30 is a diagram showing the configuration of one 3-state data output circuit in the LSI DC test circuit of the present embodiment, FIG.
FIG. 6 is a diagram showing the configuration of one 2-state data output circuit in the LSI DC test circuit of the present embodiment.

FIG. 27 shows that in the DC test circuit of the LSI of this example, the external terminals are composed of input / output terminals, and the data input / output circuit connected to the external terminals is connected to the I / O buffer 200.
In comparison with the case of the first embodiment shown in FIG. 5, the other input of the selector 214 connected to the PchTr 212 has the other input of the selector 14a connected to the update latch 16a on the data side. DC is different except that it is connected to the output. In the TEST mode, the output of the selector 14a is the same as the output of the update latch 16a on the data side.
This is similar to the case of the first embodiment shown in FIG.

FIG. 28 shows a case where the DC test circuit of the LSI of this example has an external terminal composed of an input terminal and a data input circuit connected to the external terminal having an input buffer 201, which is shown in FIG. Compared to the case of the first embodiment, the selector 21 connected to the PchTr 212
The difference is that the other input of 4 is connected to the output of the selector 14d to which the Update latch 16 is connected. In the TEST mode, the selector 14d
Output becomes the same as the output of the Update latch 16, and the operation thereof is similar to that of the first embodiment shown in FIG.

FIG. 29 shows a DC test circuit of the LSI of this example, in which the external terminal is an output terminal and the 3-state (st) data output circuit connected to the external terminal has a 3st output terminal.
The case where the output buffer 203 is provided is shown. Compared with the case of the first embodiment shown in FIG. 10, the other input of the selector 214 connected to the PchTr 212 is connected to the update latch 16a on the data side. Selector 1
4a except that it is connected to the output of 4a
In the TEST mode, the output of the selector 14a is the same as the output of the Update latch 16a on the data side, and therefore the operation is the same as in the case of the first embodiment shown in FIG.

FIG. 30 shows a 2-state (st) data output circuit connected to the external terminal in the DC test circuit of the LSI of this example.
The case where the output buffer 202 is provided is shown. Compared with the case of the first embodiment shown in FIG. 12, the other input of the selector 214 connected to the PchTr 212 is Upd.
The difference is that it is connected to the output of the selector 14a to which the ate latch 16 is connected. In the TEST mode, the output of the selector 14a is the same as the output of the Update latch 16, so the operation is the same as that of the first embodiment shown in FIG.

In the example shown in FIGS. 27 to 30, each I is obtained by performing control in the same procedure as in the example of FIGS. 5, 8, 10 and 12 in the case of the first embodiment. / O buffer 200, input buffer 201, 3st output buffer 2
The output state of the 03, 2st output buffer 202 can be controlled in the same manner as in the first embodiment, and only a specific pull-up resistor 210 can be connected, so that the conventional method is used. It is possible to judge whether each pull-up resistor 210 is good or bad.

Although the embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and there are changes in design within the scope not departing from the gist of the present invention. However, it is included in this invention. For example, the circuit that turns ON / OFF the pull-up resistor 210 is not limited to the PchTr, but may be an NchTr, a transfer gate, or the like. Also, DC TEST control signal MODE R
In addition to being generated by the TAP circuit 10, it may be supplied from an LSI external terminal or may be supplied from another test control circuit. In each of the embodiments, for convenience of description, the I / O buffer 200, the input buffer 201, the 3st output buffer 203, and the 2st output buffer 202 are described as having a three-circuit configuration, but the present invention is not limited to this. Alternatively, the number of circuits may be two circuits, five circuits, or the like.

[0143]

As described above, the LSI of the present invention
According to the DC test circuit of, L having a plurality of external terminals
In SI, the value of each pull-up resistor or pull-down resistor connected to each external terminal is measured in a state where each external terminal is bundled and connected to one of the signal terminals of the LSI tester, and the good / defective A decision can be made. Even if it is not possible to bundle the external terminals because a bus fight occurs, set the required value in the BSCAN circuit to turn off the pull-up resistor or pull-down resistor outside the measurement target, and It is possible to measure the value of a certain pull-up resistance or pull-down resistance and determine whether the resistance is good or bad. Therefore, according to the present invention,
A BSCAN circuit for controlling a transistor or the like that turns ON / OFF the pull-up resistor or pull-down resistor, which has been conventionally required to measure the value of the pull-up resistor or pull-down resistor, is no longer necessary.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a DC test circuit for an LSI according to a first embodiment of the present invention, in which an external terminal is an input / output terminal.

FIG. 2 is a diagram showing a DC test circuit of the LSI according to the embodiment,
It is a circuit diagram which shows the structure of TAP.

FIG. 3 is a diagram showing a DC test circuit of an LSI according to the same embodiment;
It is a circuit diagram which shows the structure of an instruction decoder.

FIG. 4 is a diagram showing a state diagram of a TAP circuit.

FIG. 5 is a DC test circuit of the LSI of the same embodiment,
It is a circuit diagram which shows the state which bundled the external terminal of the data input / output circuit of 3 circuits.

FIG. 6 is a flowchart illustrating an operation of the DC test circuit of the LSI according to the embodiment.

FIG. 7 is a diagram showing a DC test circuit of the LSI of the same embodiment,
It is a circuit diagram which shows the structure when an external terminal is an input terminal.

FIG. 8 is a diagram showing a DC test circuit of an LSI according to the same embodiment;
It is a figure which shows the structure of the data input circuit of 1 circuit.

FIG. 9 is a diagram showing a DC test circuit of an LSI according to the same embodiment,
It is a circuit diagram which shows the structure when an external terminal is a 3-state output buffer.

FIG. 10 is a diagram showing a configuration of one 3-state data output circuit in the DC test circuit of the LSI of the embodiment.

FIG. 11 is a circuit diagram showing a configuration in the case where the external terminal is a 2-state output buffer in the DC test circuit of the LSI of the embodiment.

FIG. 12 is a diagram showing a configuration of one 2-state data output circuit in the DC test circuit of the LSI of the embodiment.

FIG. 13 is a circuit diagram of a DC test circuit for an LSI according to a second embodiment of the present invention, showing a state in which external terminals of two data input / output circuits are bundled.

FIG. 14 is a diagram showing the configuration of one data input / output circuit in the DC test circuit for the LSI of the embodiment.

FIG. 15 is a diagram showing the configuration of one data input circuit in the DC test circuit of the LSI of the embodiment.

FIG. 16 is a diagram showing the configuration of one 3-state data output circuit in the DC test circuit for the LSI of the embodiment.

FIG. 17 is a diagram showing the configuration of one 2-state data output circuit in the DC test circuit for the LSI of the embodiment.

FIG. 18 is a circuit diagram of the DC test circuit of the LSI of the embodiment, showing a state in which the external terminals of the data input / output circuit with pull-up resistor and the data input / output circuit with pull-down resistor are bound together.

FIG. 19 is a diagram showing the configuration of one data input / output circuit in a DC test circuit for an LSI according to a third embodiment of the present invention.

FIG. 20 is a diagram showing the configuration of one data input circuit in the DC test circuit of the LSI of the embodiment.

FIG. 21 is a diagram showing a configuration of one 3-state data output circuit in the DC test circuit of the LSI of the embodiment.

FIG. 22 is a diagram showing the configuration of one two-state data output circuit in the DC test circuit for the LSI of the embodiment.

FIG. 23 is a diagram showing the configuration of one data input / output circuit in the DC test circuit for an LSI according to the fourth embodiment of the present invention.

FIG. 24 is a diagram showing a configuration of one data input circuit in the DC test circuit of the LSI of the embodiment.

FIG. 25 is a diagram showing the configuration of one 3-state data output circuit in the DC test circuit for the LSI of the embodiment.

FIG. 26 is a diagram showing the configuration of one 2-state data output circuit in the DC test circuit for the LSI of the embodiment.

FIG. 27 is a diagram showing the configuration of one data input / output circuit in the DC test circuit for the LSI of the fifth embodiment of the present invention.

FIG. 28 is a diagram showing the configuration of one data input circuit in the DC test circuit for the LSI of the embodiment.

FIG. 29 is a diagram showing the configuration of one 3-state data output circuit in the DC test circuit for the LSI of the embodiment.

FIG. 30 is a diagram showing the configuration of one 2-state data output circuit in the DC test circuit for the LSI of the embodiment.

FIG. 31 is a diagram showing a circuit configuration in the case where a plurality of LSI external terminals are bundled and a test is performed in the first conventional example.

FIG. 32 is a diagram showing a circuit state when a test is performed by bundling a plurality of LSI external terminals when a pull-up resistor is provided in the external terminals in the first conventional example.

FIG. 33 is a diagram showing a circuit configuration in the case where a plurality of LSI external terminals are bundled and a test is performed in the second conventional example.

[Explanation of symbols]

10 TAP circuits 14a, 14b, 14c, 14d Selectors 15, 15a, 15b BSCAN registers 16, 16a, 16b Update latch 17 NOR gate 18 AND gate 101 LSI substrate 102 Internal logic circuits 111a, 111b, 111c Data input / output circuits 112a, 112b , 112c Data input circuits 113a, 113b, 113c 2st data output circuits 114a, 114b, 114c 3st data output circuit 200 I / O buffer (buffer) 201 Input buffer (buffer) 202 2st output buffer (buffer) 203 3st output buffer (buffer) ) 210 pull-up resistor 211 pull-down resistor 212 PchTr (control element) 213 NchTr (control element) 214 selector

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 2G132 AA17 AC15 AD01 AK07 AK10                       AK13 AL00                 4M106 AC01 AC07 CA01 CA10                 5F038 DF16 DT05 DT06 DT10 EZ20

Claims (18)

[Claims] 1. A semiconductor device having a plurality of buffers connected between an internal logic circuit and an external terminal through a boundary scan circuit, wherein a pull-up (or pull-down) resistance value connected to each external terminal is provided. In order to measure, the state of the boundary scan circuit is switched in a predetermined order to set the logical value of each buffer to a value that does not affect the measurement of the pull-up (or pull-down) resistance. A control element for connecting or disconnecting an up (or pull-down) resistance to a power supply (or ground) is configured to be on / off controllable by using a set value in the boundary scan circuit. DC test circuit for semiconductor devices. 2. The buffer is an input / output buffer or a 3-state output buffer, and the set value in the boundary scan circuit is a logical value of an update latch on the data side in the boundary scan circuit. A DC test circuit for a semiconductor device according to claim 1. 3. The buffer is an input buffer or a 2-state output buffer, and the set value in the boundary scan circuit is a logical value of an update latch in the boundary scan circuit. DC test circuit of semiconductor device. 4. The buffer is an input / output buffer or a three-state output buffer, and a set value in the boundary scan circuit is a logical value of a boundary scan register on the data side in the boundary scan circuit. The DC test circuit for a semiconductor device according to claim 1. 5. The buffer is an input buffer or a 2-state output buffer, and a set value in the boundary scan circuit is a logical value of a boundary scan register in the boundary scan circuit. A DC test circuit for the semiconductor device described. 6. The buffer is an input / output buffer or a 3-state output buffer, and a set value in the boundary scan circuit is an inverted output value of a logical value of a boundary scan register on the enable side in the boundary scan circuit. The DC test circuit for a semiconductor device according to claim 1, wherein: 7. The buffer is an input buffer or a two-state output buffer, and a set value in the boundary scan circuit is an inverted output value of a logical value of a boundary scan register in the boundary scan circuit. The DC test circuit for a semiconductor device according to claim 1. 8. The buffer is an input / output buffer or a 3-state output buffer, and a set value in the boundary scan circuit is an output value of a selector that selects an output of a data side update latch in the boundary scan circuit. The DC test circuit for a semiconductor device according to claim 1, wherein the DC test circuit is provided. 9. The buffer is an input buffer or a two-state output buffer, and a set value in the boundary scan circuit is an output value of a selector that selects an output of an update latch in the boundary scan circuit. The semiconductor device according to claim 1, wherein D
C test circuit. 10. A semiconductor device having a plurality of buffers connected between an internal logic circuit and an external terminal via a boundary scan circuit, the value of a pull-up (or pull-down) resistance connected to each external terminal. When measuring, the state of the boundary scan circuit is switched in a predetermined order to set the logical value of each buffer to a value that does not affect the measurement of the pull-up (or pull-down) resistance. A DC test of a semiconductor device, characterized in that a control element for connecting or disconnecting an up (or pull-down) resistance to a power supply (or ground) is on / off controlled by using a set value in the boundary scan circuit. Method. 11. The buffer is an input / output buffer or 3
11. The DC test method for a semiconductor device according to claim 10, wherein a logical value of a data side update latch in the boundary scan circuit is used as a set value in the boundary scan circuit in the case of a state output buffer. 12. The logic value of an update latch in the boundary scan circuit is used as a set value in the boundary scan circuit when the buffer is an input buffer or a two-state output buffer. A method for DC testing a semiconductor device as described. 13. The buffer is an input / output buffer or 3
11. The DC test method for a semiconductor device according to claim 10, wherein in the case of a state output buffer, a logical value of a boundary scan register on a data side in the boundary scan circuit is used as a set value in the boundary scan circuit. . 14. The logical value of a boundary scan register in the boundary scan circuit is used as a set value in the boundary scan circuit when the buffer is an input buffer or a two-state output buffer. 10 DC of the semiconductor device
Test method. 15. The buffer is an input / output buffer or 3
11. The semiconductor device according to claim 10, wherein in the case of a state output buffer, an inverted output value of a logical value of a boundary scan register on the enable side in the boundary scan circuit is used as a set value in the boundary scan circuit. DC test method. 16. When the buffer is an input buffer or a two-state output buffer, an inverted output value of the logical value of the boundary scan register in the boundary scan circuit is used as a set value in the boundary scan circuit. The DC test method for a semiconductor device according to claim 10. 17. The buffer is an input / output buffer or 3
11. The semiconductor according to claim 10, wherein in the case of a state output buffer, the output value of a selector that selects the output of the update latch on the data side in the boundary scan circuit is used as the set value in the boundary scan circuit. DC test method for equipment. 18. When the buffer is an input buffer or a two-state output buffer, the output value of a selector that selects the output of the update latch in the boundary scan circuit is used as a set value in the boundary scan circuit. 11. The DC test method for a semiconductor device according to claim 10.