JPH085709A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the working efficiency of DC (direct current) characteristic tests. CONSTITUTION:For daisy-chain connected AND logical gates TGI-TGm, such input signal patterns that the logical states of test outputs in the final stage are alternately toggled and the logical state of each input signal is also appropriately toggled are inputted to input terminals PI1-PIm of the gates. When an outputted test select signal TS is set to an 'H' state, test outputs can be outputted front output terminals PO1-POn. Therefore, the working time of DC characteristic tests can be shortened, because DC characteristic tests about the input can be performed in parallel with those about the output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which a predetermined logic circuit is built as an internal circuit, and more particularly to a DC (direct current) of the semiconductor integrated circuit itself.
The present invention relates to a semiconductor integrated circuit capable of improving work efficiency of a characteristic test.

[0002]

2. Description of the Related Art As a basic test of a semiconductor integrated circuit, there is a DC characteristic test. This DC characteristic test is to measure a steady voltage or a steady current of an input terminal, an output terminal or a power supply terminal of a semiconductor integrated circuit to be tested.

For example, various voltage signals from a high level input voltage VIH corresponding to the power supply voltage to a low level input voltage VIL corresponding to the ground potential are input to the input terminal. At this time, it is tested whether the operation of the input buffer connected to the input terminal is normal. For example, it is tested whether the threshold voltage VTH or VTL of the input buffer is proper.

Further, in the DC characteristic test on the input terminal, the input signal current at the time of inputting the signal of the high level input voltage VIH, that is, the high level input current IIH is measured. When the low level input voltage VIL is input, the current of the input signal, that is, the low level input current IIL is measured. By measuring the high level input current IIH and the low level input current IIL, the input impedance of the input terminal is tested for suitability.

At the output terminal of the semiconductor integrated circuit, the voltage of the signal at the output terminal is measured as a DC characteristic test. For example, the output voltage of the signal when the H state is output from the output terminal, that is, the high level output voltage VOH is measured. Further, the output voltage of the signal when the L state is output from the output terminal, that is, the low level output voltage VOL is measured. Regarding the output terminal to be tested, the high level output voltage VO
If H is below the regulation, the correct H state cannot be output. On the other hand, if the low level output voltage VOL at the output terminal is above the specified level, the L state cannot be output correctly.

Regarding the power supply of the semiconductor integrated circuit, the power supply current is measured when the input signal and the output signal are in a steady state. MOS (metal oxide semiconductor)
) Type semiconductor integrated circuit, the normal power supply current in a steady state is zero or a very small current. here,
Even in such a steady state, when a large power supply current flows, some kind of defect is detected inside the semiconductor integrated circuit.

FIG. 5 is a circuit diagram showing a connection in a DC characteristic test of a semiconductor integrated circuit which has been conventionally performed.

In FIG. 5, an input I of the semiconductor integrated circuit 1 is input.
An example of connection when performing a DC characteristic test on the output, output O, etc. is shown. In FIG. 5, the input control device 12, the input driver 14, and the input test power supply 16 are shown.
, Comparators 22a and 22b, and path determination device 2
4 and an output test power supply 26 are used.

First, the input I of the semiconductor integrated circuit 1
The DC characteristic test regarding the input control device 12, the input driver 14, and the input test power supply 16 is performed.

The input control device 12 outputs, as a signal S11, the logical states sequentially input to the input I of the semiconductor integrated circuit 1. Further, the input control device 12 sets the high-level input voltage VIH and the low-level input voltage VIL of the input test power supply 16 in which the high-level input voltage VIH and the low-level input VIL which are output as described later are variable. I do.

The input test power supply 16 generates the high level input voltage VIH and the low level input voltage VIL. The high level input voltage VIH corresponds to the H-state voltage input to the input I of the semiconductor integrated circuit 1. The low level input voltage VIL corresponds to the voltage in the L state of the signal input to the input I of the semiconductor integrated circuit 1. The high level input voltage VIL and the low level input voltage VIL of the input test power supply 16 supply the power to the input driver 14. The high level input voltage VIH and the low level input voltage VIL of the input test power supply 16 are variable in accordance with the signal input from the input control device 12. By changing the high-level input voltage VIH and the low-level input voltage input voltage VIL, the H-state voltage and the L-state voltage output from the input driver 14 to the semiconductor integrated circuit 1 are set.

The input driver 14 outputs the same logic state as the signal S11 output by the input control device 12 as a signal S12. In particular, the input driver 14 can change the voltage of the signal S12 in the H state or the L state by changing the voltage of the power source supplied from the input test power source 16.

On the other hand, referring to FIG. 5, for the DC characteristic test of the output terminal of the semiconductor integrated circuit 1, the comparators 22a and 22b and the path determination device 24 are used.
And an output test power supply 26 are used.

First, the comparators 22a and 22b
Are the same as each other and have an input +, an input −, and an output U. These comparators 22a and 22b
When the voltage input to its input + is equal to or higher than the voltage input to its input −, its output U is in the H state.
On the other hand, for the comparators 22a and 22b, when the voltage input to the input + is less than the voltage input to the input-, the output U is in the L state.

The low level output voltage VOL is input to the input + of the comparator 22a. The signal S13 output from the semiconductor integrated circuit 1 is input to the input- of the comparator 22a. Therefore, the comparator 22a outputs the H state from the output U when the signal S13 is equal to or lower than the low level output voltage VOL. On the other hand, when the signal S13 is higher than the low level output voltage VOL, the L state is output. Therefore, when the signal S13 is in the L state, the voltage in the L state has correctly reached below the specified limit by the signal S14 output from the comparator 22a, that is, the voltage in the L state is the low level output voltage. VOL
It is possible to determine whether or not the condition of less than is satisfied.

Regarding the comparator 22b,
The signal S13 is input to its input +, and the high level output voltage VOH is input to its input −. Therefore, the comparator 22b outputs the signal S13.
Is higher than the high level output voltage VOH,
The output U outputs the H state. On the other hand, the signal S1
When the voltage of 3 is smaller than the high level output VOH, the output U outputs the L state. Therefore, according to the comparator 22b, by the signal S15 output from the output U, the semiconductor integrated circuit 1
When the signal S13 output from the H state is in the H state, it is determined whether the H state voltage is equal to or higher than the specified limit, that is, the H state voltage is equal to or higher than the high level output voltage VOH. .

Further, the path judging device 24, based on the signal S14 outputted by the comparator 22a and the signal S15 outputted by the comparator 22b,
Further, by comparing with the logic state of the signal S13 output from the semiconductor integrated circuit 1, it is possible to determine whether the signal S13 satisfies the specified non-defective condition. That is,
When the signal S13 is in the L state and the signal S14 is in the H state, the path determination device 24 determines that there is no problem with respect to the signal S13 being in the L state. On the other hand, the path determination device 24 determines that the signal S13 is H level.
In the case of the state, if the signal S15 is in the H state, it is determined that there is no problem in the H state of the signal S13.

The output test power supply 26 generates the low level output voltage VOL and the high level output voltage VOH. First, the low level output voltage VOL is an upper limit voltage for correctly transmitting the L state when the semiconductor integrated circuit 1 to be tested outputs the L state. That is, when the semiconductor integrated circuit 1 outputs the L state, the voltage of the signal needs to be lower than the low level output voltage VOL. On the other hand, the high level output voltage VOH
Is a lower limit voltage for correctly transmitting the H state when the semiconductor integrated circuit 1 to be tested outputs the H state. That is, when the semiconductor integrated circuit 1 outputs the H state, its voltage needs to be higher than the high level output voltage VOH.

Thus, as shown in FIG. 5, it is possible to perform a DC characteristic test on the input terminal and the output terminal. That is, it is possible to determine whether the semiconductor integrated circuit 1 to be tested can correctly input the signal of the L state or the H state input to the input terminal. The signal output from the semiconductor integrated circuit 1 to be tested is
It can be determined whether or not the L state or the H state is correctly output and transmitted.

Various techniques have been disclosed in order to improve the work efficiency when performing the DC characteristic test as shown in FIG.

FIG. 6 is a logic circuit diagram in which the work efficiency of the DC characteristic test of the semiconductor integrated circuit itself is improved. In FIG. 6, the input terminals PI1 to PIm
Is input and the signals are output from the output terminals PO1 to POn. The semiconductor integrated circuit has the internal circuit 3 built therein. The internal circuit 3 is provided with a predetermined logic circuit for functioning the semiconductor integrated circuit.

In such a semiconductor integrated circuit, consideration is given to a DC specific test for the input terminals PI1 to PIm.

That is, NAND logic gates TG1 to TGm are connected to the respective input terminals PI1 to PIm as input test circuits. The NAND logic gates TG1 to TGn used as these input test circuits are provided for each of the input buffers BI1 to BIm provided corresponding to the input terminals PI1 to PIm. Regarding these input test circuits, if the output of one input test circuit is the test output Ti, the test output T (i-1) of the input test circuit of the previous stage and the input test circuit of this stage The AND operation is performed with the output of the input buffer.

Further, such input buffers BI1 to BI1
N for each input test circuit provided for each Im
The AND logic gates TG1 to TGm are daisy chain connected to each other. Further, the NAND logic gate T at the final stage, which is daisy chain connected in this way,
The test output Tm output by Gm is the output buffer B
It is output to the outside of the semiconductor integrated circuit through the output terminal 3 and the output terminal PK3.

FIG. 7 is a diagram showing the operation of the input test circuit.

In FIG. 7, when "m" shown in FIG. 6 is 5, the signal at the input terminal PI1 (indicated by A in FIG. 7) and the input terminal PI2.
Signal (shown by B), the signal of the input terminal PI3 (shown by C), the signal of the input terminal PI4 (shown by D), and the signal of the input terminal PI5 (shown by E). At the same time, an output signal TO which is output as the test output T7 and is output from the output buffer B3 is shown.

Further, as shown in FIG. 7, the input signal patterns shown in A to E from step 1 to step 11 are input to the input terminals PI1 to PI5, respectively.
The test patterns are sequentially input. or,
If the same logic state of the output signal TO shown in FIG. 7 is output from the output terminal PT3 with respect to the signal pattern input in each step, there is a particular problem in that step. There is no such thing. By sequentially inputting the input pattern of each step in this manner, it is possible to detect a defect in the input buffers BI1 to BI5.

In particular, while sequentially inputting the input signal patterns of steps 1 to 11 shown in FIG. 7,
The voltage supplied to the input driver 14 shown in FIG. 5 can be measured while being changed by the input test power supply 16. That is, it is tested whether the logic state can be correctly determined when the input signal is input with the allowable voltage.

[0029]

However, the one shown in FIG. 6 relates to the DC characteristic test, particularly to the input. As described above, the DC characteristic test is performed independently for the input terminals and the output terminals while using specific input signal patterns.

Therefore, the DC characteristic test for the input terminal using a large number of input signal patterns, and the DC characteristic test for the output terminal which tends to use a larger number of input signal patterns.
Since the characteristic test is performed independently of each other in this way, the whole working time becomes long. In particular, the DC characteristic test on the output terminal requires more test patterns and test time than the DC characteristic test on the input terminal, which requires a long working time.

In the DC characteristic test for such an output terminal, it is necessary to toggle the target output terminal from the L state to the H state or from the H state to the L state. Such a toggle is performed while sequentially inputting a specific input signal pattern to the input terminal of the semiconductor integrated circuit 1 to be tested.

Normally, when the output terminal to be tested becomes the desired logic state, the signal input to the semiconductor integrated circuit 1 to be tested is fixed, and the comparators 22a, 22b and Path determination device 2
4 was used for the determination. The DC characteristic test on each output terminal is sequentially performed on all the output terminals of the target semiconductor integrated circuit 1.

Therefore, if the number of input terminals of the semiconductor integrated circuit 1 increases, the length of one input signal pattern also increases. Moreover, as the number of output terminals increases, the number of test objects increases and the working time increases.

The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to provide a semiconductor integrated circuit capable of improving the work efficiency of the DC characteristic test of the semiconductor integrated circuit itself. .

[0035]

According to the present invention, in a semiconductor integrated circuit in which a predetermined logic circuit is built as an internal circuit, the internal circuit from the outside of the semiconductor integrated circuit which is a test target of a DC characteristic test. A total of m input buffers used for inputting a signal to the input buffer, the test output T (i −1) of another input test circuit provided for each of the input buffers, which is the previous stage, and A total of m inputs that are daisy-chain connected to each other, which performs a specific logical operation with the output of the input buffer corresponding to the input test circuit and outputs the operation result as the test output Ti of the input test circuit of the present stage. A total of n used for outputting a signal from the internal circuit to the outside of the semiconductor integrated circuit, which is a test target of the test circuit and the DC characteristic test
Output buffers, and the output of the corresponding output buffer provided for each output buffer is changed according to the signal from the internal circuit, or according to the test output Tm output from the input test circuit at the final stage. The above object is achieved by including a total of n output test circuits that are changed or selected according to a predetermined output test selection signal.

[0036]

As described above, the DC characteristic test of the semiconductor integrated circuit has hitherto been performed independently for the input terminal and the output terminal. First, the DC characteristic test on the input terminal requires a plurality of input signal patterns and requires a test time. Further, the DC characteristic test on the output terminal requires a larger number of input signal patterns.

Therefore, in the present invention, the DC characteristic test for such an input terminal and the DC characteristic test for such an output terminal are simultaneously performed, so that the working time required for the entire DC characteristic test is reduced. The work is shortened to improve work efficiency.

Further, the DC characteristic test for the output terminal requires a larger number of input signal patterns than the DC characteristic test for the input terminal. Therefore, the present invention aims to improve this point. ing.

That is, the "test state" or "normal state" is selected by using the output test selection signal. If a test state is selected, the present invention
The logic state of the output terminal of the semiconductor integrated circuit can be easily changed and set from outside the semiconductor integrated circuit. Therefore, to set the logic state of the output terminal,
It is not necessary to input many input signal patterns, and work efficiency can be improved.

[0040]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a logic circuit diagram of a first embodiment of a semiconductor integrated circuit to which the present invention is applied.

In FIG. 1, a predetermined logic circuit is built in the internal circuit 3 in the semiconductor integrated circuit. The internal circuit 3 inputs signals from outside the semiconductor integrated circuit by means of the input terminals PI1 to PIm and the input buffers BI1 to BIm. Further, the internal circuit 3 is provided with output buffers BO1 to BOn and output terminals PO1 to POn,
The signal is output to the outside of the semiconductor integrated circuit.

The semiconductor integrated circuit of the first embodiment has N
AND logic gates TG1 to TGm and multiplexer T
AND with M1 to TMn and input buffers B1 and B2
The logic gates G1 and G2 are provided.

First, the NAND logic gate TG1 is
The input test circuit is the same as the one having the same reference numeral shown in FIG. Also, the NAND logic gate T at the final stage
The test output Tm output by Gm is input to the input 1 of all of the multiplexers TM1 to TMn described later.

As shown in FIG. 1, the NAND logic gates TG1 to TGm, which are daisy chain connected, operate as described above with reference to FIG. Therefore, when the input signal pattern as shown in FIG. 7 is input, the test output signal Pm
(Corresponding to the output signal TO in FIG. 7) toggles between the H state and the L state each time the step advances.

The multiplexers TM1 to TMn correspond to the output test circuit of the present invention. The multiplexers PM1 to PMn are provided for each of the n output buffers BO1 to BOn. Further, the multiplexers TM1 to TMn are connected to the corresponding output buffer B.
The outputs of O1 to BOn are changed according to the signal from the internal circuit 3, or the NAND logic gate T at the final stage is changed.
The test output Tm output from Gm (input test circuit)
According to the output test selection signal TS.

Specifically, the multiplexers TM1 to T
Mn is either the signal from the internal circuit 3 input to its input 0 or the test output Tm input to its input 1 according to the output test selection signal TS input to its selection input S. One is selected and the selected one is output to the output U. That is, when the output test selection signal TS is in the L state, the multiplexers TM1 to TMn output the output buffers BO1 to BOn corresponding to the logic state from the internal circuit 3.
Output to. On the other hand, the multiplexers TM1 to TMn
Means that when the output test signal TS is in the H state, the output buffers BO1 to BOn corresponding to the test output Tm are
Is output to.

In FIG. 1, the output buffer B
For O (n-1) and BOn, tri-state output is performed. Control of such tri-state output is performed by the AND logic gate G1 or G2.

In the AND logic gates G1 and G2, when the output test enable signal TE input through the input buffer B2 is in the H state, both of the output buffers BO (n -1) and BOn are in the selected state. (Enable state), the logic states of the signals of the outputs O1 to On input respectively are output as they are.

The output buffers BO (n -1) and BOn operate according to the enable signal TE1 or TE2 from the corresponding internal circuit 3 when the output test enable signal TE is in the L state. Is. That is, when the output test enable signal TE is in the L state, the output buffer BO (n-1) outputs the respective logic states according to the enable signal TE1, and the output buffer BOn outputs the respective logic states, or respectively. The output is controlled to a high impedance state.

In the first embodiment, the output test selection signal TS is set to the L state and the output test enable signal TE is set to the L state during the normal operation. Thereby, the multiplexers TM1 to TM
In each case, n is the input 0 and the output U
Connect to. As a result, the output O1 of the internal circuit 3 is
To On are connected to the output terminals TO1 to TOn, respectively. Therefore, the internal circuit 3 operates regardless of the input test circuit described above and the connection test circuit described above.

On the other hand, in the first embodiment, when the DC characteristic test for the input terminal is performed and the DC characteristic test for the output terminal is performed, the output test selection signal TS is used.
Is set to the H state, and the output test enable signal TE is set to the H level.
State. After that, the input signal patterns as shown in FIG. 7 are sequentially input to the input terminals PI1 to PIm.

That is, in such an input signal pattern, first, all the input terminals PI1 to PIm are set to the H state. After that, the L state is set for each pin from the input terminal PI1 to the input terminal PIm at each step. After (m + 1) steps, all the input terminals P
After I1 to PIm are in the L state, this time, the input terminal PIm side is switched to the input terminal PI1 side, and the H state is sequentially switched at each step.

By doing so, the logic state of the test output Tm alternately toggles between the H state and the L state for each step. The test output Tm is output from the output terminals PO1 to POn via the multiplexers TM1 to TMn and the output buffers BO1 to BOn, respectively.

Therefore, by observing the output of any one of the output terminals PO1 to PIn while sequentially inputting such an input signal pattern, it is possible to first perform the DC characteristic test of the input terminal as described above. it can. Further, by simultaneously observing the toggle of the signals of the output terminals PO1 to POn, it is possible to simultaneously perform the DC characteristic test of each output terminal.

Here, when considering the DC characteristic test of the input terminals, in the case of the number of m input terminals, approximately (m × 2 +
1) The pattern of the input signal of the step is required. On the other hand, when considering the DC characteristic test on the output terminals, the n output terminals PO1 to POn are 3 pins by pin.
When performing a DC characteristic test in steps, (n × 3)
Input signal pattern is required.

Here, in the present embodiment, the DC characteristic test for the input terminal and the DC characteristic test for the output terminal can be executed in parallel. Therefore, in order to complete both the DC characteristic test on the input terminal and the DC characteristic test on the output terminal, the larger number of steps (n × 2 + 1) or (n × 3),
It is only necessary to input the test pattern of the input signal, and the test time can be shortened.

It should be noted that this first test circuit is used as the input test circuit.
The NAND logic gates TG1 to TGm of the embodiment are not limited to such NAND logic gates. That is, each may be an AND logic gate, an OR logic gate, a NOR logic gate, or an exclusive OR logic gate.

In addition, if the logic is determined in advance, most of them can be used. Depending on the case, it is possible to mix the ones that operate different logics.

For example, the NAND logic gates TG1 to TG1
TGm are all AND logic gates, and the input terminal P
When the number of I1 to PIm is 7 (n = 7), FIG.
The test pattern of the input signal as shown in FIG. It is to be noted that an AND logic gate is used to input the input signal pattern as shown in FIG.
This is called the second embodiment.

In the first or second embodiment, the output buffers BO (n-1) and B (n-1) and B (n-1)
It is also possible that all the On's are normal output buffers (not tri-state outputs) and all output buffers are normal ones (not tri-state outputs) with respect to the output terminals subject to the DC characteristic test. .
In this case, the output test enable signal TE is unnecessary. Therefore, the input terminal PT1, the input buffers B2, A
The ND logic gate G1 and FIG. 2 can be omitted.

FIG. 3 is a logic circuit diagram of a third embodiment of a semiconductor integrated circuit to which the present invention is applied.

As shown in FIG. 3, in the third embodiment, the number of input terminals in the first embodiment is four (m = 4), and the number of output terminals is five (n = 5). It is what In addition to this, a bidirectional input / output terminal PIO is used, and a bidirectional buffer composed of an input buffer BI and an output buffer BO of tristate output is used.

Therefore, the third embodiment is particularly provided with the NAND logic gate TG and the D-type latch G5 used as the input test circuit. Further, a multiplexer TM is provided as an output test circuit. An AND logic gate G3 and an exclusive OR for controlling enable of the output buffer BO of the bidirectional input / output buffer.
A logic gate G4 is provided.

Even in the third embodiment, in the normal state, D
When the C characteristic test is not performed, the output test selection signal TS is set to the L state and the output test enable signal TE is set to the L state. As a result, for example, the input / output terminal PIO can also operate normally. That is, the multiplexer TM selects the output O6 of the internal circuit 3. Further, the enable control of the output buffer BO of the tri-state output is performed by the enable signal TE.
3 can be done. The enable signal TE3
Is in the L state, the output buffer BO is in the enable state, and when the enable signal TE3 is in the H state, it is in the disable state.

On the other hand, in the test state in which the DC characteristic test is performed, the output test selection signal TS is set to the H state. Also, the D of the input / output terminal PIO, particularly the input
When performing the C characteristic test, the output test enable signal TE is set to the L state. On the other hand, the input / output terminal PIO
In particular, when performing a DC characteristic test on the output, the output test enable signal TE is set to the H state.

FIG. 4 is a time chart showing the operation of the third embodiment.

In this time chart, the input signal I input from each of the input terminals PI1 to PI4 is input.
N1 to IN4 and an input signal IN5 input from the bidirectional input / output terminal PIO are shown. Also, the output test signal TS and the output test enable signal T
E is shown. Further, the D-type latch G used as an input test circuit corresponding to the input / output terminal PIO.
5 input D and output Q, and the NAND logic gate TG
The test output T5 that is output by is shown. Also, a signal OE output from the exclusive OR logic gate G4, which is used for enable control of the output buffer BO.
N is indicated.

In the time chart of FIG. 4, time
Before t ₁₁ , the output test selection signal TS is set to the H state in order to perform the DC characteristic test. Further, all the input signals IN1 to IN5 are set to the H state.

Thereafter, at time t ₁₁ , the input signal IN
1 goes into the L state, and the test output T5
Becomes the H state. At time t ₁₂ , the input signal IN2 is in the L state, and the test output T5 is in the L state accordingly.
It becomes a state. At time t _13, the input signal IN3 to the L state, the test output T5 becomes H state is accompanied thereto. At time t _14, the input signal IN4 becomes L state, this is accompanied, the test output T5 becomes L state. At time t _15, the input signal IN5 becomes L state, this is accompanied, the test output T5 becomes H state.

[0071] In the time t _15, when the input signal I5 Thus becomes L state, all input signals I1~I5
Becomes the L state. Further, at the time t _15, the input signal I
5 is in the L state, its input D of the D-type latch G5
, The L state is taken in, and its output Q is L
It becomes a state.

After that, at time t ₁₆ , the input signals IN1 to IN5 are all in the H state. Along with this,
The logic state input to the input D of the D-type latch G5 also becomes the H state, and the logic state of its output Q also becomes the H state.

[0073] Further, at time t _17, the output test enable signal TE is set to H state. At the rise of the output test enable signal TE, the D
The logic state applied to its input A of the type latch G5 is retained. After this, at time t ₁₈ , time t _19, etc., the input I
By inputting the input signal pattern to N1 to IN5, D
Perform C characteristic test.

At time t ₂₀ , the output test selection signal TS is set to the L state in order to end such a series of DC characteristic tests and return to the normal state. Further, the output test enable signal TE is also in the L state.

As described above, in the third embodiment, the DC characteristic test to which the present invention is applied can be performed even if the bidirectional input / output terminal PIO is provided. In particular, by providing the D-type latch G5 of the corresponding input test circuit for such an input / output terminal PIO, the output of the input buffer BI can be held and a DC characteristic test regarding the input can also be performed. I am able to do it.
It is also possible to perform a DC characteristic test on the output of such a bidirectional input / output terminal PIO.

[0076]

As described above, according to the present invention,
The excellent effect that the work efficiency of the DC characteristic test of the semiconductor integrated circuit itself can be improved can be obtained.

[Brief description of drawings]

FIG. 1 is a logic circuit diagram of a first embodiment or a second embodiment of a semiconductor integrated circuit to which the present invention is applied.

FIG. 2 is a diagram showing an input signal pattern (test pattern) used in the second embodiment.

FIG. 3 is a logic circuit diagram of a third embodiment of a semiconductor integrated circuit to which the present invention is applied.

FIG. 4 is a time chart showing the operation of the third embodiment.

FIG. 5 is a circuit diagram of a DC characteristic test on an input terminal and an output terminal of a conventional semiconductor integrated circuit.

FIG. 6 is a circuit diagram of a semiconductor integrated circuit in which a conventional DC characteristic test for input is considered.

FIG. 7 is a diagram showing an example of an input signal pattern (test pattern) used in the conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit 3 ... Internal circuit 12 ... Input control device 14 ... Input triber 16 ... Input test power supply 22a, 22b ... Comparator 24 ... Path determination device 26 ... Output test power supply BI1-BIm, B1, B2 ... Input buffer BO1- B On, B3 ... Output buffer G1 to G4 ... AND logic gate G5 ... D type latch PIO ... Input / output terminal PI1 to PIm ... Input terminal PO1 to POn ... Output terminal TG1 to TGm ... NAND logic gate (input test circuit) TM1 to TMn , TM ... multiplexer (those used to output test circuit) t ₁₁ ~ t ₂₀ ... time

Claims (1)

[Claims] 1. A semiconductor integrated circuit having a predetermined logic circuit built therein as an internal circuit, which is used when a signal is input to the internal circuit from outside the semiconductor integrated circuit to be tested by a DC characteristic test. A total of m input buffers, a test output T (i −1) of another input test circuit of the preceding stage provided for each input buffer, and an input corresponding to the input test circuit of this stage. A total of m input test circuits that are daisy-chain connected to each other and perform a specific logical operation with the output of the buffer and output the operation result as the test output Ti of the input test circuit of the present stage, and the DC characteristic test A total of n output buffers, which are used when outputting a signal from the internal circuit to the outside of the semiconductor integrated circuit to be tested, and provided for each output buffer Is either to change the output of the corresponding output buffer in response to a signal from the internal circuit, said test output Tm of the input test circuit of the final stage outputs
A total of n output test circuits which are changed according to the above or are selected according to a predetermined output test selection signal.