JP2003332891A - Oscillator circuit, semi-conductor device including the same, semi-conductor storage device, and method for controlling the oscillator circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillator circuit which shortens the unstable transition period of a oscillation frequency when oscillation is started in the oscillator circuit to be controlled in operating and stopping, and outputs the oscillation signal with the stabilized oscillation frequency immediately after the start of oscillation. <P>SOLUTION: When an oscillation permitting signal (EN) is in an in-active state, a switch part 1 becomes conductive, and a prescribed signal from a signal generating part 2 is supplied to a control line (VR). When the oscillation permitting signal (EN) is changed into an active state, an oscillation frequency control signal (VR) is set in the control line (VR) in a short time even with the limited driving ability of a control part 7. Thus, the unstable oscillation signal due to a transition signal transfer in the control line (VR) is prevented from being outputted from the oscillating part 8. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit capable of controlling operation / stop, a semiconductor device and a semiconductor memory device having an oscillator circuit, and a method of controlling an oscillator circuit, and more particularly to a method of controlling oscillation. In regard to stable operation in.

[0002]

2. Description of the Related Art In recent years, with the progress of higher functionality in electronic equipment, in semiconductor devices and semiconductor memory devices, there is a strong demand for reduction of current consumption in combination with higher functionality of circuits. This is not only required for mobile devices, but is becoming an indispensable technology for future products in connection with the tendency toward energy saving due to the recent increase in environmental problems.

In order to meet this requirement, the bias current required for circuit operation is reduced to the utmost limit, and control is performed to stop unnecessary circuit operation. The same applies to the oscillation operation of the oscillator circuit. A circuit configuration is proposed in which the bias current required for the oscillation operation is reduced to the limit, and the oscillator is used in the standby mode such as the power-down mode where only the limited circuit operation is performed. Low current consumption control is performed such as stopping the oscillation operation of the circuit and also cutting off the current path of the bias circuit.

In the semiconductor device 1000 shown in FIG. 13, a boosted voltage higher than the power supply voltage is required or a MOS transistor is required when an external interface having a voltage higher than its own power supply voltage is required or a memory cell is accessed. A negative voltage may be needed for the back gate bias of the transistor. Therefore, the booster / negative power supply circuit 20
It has 0. In general, in the semiconductor device 1000, in order to generate a boosted voltage higher than the power supply voltage or a negative voltage of reverse polarity inside the device, charge is supplied to the capacitor by a charge pump method or the like, or It is necessary to extract the charge from the capacitor. Therefore, the oscillation signal is input from the oscillator circuit 100 to the booster / negative power supply circuit 200.

Here, in FIG. 13, the semiconductor device 10 is provided with two sets of oscillator circuits 100.
This is for supplying an oscillating signal according to the operating state of 00 to the boosting / negative power supply circuit 200. The activation signal ACT of one oscillator circuit 100 is input to the enable (EN) terminal. In the other oscillator circuit 100, the standby signal SBY that is the inverted activation signal ACT is input to the enable (EN) terminal.

When activation signal ACT is activated, internal circuit 400 is in the operating state, and therefore boosting / negative power supply circuit 200 must have sufficient power supply capability. Therefore, the oscillator circuit 100 activated by the activation signal ACT needs to output an oscillation signal at a high oscillation frequency in order to secure sufficient power supply capability from the boost / negative power supply circuit 200. At this time, the oscillator circuit 100 activated by the standby signal SBY is in the idle state.

When the standby signal SBY is activated, the internal circuit 400 is in the standby state. In this case, it is necessary to reduce the current consumption of the semiconductor device 1000 to the minimum necessary. Therefore, it is only necessary that the booster / negative power supply circuit 200 be supplied with the minimum necessary power supply for maintaining the bias state in the internal circuit 400. Therefore, the oscillator circuit 100 activated by the standby signal SBY may operate at a lower frequency than in the activated state. At this time, the oscillator circuit 100 that is activated by the activation signal ACT is in the idle state.

In the semiconductor memory device 2000 shown in FIG. 14 as well as the semiconductor device 1000 (FIG. 13), a voltage booster for supplying a boosted voltage or a negative voltage to the internal circuit 410 is used.
A negative power supply circuit 200 may be required, and an oscillator circuit 100 that oscillates at a high frequency when activated,
The oscillator circuit 100 that oscillates at a low frequency during standby is switched and used. Further, the semiconductor memory device 2000 includes a refresh control circuit 300 that refreshes the charges accumulated in the memory cell 500. Then, the oscillator circuit 100 measures the refresh period in order to periodically perform the refresh operation. In semiconductor memory device 2000, oscillator circuit 100 is configured to operate in a state where activation signal ACT is activated. In an operating specification in which a data holding operation is required only in the activated state in a portable device or the like, the current consumption in the standby state can be reduced to the limit by suspending the oscillator circuit 100 in the standby state and stopping the refresh operation.

The first prior art as the oscillator circuit 100 will be shown below. The oscillator circuit 100 of FIG. 15 includes an oscillator 8 and a controller 7, and controls the oscillation frequency of the oscillator 8 to a predetermined frequency by an oscillation frequency control signal VR from the controller 7. Further, the control unit 7 and the oscillation unit 8 are controlled by the enable signal EN, and actuation / stopping is performed according to the enable signal EN. The configuration is such that unnecessary oscillation operation is stopped by controlling the enable signal EN to reduce current consumption. Further, in order to obtain an oscillating operation of a predetermined frequency with a minimum required current consumption, the control unit 7
Has a configuration different from that of the oscillating unit 8 and supplies a minimum required bias. In addition, the operation is suspended during the suspension to reduce the current consumption.

FIG. 16 shows an oscillator circuit of a first specific example in the first prior art. In the control unit 720, the switch element S100 controlled by the enable signal EN is connected to the power supply voltage VDD, and the PMOS transistor TP
The oscillation frequency control signal VR is output from the gate terminal and the drain terminal which are connected to the source terminal of 100 and are connected to each other. Further, it is connected to the ground voltage VSS via the resistance element R100. The oscillation frequency control signal VR is
Switch element S100, PMOS transistor TP10
0, and a bias current IC flowing in a current path formed via the resistance element R100. here,
The bias current IC is generally set to a limited small current value due to the demand for low current consumption operation. For example,
If the resistance value of the resistance element R100 is set to 1 MΩ, it is set to about several microamperes.

Further, the oscillating section 830 includes the odd-numbered stages (in FIG. 16, three stages are illustrated) of inverter elements INV100 to INV.
The NV 102 is connected in a loop to form a ring oscillator. Each inverter element INV100 to INV
The power supply terminal of V102 is the PMOS transistor TP10.
1 to the power supply voltage VDD. PMOS
The gate terminal of the transistor TP101 is controlled by the oscillation frequency control signal VR. A switch element S10 controlled by the enable signal EN from the inverter element INV102
The oscillation signal VOSC is output via 1.

FIG. 17 shows an oscillator circuit of a second specific example in the first prior art. Oscillator 830 of First Specific Example
Instead of this, an oscillating unit 810 is provided. Oscillator 810
Is a NOR element NO instead of the inverter element INV102.
R100 is provided, and the enable signal EN is input to the other input terminal of the NOR element NOR100.

In the first and second specific examples, the enable signal EN is activated in a low level state. When the switch element S100 is turned on, the bias current IC flows through the control unit 720, and the control line VR changes the oscillation frequency control signal VR.
Biased to. In the oscillators 810 and 830 to which the oscillation frequency control signal VR is input, the controller 7 outputs the drive current.
A bias current IC equal to 20 flows and the ring oscillator oscillates. In the first specific example, the switch element S
Since 101 is conductive, the oscillation signal VOSC is output. Further, in the second specific example, since the NOR element NOR100 to which the low level enable signal EN is input functions as a logical inversion element, the ring oscillator operates and the oscillation signal VOSC is output.

FIG. 19 shows an oscillator circuit of a third example of the first prior art. Control unit 720 of the second specific example
Instead of this, a control unit 740 is provided. Control unit 740
Then, instead of the switch element S100, the switch element S1
02 is inserted between the resistance element R100 and the ground voltage VSS. The switch element S102 is controlled by the enable signal EN. The enable signal EN is inverted and input to the other input terminal of the NOR element NOR100 by the inverter element INV103.

In the third example, the enable signal EN is activated in the high level state. Switch element S102
Is conducted, a bias current IC flows through the control unit 740, and the control line VR is biased by the oscillation frequency control signal VR.
The bias current IC also flows into the oscillator 810, and the ring oscillator performs an oscillating operation. In the third specific example, the enable signal EN is inverted by the inverter element INV103 and input to the NOR element NOR100 as a low level. The NOR element NOR100 functions as a logic inversion element, the ring oscillator operates and the oscillation signal VOSC is output.

The second oscillator circuit 100 is used.
As a conventional technique, an oscillator circuit disclosed in Japanese Patent Laid-Open No. 11-317623 is shown in FIG. The oscillator circuit of FIG. 21 includes an oscillator 910 and a pulse generator 920. The monostable multivibrator MM of the pulse generator 920 detects the rising of the power supply voltage VCC and generates a high-level control pulse P for a certain time t1.
As a result, the switch SW is turned on and a large initial current is supplied to the piezoelectric vibrator X for a certain time t1 after the power supply to the oscillation unit 910 is turned on.

FIG. 22 shows operation waveforms at the time of startup. When the power supply voltage VCC rises at time T1, the multivibrator MM detects this rise and detects the time t1.
Control pulse P is generated. The switch SW is turned on, and a large initial current is applied to the piezoelectric vibrator X. With this switch SW, oscillation is started earlier than time t2.

[0018]

However, in the oscillator circuit 100 (FIG. 15) of the first conventional technique,
As shown in the circuit diagrams of the first to third specific examples (FIGS. 16, 17, and 19), the enable signal EN changes to the oscillation units 8 and 810.
It may be input to 830 to control the operation / stop of the oscillation operation, and may control the output of the oscillation signal VOSC. The control units 7, 720, 740 to which the enable signal EN is input are oscillating units 8, 810, 830.
The oscillation frequency control signal VR for controlling the oscillation frequency of Since it takes a predetermined time for the control line VR to reach the oscillation frequency control signal VR after the activation of the enable signal EN, the oscillation frequency does not change until the oscillation signal VOSC transitions to a stable state in which it oscillates at a predetermined frequency. Be stable. There is a certain unstable period after activation, which is a problem. The existence of this unstable period may cause the following specific problems.

In the oscillating units 8, 810 and 830, the control state is determined only by the logical level of the enable signal EN, so that the oscillating operation state is set at the same time when the enable signal EN is activated. On the other hand, the control units 7, 720, 74
At 0, the current path that was interrupted in the standby state is
The control line VR is set up to the oscillation frequency control signal VR by the bias current IC flowing by being established by the activation of the enable signal EN. Where the bias current I
Since C is a small current value limited due to the request for low current consumption operation, it takes a predetermined time for the control line VR to reach the oscillation frequency control signal VR. Since the oscillating units 8, 810 and 830 are in the oscillating operation state at the same time when the enable signal EN is activated, the oscillating frequency control signal VR
The oscillation signal VOSC will be output at an oscillation frequency different from the predetermined frequency with respect to the transient voltage level until the voltage reaches. This period is an unstable period and there are various problems in circuit operation.

The unstable period X1 shown in FIG. 18 occurs in the first and second specific examples (FIGS. 16 and 17). In the control unit 720 of the first and second specific examples, the enable signal EN
When it is inactive, the control line VR drops to the ground voltage VSS. When the enable signal EN becomes low level and is activated, the control line VR gradually rises, but when the bias current has a small current value, a predetermined time ( An unstable period X1) is required. Therefore, during this period, a voltage lower than the oscillation frequency control signal VR is P of the oscillation units 810 and 830.
The ring oscillator is driven by a drive current that is applied to the MOS transistor TP101 and is larger than the set bias current IC. As a result, the oscillation signal VO
SC oscillates at a frequency higher than a predetermined frequency.

During the unstable period X1, the oscillator circuit 10
In addition to the increase in the current consumption of 0 itself, the circuit operation of the booster / negative power supply circuit 200 in the semiconductor device 1000 or the semiconductor memory device 2000 is faster than necessary, and the semiconductor memory device 2000 has the refresh control circuit 300. However, the refresh operation is executed in a shorter cycle than necessary, resulting in a large current consumption, which is a problem. When operating in an environment in which the power supply capacity is limited, such as battery drive, or in an environment in which the impedance of the power supply path cannot be ignored, the semiconductor device 1000 and the semiconductor memory device 1000 and the semiconductor memory device may have a large current consumption during the unstable period X1. Device 2
This is a problem because the power supply voltage supplied to 000 may drop more than necessary and may cause malfunction.

If the booster / negative power supply circuit 200 operates at a higher frequency than necessary, a voltage higher than the set value may be generated, which may adversely affect the reliability of the device, which is a problem. In particular, this is a problem in a use environment of a portable device or the like in which activation / deactivation of the enable signal EN is frequently repeated.

The unstable period X2 shown in FIG. 20 occurs in the third specific example (FIG. 19). Control unit 7 of the third specific example
In 40, when the enable signal EN is at a low level and is inactive, the control line VR has a voltage (VDD-V) obtained by subtracting the threshold voltage Vthp of the PMOS transistor from the power supply voltage VDD.
thp). When the enable signal EN becomes high level and is activated, the voltage level of the control line VR gradually drops to the oscillation frequency control signal VR, but when the bias current IC has a small current value, a predetermined time ( The unstable period X2) is required. Therefore, during this period, a voltage higher than the oscillation frequency control signal VR is generated by the oscillation unit 810.
In some cases, the ring oscillator is driven with a drive current smaller than the set bias current IC applied to the PMOS transistor TP101, or is not driven. As a result, the oscillation signal VOSC is oscillated at a frequency lower than the predetermined frequency or is in an oscillation stopped state.

During the unstable period X2, the oscillation frequency of the oscillation signal VOSC becomes lower than the predetermined frequency, so that the voltage generation in the step-up / negative power supply circuit 200 in the semiconductor device 1000 or the semiconductor memory device 2000 is insufficient. Will be. If the boosted voltage is insufficient, there is a risk of malfunction of the external interface portion and malfunction of access to the memory cell, which is a problem. If the negative voltage is insufficient, the back gate bias of the MOS transistor will be insufficient, which may lead to fluctuations in the threshold voltage and deterioration in noise resistance.

Further, in the semiconductor memory device 2000, the cycle of the refresh operation to be controlled by the refresh control circuit 300 becomes longer than necessary, which may cause data loss depending on the data retention characteristic. is there.

Here, the relationship between the oscillation frequency control signal VR and the oscillation frequency of the oscillation signal VOSC will be described. The oscillation frequency is the inverter element IN that constitutes the ring oscillator.
It is determined by the propagation delay time such as V100 to INV102. Then, this propagation delay time is
In the cases of the first to third specific examples in which the driving capability of the transistors constituting V100 to INV102 is sufficiently large, it is determined by the bias current IC which is the driving current supplied to each power supply terminal. Bias current IC
This is because the charging / discharging time of the input capacitance of each stage becomes the propagation delay time. That is, the oscillation frequency of the oscillation signal VOSC is proportional to the bias current IC.

The bias current IC operates with the saturation characteristic of the PMOS transistor TP101, and has a relationship of IC = K × ((VDD-VR) -Vthp) ² = K × ((VDD-Vthp) -VR) ² . Here, K is a PMOS transistor P
A physical constant 101 has. Moreover, Vthp shows a positive value. Therefore, the threshold voltage is -Vth
p. This equation holds true because the gate-source voltage does not fall below the threshold voltage, so VR
<It is a relational expression in VDD-Vthp.

Therefore, when VR = VDD-Vthp,
IC = 0, the oscillation operation stops, and V
In the region of R <VDD-Vthp, the bias current IC changes with the square characteristic with respect to the change of VR. That is, the oscillation frequency changes with the square characteristic with respect to the change of VR, and the oscillation frequency of the oscillation signal VOSC changes greatly during the unstable periods X1 and X2.

Oscillation circuit in the second prior art (FIG. 21)
Then, although the switch SW causes the oscillation to start earlier by the time t2, the oscillation signal OUT has a small amplitude immediately after the start of the oscillation and gradually increases and becomes stable. Even if the time until the start of oscillation is shortened, the unstable period after the start of oscillation cannot be resolved, which is a problem.

The second prior art has a circuit configuration in which the operation is started by turning on the power supply as a start signal. The rising waveform of the power supply voltage VCC at this time assumes a sharp voltage transition as shown in FIG. Therefore, it is mounted on the semiconductor device 1000 or the semiconductor memory device 2000, and has a function of switching between a standby state such as a power down mode and an active state while the power supply voltage is still applied, and enables the enable signal EN and the like. It cannot be applied when the starting operation is performed based on the input of the control signal.

The fixed period t1 in which the control pulse P is at the high level is set by the resistance element Ra and the capacitance element Ca which are passive elements. On the other hand, the switch SW controlled to be in the ON state by the high-level control pulse P is an active element. Further, the fixed period t1 in which the initial current is applied to the piezoelectric vibrator X is selected by an experiment so that the starting time can be minimized. Since the passive element and the active element are composed of different elements and structures, it is common that they have manufacturing variations independent of each other. Therefore, the fixed time t1 determined by the passive elements Ra and Ca may be an arbitrary combination of the threshold value and the driving ability of the active element SW in the ON state, and it may be difficult to maintain the condition selected in the experiment. There is a problem.

For example, when the piezoelectric vibrator X is insufficiently activated due to the constant time t1 or the insufficient drive capability of the switch, a further activation time is required after the constant time t1 ends. On the contrary, when the constant time t1 is excessive, the activation time of the piezoelectric vibrator X continues longer than necessary.
In any case, the startup time cannot be optimized, which is a problem.

The present invention has been made in order to solve the above-mentioned problems of the prior art, and shortens the transient unstable period of the oscillation frequency at the start of oscillation of the oscillator circuit capable of controlling the operation / stop. It is an object of the present invention to provide an oscillator circuit capable of outputting an oscillation signal having a stable oscillation frequency immediately after the start of oscillation, a semiconductor device and a semiconductor memory device including the oscillator circuit, and a method for controlling the oscillator circuit. .

[0034]

In order to achieve the above-mentioned object, an oscillator circuit according to a first aspect of the present invention includes an oscillating section that oscillates at an oscillation frequency according to an oscillation frequency control signal.
It is placed between the control unit that outputs the oscillation frequency control signal to the oscillator through the control line and the signal generation circuit and the control line when the oscillation enable signal is activated. And a switch unit for supplying a predetermined signal from the signal generating circuit to the control line.

In the oscillator circuit of the first aspect, the oscillating section and the control section are activated and the oscillating operation is performed in the activated state of the oscillation enable signal. The oscillation frequency is set by an oscillation frequency control signal output from the control unit to the oscillation unit via the control line. When the oscillation enable signal is inactive, the oscillating unit and the control unit are inactivated. At this time, a predetermined signal is supplied from the signal generating circuit to the control line via the switch unit.

In the oscillator circuit control method according to the present invention, when the oscillation operation is performed in response to the oscillation frequency control signal, the oscillation frequency control operation is activated by the activation of the oscillation enable signal, and the control state is maintained. Is a method of controlling an oscillator circuit in which the oscillation frequency shifts to a set value by shifting to a preset setting state, in which the control state from the signal generator is when the oscillation enable signal is inactive. It is characterized by being maintained in a predetermined state by a signal.

The oscillator circuit according to claim 2 is
An oscillation unit that oscillates at an oscillation frequency according to the oscillation frequency control signal, a first control unit that outputs the oscillation frequency control signal to the oscillation unit through a control line when the oscillation permission signal is activated, and an oscillation permission signal. When activated, the pulse generator that outputs a pulse signal, and activated by the pulse signal,
It is characterized by including a second control unit that outputs a predetermined signal, and a switch unit that is arranged between the second control unit and the control line, conducts by a pulse signal, and supplies the predetermined signal to the control line. .

In the oscillator circuit of the second aspect, the oscillating section and the first control section are activated and the oscillating operation is performed in the activated state of the oscillation enable signal. The oscillation frequency is set by the oscillation frequency control signal output from the first control unit to the oscillation unit via the control line. When the oscillation enable signal is activated, the switch unit and the second control unit are activated during the pulse signal output from the pulse generation unit, and the predetermined signal is transmitted from the second control unit to the control line via the switch unit. Supplied.

Further, in the oscillator circuit control method according to the present invention, when the oscillation operation is performed in response to the oscillation frequency control signal, the first control operation of the oscillation frequency is activated by activation of the oscillation permission signal, This is a method for controlling an oscillator circuit in which the oscillation frequency shifts to a set value as the control state shifts to a preset setting state, and the control state is maintained for a predetermined period after the oscillation enable signal is activated. The second control operation that shifts to a predetermined state is activated.

As a result, when the oscillation enable signal is inactive and the control unit is inactive, or during a predetermined period such as a pulse signal when the oscillation enable signal transits to the active state, a predetermined signal is applied to the control line. Therefore, when the control unit or the first control unit is activated by activating the oscillation enable signal, the time delay until the signal on the control line is set to the oscillation frequency control signal is shortened. Therefore, the unstable period of the oscillation frequency when the oscillation is permitted can be shortened.

It is possible to suppress fluctuations in the oscillation frequency during the unstable period, increase in consumption current and fluctuations in voltage due to fluctuations in the oscillation frequency, and malfunctions and the like accompanying them. It is suitable for use in power saving applications represented by the field of portable devices, in which the operating state can be switched between a normal use state and a standby state such as a power down mode that supports low current consumption.

An oscillator circuit according to a third aspect is the oscillator circuit according to the first or second aspect, further comprising a detection section for controlling the oscillating section according to a detection signal obtained by detecting a signal on the control line. .

As a result, the signal on the control line is detected, and when the signal corresponding to the predetermined oscillation frequency is reached,
The oscillating unit can be controlled to start an oscillating operation or output an oscillating signal. When the control unit or the first control unit is activated by the activation of the oscillation enable signal, it is detected that the signal on the control line has not reached a signal equivalent to the oscillation frequency control signal, and the error when the oscillation is enabled is detected. It is possible to prevent output of a stable oscillation frequency.

An oscillator circuit according to a fourth aspect is the oscillator circuit according to the first or second aspect, further comprising: a delay unit for controlling the oscillation unit by outputting a delay signal obtained by adding a predetermined delay time to the oscillation permission signal. It is characterized by including.

Thus, the time for the oscillation frequency control signal output from the controller or the first controller to stabilize can be added as the predetermined delay time, and the oscillator can be controlled after the oscillation frequency control signal stabilizes. Then, the oscillation operation can be started or an oscillation signal can be output.
A stable oscillation signal can be obtained.

A semiconductor device according to a fifth aspect includes an oscillator circuit according to at least one of the first to fourth aspects, and a voltage generating circuit that generates a voltage in response to an oscillation signal output from the oscillator circuit. It is characterized by including.

According to a sixth aspect of the semiconductor memory device of the present invention,
The oscillator circuit according to any one of claims 1 to 4 is provided, and a voltage generation circuit that generates a voltage in response to an oscillation signal output from the oscillator circuit is provided.

According to a seventh aspect of the semiconductor memory device,
An oscillator circuit according to any one of claims 1 to 4, and a refresh control circuit for controlling a refresh cycle in response to an oscillation signal output from the oscillator circuit.

In the semiconductor device of the fifth aspect or the semiconductor memory device of the sixth aspect, the voltage generating circuit generates a voltage in response to the oscillation signal output from the oscillator circuit. According to another aspect of the semiconductor memory device of the present invention, the refresh control circuit controls the refresh cycle in response to the oscillation signal output from the oscillator circuit.

As a result, even when the oscillation enable signal is activated, an unstable oscillation signal is not output to the voltage generation circuit or the refresh control circuit, and stable circuit operation can be performed.

That is, a large current consumption due to the output of an unstable high-frequency oscillation signal, a malfunction due to a power supply voltage drop accompanying this, or the reliability of a semiconductor device or a semiconductor memory device due to excessive voltage generation. No problems will occur. On the contrary, the fluctuation of the transistor characteristics due to the unstable output of the low-frequency oscillation signal or the stop of the oscillation, the deterioration of the noise resistance, the disappearance of the stored data in the semiconductor memory device, etc. do not occur.

The principle of the present invention will be described below with reference to the first and second principle explanatory diagrams (FIGS. 1 and 2). First, the solid line portion will be described.

The oscillator circuit 100 of the present invention shown in FIG.
The first principle diagram of FIG. 3 illustrates the principle of the present invention corresponding to claim 1. The control unit 7 and the oscillating unit 8 have a control line (V
R) and both are controlled by the oscillation enable signal (EN). The oscillation enable signal (EN) causes the oscillator 8 to be ready for oscillation, and the controller 7 starts the control operation.
The control unit 7 that has started the control operation outputs an oscillation frequency control signal (VR) corresponding to a predetermined oscillation frequency to the oscillation unit 8 via the control line (VR). Oscillator circuit 10
The signal generator 2 provided outside 0 is connected to the control line (VR) via the switch 1. The switch unit 1 is controlled by the oscillation enable signal (EN).

The control unit 7 is activated by the oscillation enable signal (EN) and starts the control operation. However, the driving capability may be limited to a small amount due to a request such as low current consumption. In some cases, it takes a long time for the control line (VR) to reach the oscillation frequency control signal (VR). Therefore, when the oscillation enable signal (EN) is inactive, the switch section 1 is turned on to supply a predetermined signal from the signal generating section 2 to the control line (VR). Here, the signal generator 2 is a unit that is provided outside the oscillator circuit 100 in advance and supplies a predetermined signal to the components other than the oscillator circuit 100. In the first principle of the present invention, the predetermined signal is used.

In FIG. 1, an external signal generator 2 and a switch section constitute a preset section A1. Since the predetermined signal is supplied to the control line (VR) while the oscillation enable signal (EN) is inactive, the control unit 7 is limited to drive when the oscillation enable signal (EN) transits to the active state. Even if the capacity is high, the control line (VR) can be set to the oscillation frequency control signal (VR) in a short time, and the transient control line (V) can be set.
The unstable oscillation signal due to the signal R) is not output from the oscillation unit 8.

The oscillator circuit 100 of the present invention shown in FIG.
The second principle diagram of (1) illustrates the principle of the present invention corresponding to claim 2. A first controller 7 is provided instead of the controller 7 in the first principle diagram, and a second controller 2 is provided instead of the signal generator 2.
The controller 3 is provided. Further, a pulse generator 4 is provided in addition to the first principle explanatory diagram. The pulse generation unit 4 outputs a pulse signal to the switch unit 1 and the second control unit 3 when the oscillation enable signal (EN) is input. The pulse signal is output in response to the activation transition of the oscillation enable signal (EN). When the pulse signal is input, the switch unit 1 becomes conductive, and the second control unit 3 is activated and supplies a predetermined signal output to the control line (VR).

According to the second principle of the present invention, in order to supplement the limited drive capability of the first controller 7, the oscillation enable signal (EN)
The second control unit 3 is driven in addition to the first control unit 7 for a predetermined period from the activation transition of (1) to enhance the drive capability until the control line (VR) reaches the oscillation frequency control signal (VR). First
The control line (VR) is set to the oscillation frequency control signal (VR) in a short time in response to the activation of the oscillation enable signal (EN) while the driving capability of the control unit 7 is limited to maintain the low current consumption operation. Therefore, the unstable oscillation signal due to the transient control line (VR) signal is not output from the oscillation unit 8.

Next, in the first and second principle explanatory diagrams of the present invention, the detection section 5 and the delay section 6 indicated by dotted lines will be described. These constituent elements 5 and 6 are not essential constituent elements in the first and second principle explanatory diagrams. By providing either one or both of them, the configuration is for surely removing the unstable operation period when the oscillation enable signal (EN) is activated.

The detecting section 5 detects whether or not the signal on the control line (VR) has been input and has reached a signal equivalent to the oscillation frequency control signal (VR) which is the set value. The detection result is input to the oscillator 8 as a detection signal (MON) to control the oscillation operation. By the detection signal (MON) indicating that the signal on the control line (VR) has reached a signal equivalent to the oscillation frequency control signal (VR), the oscillation unit 8 causes the oscillation enable signal (E).
With N), it is controlled to start an oscillation operation or output an oscillation signal.

Further, the delay section 6 has an oscillation enable signal (EN).
Is output to the oscillating unit 8 after a predetermined delay time is added. When the oscillation enable signal (EN) is activated, the control line (V
The predetermined delay time is set in accordance with the transition period in which the signal R) changes to a signal equivalent to the oscillation frequency control signal (VR). After the signal on the control line (VR) reaches a signal equivalent to the oscillation frequency control signal (VR), it is controlled to start the oscillation operation of the oscillation unit 8 or output the oscillation signal, and the transient oscillation frequency An unstable oscillation signal due to the setting of the control signal (VR) will not be output from the oscillation unit 8.

As another method of maintaining the detection unit 5 in the inactive state, the detection unit 5 may be controlled by the oscillation enable signal (EN). If the circuit operation of the detection unit 5 is inactivated in the inactive state, the operation of the detection unit 5 can be stopped regardless of the signal of the control line (VR).

[0062]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an oscillator circuit of the present invention,
A semiconductor device and a semiconductor memory device including an oscillator circuit, and an embodiment embodying a method of controlling the oscillator circuit will be described in detail with reference to the drawings based on FIGS. 3 to 14.

The oscillator circuit 101 shown in FIG.
It is the oscillator circuit of 1st Embodiment with respect to a principle diagram (FIG. 1). The control unit 71 includes the switch element S10 included in the control unit 720 in the first specific example of the first conventional technique.
0 is replaced by a PMOS transistor TP0 and an NMOS transistor TN1. The low-active enable signal EN is input to the enable (E) terminal to directly control the gate terminal of the PMOS transistor TP0 and also to NMO via the inverter element I1.
It controls the gate terminal of the S transistor TN1. In the control unit 71, the bias current IC is generally set to a small current value limited due to a request for low current consumption operation. For example, if the resistance value of the resistance element R100 is set to 1 MΩ, it is set to about several microamperes.

The oscillating section 81 has the same structure as the oscillating section 810 in the second specific example of the first prior art, and is connected to one input terminal of the NOR element NOR100 forming the ring oscillator via the enable (E) terminal. Enable signal EN
Is entered.

The switch section 11 is composed of a so-called transfer gate SW1 in which the source terminal and the drain terminal of the PMOS transistor and the NMOS transistor are connected to each other. The enable signal EN is directly input to the gate terminal of the NMOS transistor and the gate terminal of the PMOS transistor is logically connected to the gate terminal of the PMOS transistor via the inverter element I2 so that the low active enable signal EN is rendered conductive at the high level. It is inverted and input. The switch element 11 has a control line VR
And the output terminal VR2 of the potential generation circuit 21 provided outside the oscillator circuit 101 are electrically connected. The switch section 11 and the potential generation circuit 21 constitute a preset circuit A11 for the control line VR.

FIG. 4 shows operation waveforms. Enable signal E
When N is at a low level, both the PMOS transistor TP0 and the NMOS transistor TN1 of the control unit 71 become conductive and the bias current IC flows. This bias current IC is converted into a voltage value by flowing into the diode-connected PMOS transistor TP100,
The oscillation frequency control signal VR is output to the control line VR.

The oscillation frequency control signal VR output to the control line VR is the PMOS transistor TP1 of the oscillator 810.
The inverter element and the NOR element NOR10 which are input to the gate terminal of the inverter 01 and constitute the ring oscillator.
A bias current IC is supplied to the 0 power supply terminal. here,
Although it has been described that the PMOS transistors TP100 and TP101 have the same size and the bias currents flowing through the two are the same bias current IC, the size of both transistors is appropriately changed to provide a difference in driving capability. Needless to say, the bias current ratio can be set according to the difference in driving ability.

At this time, enable (E) of the oscillating unit 810
The low-level enable signal EN is input to the terminal, and the NOR element NOR100 functions as a logic inverting element. Therefore, a ring oscillator loop is formed in the oscillating unit 810, and each element driven by the bias current IC outputs the oscillation signal VOSC of a predetermined frequency.

The oscillation frequency of the oscillation signal VOSC is determined by the bias current IC, which is determined by the oscillation frequency control signal VR generated by the controller 71. That is, the oscillation frequency control signal VR is determined by the bias current IC flowing in the diode-connected PMOS transistor TP100 having a predetermined driving capability, and the PMOS transistor TP having a predetermined driving capability.
By being supplied to the gate terminal of 101, a predetermined bias current IC is set as the power supply current of each element forming the ring oscillator. This is because the bias current IC determines the propagation delay time due to the charging / discharging time of the input capacitance of each stage, and the time obtained by adding the propagation delay time for one round of the ring oscillator is the oscillation period T0 in the steady state.

At this time, since the switch section 11 is in the off state, the control line VR and the output voltage of the potential generating circuit 21 are disconnected.

Next, it is assumed that the enable signal EN makes a transition to a high level and becomes an inactive state. Control unit 71
In, the PMOS transistor TP0 and the NMOS
Both the transistors TN1 are turned off, the current path of the bias current IC is cut off, and the output to the control line VR becomes a floating state. At the same time, in the oscillation unit 810, the output signal of the NOR element NOR100 is fixed to the low level to interrupt the loop of the ring oscillator, and the oscillation signal VOSC is fixed to the low level to stop the oscillation operation.

At this time, the switch section is conducted (ON),
Instead of the control unit 71 in the floating state, the potential generation circuit 21 sets the voltage level of the control line VR to the predetermined voltage VR2. Here, it is preferable that the predetermined voltage VR2 has a voltage level equivalent to that of the oscillation frequency control signal VR.

When the enable signal EN transits to the low level again and transits to the active state, the switch section 11 is turned off (OFF), the potential generating circuit 21 is disconnected from the control line VR, and the control section 71 and the oscillation are generated. The parts 810 are activated together.

As described above in detail, according to the first embodiment, the control unit 71 is operated in response to a request such as a low current consumption operation.
When the drive capability is limited to a small level, the preset section A11 including the switch section 11 and the potential generation circuit 21 controls the voltage level of the control line VR when the enable signal EN is inactive.
Since the voltage level can be maintained at the predetermined voltage VR2 that is equivalent to the voltage level, it is possible to return to the steady state in a short return time X01. Since the recovery time is short, the generation period of the transient oscillation frequency can be short. In addition, since the predetermined voltage VR2 in the inactive state is equal to the oscillation frequency control signal VR, the difference in the bias current IC becomes small, and the transient oscillation cycle TS1 during the recovery period is close to the oscillation cycle T0 in the steady state. It can be a cycle.

At this time, the control unit 71 and the potential generation circuit 21
And preferably have equivalent circuit configurations with equivalent circuit elements. As a result, variations in element parameters due to variations in manufacturing act equally, and the same bias condition is maintained for variations in element parameters. Specifically, if the potential generation unit 21 has a circuit configuration equivalent to that of the control unit 71, the element variation has the same effect, and therefore the voltage level of the oscillation frequency control signal VR output by the control unit 71 and the potential generation. Circuit 21
This is convenient because it is always set with a constant correlation with the predetermined voltage VR2 output by.

When the enable signal EN, which is an oscillation enable signal, is at a high level and is inactive and the control section 71 is inactive, a predetermined voltage VR, which is a predetermined signal, is applied to the control line VR.
Since 2 can be supplied, the time until the voltage level of the control line VR is charged to the oscillation frequency control signal VR when the control unit 71 is activated by the activation that the enable signal EN becomes low level. The delay can be shortened, and the unstable period of the oscillation frequency at the time of activation can be shortened.

Further, it is possible to suppress fluctuations in the oscillation frequency during the unstable period, increase in consumption current and fluctuations in voltage due to fluctuations in the oscillation frequency, and malfunctions and the like accompanying these fluctuations. It is suitable for use in power-saving applications represented by the field of mobile devices in which the operating state is switched between a standby state that supports low current consumption.

The oscillator circuit 102 shown in FIG.
It is the oscillator circuit of 2nd Embodiment with respect to a principle diagram (FIG. 2). A first control unit 72 is provided instead of the control unit 71 in the oscillator circuit 101 of the first embodiment. Further, in addition to the oscillator circuit 101 of the first embodiment, a pulse generator 41 and a second controller 31 are provided. Further, the potential generating circuit 21 used in the first embodiment is not used. Switch unit 11, pulse generation unit 41, and second
The control section 31 constitutes a preset section A21.

The first control section 72 has a structure in which the switch element S100 provided in the control section 720 in the first specific example of the first prior art is replaced with a PMOS transistor TP01. Low active enable signal EN
Is input to the enable (E) terminal and directly controls the gate terminal of the PMOS transistor TP01. Also PM
A PMOS transistor TP11 and a resistance element R11 are provided instead of the OS transistor TP100 and the resistance element R100. Here, the gate width and gate length of the PMOS transistor TP11 are W1 and L1. The bias current IC1 is set by the ratio of the gate width and the gate length (gate width / gate length = W1 / L1) of the PMOS transistor TP11 and the resistance value of the resistance element R11. First
Similar to the control unit 71 of the embodiment, the bias current IC1 is generally set to a limited small current value due to a request for low current consumption operation. For example, if the resistance value of the resistance element R11 is set to 1 MΩ, it is set to about several microamperes.

The pulse generating section 41 has a NOR element NOR2.
And an odd number of stages connected in series (three stages are illustrated in FIG. 5)
And a delay circuit configured to measure the delay time of τX02. One input terminal of the NOR element NOR2 and the input terminal of the delay circuit are connected to the enable (E) terminal, and the enable signal EN is input. The other input terminal of the NOR element NOR2 is connected to the output terminal SET of the delay circuit. The pulse generator 41 outputs the high-level pulse signal SET by using the low-level transition of the enable signal EN as a trigger signal. In this case, the pulse width is τX02. The output pulse signal SET is input to the switch unit 11 and inverted by the inverter element I2 of the switch unit 11 to generate the second pulse signal.
It is input to the enable (E) terminal of the control unit 31.

The second control section 31 has the same structure as the first control section 72. Instead of the PMOS transistors TP01 and TP11 and the resistance element R11, which are the constituent elements of the first control unit 72, the PMOS transistor TP0.
2, TP12, and a resistance element R12. The low active enable signal EN is inverted by the switch unit 11 and then input to the enable (E) terminal to directly control the gate terminal of the PMOS transistor TP02. The gate width and gate length of the PMOS transistor TP12 are W2 and L2. The bias current IC2 flowing in the current path is the ratio of the gate width and the gate length of the PMOS transistor TP12 (gate width / gate length = W2 / L2).
And the resistance value of the resistance element R12.

The bias current IC2 of the second control section 31 is set to have a larger current value than the bias current IC1. At this time, W2 / L2 is larger than W1 / L1 in accordance with the increase of the current value so that the bias condition of the second control unit 31 becomes equal to the bias condition of the first control unit 72, and the resistance is increased. The resistance value of the element R12 is set smaller than the resistance value of the resistance element R11. Therefore, the output from the second control unit 31, which is output by the bias current IC2 flowing through the diode-connected PMOS transistor TP12, makes a steeper transition than the output from the first control unit 72, and oscillation frequency control is performed. The voltage level is equivalent to the voltage level of signal VR. The output terminal of the second control unit 31 is connected to the control line VR via the switch unit 11 during the output period of the pulse signal SET, and the control line VR is connected to the oscillation frequency control signal VR.
Charges and discharges rapidly to a voltage level equivalent to.

FIG. 6 shows operation waveforms. Enable signal E
When N is at the low level, the output of the pulse generation unit 41 is maintained at the low level and the switch unit 11 is in the non-conductive state. The oscillation operation is the same as the operation waveform (FIG. 4) of the first embodiment, and therefore the description thereof is omitted here.

When the enable signal EN transits to the high level and transits to the inactive state, when the PMOS transistor TP01 is turned off in the first controller 72, the current path of the bias current IC1 is cut off, and The output terminal to the control line VR is connected to the ground voltage VSS via the resistance element R11. The output of the pulse generator 41 at this time is maintained at a low level, and the switch unit 11 is in a non-conductive state. Therefore, the voltage of the control line VR drops to approximately the ground voltage VSS. At the same time, the oscillator 81
The output signal of the NOR element NOR100 of 0 is fixed to the low level to interrupt the loop of the ring oscillator, the oscillation signal VOSC is fixed to the low level, and the oscillation operation is stopped.

When the enable signal EN transits to the low level again, the first controller 72 is activated and the bias current IC1 flows. At the same time, the pulse signal SET is output from the pulse generator 41. The pulse signal SET conducts the switch unit 11 to connect the output terminal of the second control unit 31 to the control line V.
The second control unit 31 is activated while being connected to R. The second controller 31 charges the control line VR to a voltage level equivalent to that of the oscillation frequency control signal VR via the switch 11.

As described above in detail, according to the second embodiment, the second control unit 31 has a smaller drive capacity than the first control unit 72 whose driving capability is limited to a small amount due to a request for a low current consumption operation or the like. By setting the driving capability of the control circuit to be sufficiently large, the voltage level of the control line VR can be charged to a voltage level equivalent to the voltage level of the oscillation frequency control signal VR within the output period of the pulse signal SET. In this case, by adjusting the current value of the bias current IC2 and the output period of the pulse signal SET, during the pulse period τX02, the voltage level of the control line VR is charged to a voltage level equivalent to the voltage level of the oscillation frequency control signal VR. It is preferable to set the time longer than the time.

At this time, the second controller 31 and the first controller 7
2 is preferably provided with the same circuit configuration by the same circuit element. As a result, variations in device parameters due to variations in manufacturing act equally on both control units 31 and 72. In both control units 31 and 72 having the same circuit configuration, the same bias condition can be maintained with respect to the variation of the element parameter, and the same action / effect can be maintained. Furthermore, if the constituent elements of the pulse generation unit 41 and the switch unit 11 are also provided with equivalent circuit elements, both control units 31, 72, the pulse generation unit 41, The switch section 11 and the switch section 11 can be set so as to have a predetermined correlation and can maintain the same action and effect with respect to the variation of the element parameter.

Specifically, the voltage level of the oscillation frequency control signal VR output by the first control unit 72 and the predetermined voltage output by the second control unit 31 are always set with a certain correlation. In addition, the pulse signal S output from the pulse generator 41
The ET pulse period τX02 and the bias current IC2 of the second control unit 31 both have a correlation with the driving capability of the PMOS transistor. That is, when the driving capability is small, the delay time τ in the delay unit of the pulse generation unit 41
There is a correlation that the bias current IC2 becomes smaller as X02 becomes longer. There is a correlation that the pulse period τX02 becomes long when the bias current IC2 is small, and the pulse period τX02 becomes short when the bias current IC2 is large. The control line VR can be charged during the output period of the pulse signal SET regardless of variations in element parameters.

During the pulse period τX02 when the enable signal EN transits to the low level and transits to the active state by the preset section A21, the second control section 31 promptly changes the voltage level of the control line VR to the oscillation frequency control signal VR. Since it can be charged to a voltage level equivalent to, it can return to a steady state in a short return time X02. Since the recovery time is short, the generation period of the transient oscillation frequency is short, and in addition, the rapid charging to the voltage level of the oscillation frequency control signal VR causes the transient period during the recovery period. The oscillation cycle TS2 can be a cycle close to the oscillation cycle T0 in the steady state.

When the enable signal EN changes to the low level and transitions to the active state, the pulse signal S of the predetermined period τX02
Since a predetermined signal having a voltage level equivalent to the oscillation frequency control signal VR can be supplied from the second control unit 31 to the control line VR at ET, the activation of the enable signal EN activates the first control unit 72. In this case, the time delay until the voltage level of the control line VR is charged to a voltage level equivalent to the oscillation frequency control signal VR can be shortened, and the unstable period of the oscillation frequency during activation can be shortened. You can

It is possible to suppress fluctuations in the oscillation frequency during the unstable period, increase in consumption current and fluctuations in voltage due to fluctuations in the oscillation frequency, and malfunctions and the like accompanying them. It is suitable for use in power saving applications represented by the field of portable devices, in which the operating state can be switched between a normal use state and a standby state such as a power down mode that supports low current consumption.

Next, a concrete example of the case where the detecting unit (FIGS. 7 and 8) or the delay unit (FIG. 9) is provided in the first or second embodiment will be described. In the first or second embodiment, the voltage level of the control line VR is oscillated by maintaining the voltage level of the control line VR at a predetermined voltage VR2 when it is inactive or by rapidly charging it when transitioning to the active state. An unstable oscillation operation can be shortened by shortening the time for which the voltage level is equivalent to that of the frequency control signal VR. 7 to 9, it is further detected that the voltage level of the control line VR has reached a predetermined voltage level (FIGS. 7 and 8), or the time to reach the predetermined voltage level is measured (FIG. 9). . This is a measure to more reliably eliminate the unstable oscillation operation immediately after startup.

FIG. 7 shows a first specific example in the case where a detection unit is provided. The enable (E) terminal of the oscillator 8 is
The logical sum of the detection signal MON1 from the detection unit 51 and the enable signal EN is input by the NOR element NOR3 and the inverter element I3. Here, the detection signal MON1 and the enable signal EN are both low active signals, and when both input signals are low level, the low level signal is input to the enable (E) terminal of the oscillator 8 to generate the oscillator. Activate 8.

In the detection section 51, the control line VR is connected to the gate terminal of the NMOS transistor TN3. NMO
The source terminal of the S transistor TN3 is connected to the ground voltage VSS. The drain terminal is connected to the drain terminal of the PMOS transistor TP3 having the source terminal connected to the power supply voltage VDD and the gate terminal connected to the ground voltage VSS, and a logical inversion gate having this connection point as an output terminal is formed. ing. The logic inversion threshold voltage of the logic inversion gate is set by the balance between the conductance of the PMOS transistor TP3 and the conductance of the NMOS transistor TN3, and is set so as to be logically inverted with respect to the voltage level equivalent to the oscillation frequency control signal VR. There is. When the voltage level of the control line VR reaches a permissible voltage level at which the oscillation operation is performed at the permissible oscillation frequency centered on the voltage level of the oscillation frequency control signal VR, the logic is inverted and the detection signal MON1 is output. . The logic inversion threshold voltage is set near the allowable voltage level.

After activation of the control unit 71 (in the case of the first embodiment) or after presetting from the second control unit 31 (in the case of the second embodiment), the voltage level of the control line VR reaches the allowable voltage level. Up to the allowable voltage level, the logic is surely inverted and the detection signal MON1 is detected.
Can be output. The output of the first-stage logic inverting gate is output to the oscillating unit 8 as a detection signal MON1 after waveform shaping, driving capability assurance, logic matching, and the like performed by the second-stage inverter elements in the latter stage.

Here, since the detection unit 51 is always maintained in the detection state, when applied to the first embodiment, the predetermined voltage VR2 output from the potential generation circuit 21 is at a voltage level lower than the logic inversion threshold voltage. It is necessary to set to.

In the second specific example of FIG. 8, a detecting section 52 is provided in place of the detecting section 51 of the first specific example (FIG. 7). The detection signal MON2 and the enable signal EN are both low active signals, and when both input signals are low level, the low level signal is input to the enable (E) terminal of the oscillator 8 to activate the oscillator 8. Turn into.

The detection section 52 has a circuit configuration in which activation / deactivation is switched according to the enable signal EN. First
This is a configuration in which an NMOS transistor TN4 is added to the first stage circuit of the detection unit 51 of the specific example. NMOS transistor T
N4 is connected between the NMOS transistor TN3 and the output terminal of the first-stage circuit, and the enable signal EN is inverted by the inverter element I4 and input to the gate terminal. When the enable signal EN is at a low level and is in an active state, the NMOS transistor TN4 becomes conductive and the first-stage circuit is activated, so that the detection operation is performed. When the enable signal EN is at a high level and is inactive, the NMOS transistor TN4 is non-conductive and the detection operation is not performed. At the same time, there is no current consumption in the detector 52. The output terminal of the first-stage circuit is fixed to the power supply voltage VDD, and the detection operation is not performed.

FIG. 9 shows a specific example of the case where the delay unit is provided. The enable (E) terminal of the oscillating unit 8 is connected to the delay unit 6 by the NOR element NOR4 and the inverter element I3.
The logical sum of the signal from 1 and the enable signal EN is input. Here, when all the signals input to the NOR element NOR4 become low level, the low level signal is input to the enable (E) terminal of the oscillator 8 to activate the oscillator 8.

The delay section 61 comprises a first delay section D1 and a second delay section D2. The first delay unit D1 is
An even number of inverter elements (FIG. 9 illustrates a case of four stages) are connected in series. The second delay unit D2 constitutes a delay circuit that measures a predetermined delay time after the enable signal EN changes to low level. The enable signal EN is inverted by the inverter element and input to one input terminal of the NAND element NA1. A signal delayed by a predetermined delay time is input to the other input terminal via a delay unit τ including an inverter element, a CR delay element and the like. Here, the logic level between the input and output of the delay unit τ is inverted.

As a result, the output terminal logically inverted by the inverter element from the output of the NAND element NA1 has the pulse width of the predetermined delay time set by the delay unit τ with respect to the low level transition of the enable signal EN. A high-level pulse signal is obtained as the delay signal D.

Since there is a delay time on the circuit between the low level transition of the enable signal EN and the high level transition of the delay signal D, a low level hazard may occur from the inverter element I3. . The first delay unit D1 is provided as a countermeasure against this. That is, due to the delay signal from the first delay unit D1, the high level is input to at least one input terminal of the NOR element NOR4 during the delay time on the circuit from the low level transition of the enable signal EN, and the hazard is generated. Can be prevented.

As described above in detail, the detecting section 51,
With the configuration including 52, the voltage level of the control line VR is detected, and when the signal corresponding to the predetermined oscillation frequency is reached, the oscillation unit 8 is controlled to start the oscillation operation, or A signal can be output. When the control unit 71 or the first control unit 72 is activated by the activation of the enable signal EN, it is detected that the voltage level of the control line VR has not reached the voltage level equivalent to the oscillation frequency control signal VR. It is possible to prevent the output of an unstable oscillation frequency in the active state.

If the delay section 61 is provided,
A time period during which the oscillation frequency control signal VR output from the control unit 71 or the first control unit 72 stabilizes can be added as a predetermined delay time τ, and a stable oscillation signal after the time when the voltage level of the control line VR stabilizes. Can be obtained.

Further, here, the CR delay circuit or the like which constitutes the delay unit τ in the second delay section D2 is controlled by the control section 7
1, a resistance component such as a current system path of the bias current IC, IC1, or IC2 in the first control unit 72 or the second control unit 31, and a capacitance component such as a PMOS / NMOS transistor, a resistance element, and a wiring capacitance. By making it correspond to the time constant of the CR delay circuit configuration described above, the delay unit 61 can measure a time equivalent to the time until the voltage level of the control line VR reaches a stable state. Furthermore, by configuring the delay unit τ with a circuit configuration equivalent to that of the control unit 71, the first control unit 72, or the second control unit 31,
The time equivalent to the time until the voltage level of the control line VR reaches a stable state can be measured. As a result, the delay unit 31 can measure the predetermined delay time at the optimum timing.

In the third embodiment shown in FIG. 10, the oscillator 82 is used.
This is an example of a so-called voltage control type oscillator circuit 103 that controls the driving power supply voltage to set the oscillation frequency. The control unit 73 includes a resistor element array and a buffer circuit. The voltage at a predetermined position of the resistor element array is supplied as a driving power supply voltage for the oscillating unit 82 after adding driving capability to the buffer circuit. The resistor element array and the buffer circuit of the control unit 73 include NMOS transistors TN4 and TN.
5 are provided in the current paths of the resistor element array and the buffer circuit, respectively, and the enable signal EN is controlled by a signal logically inverted by the inverter element.

In the inactive state in which the enable signal EN is at a high level, the current path is cut off, the power supply to the oscillator 82 is stopped, and the oscillation operation is stopped. In the active state where the enable signal EN is at a low level, the current path is made conductive, the power is supplied to the oscillator 82, and the oscillation operation is performed.

The oscillator circuit 103 also has the preset section A1 or A2, so that the same operation and effect as those of the first or second embodiment can be obtained. Further, the detecting units 51 and 52 (FIGS. 7 and 8) or the delay unit 61 (FIG. 9) may be provided.

Next, FIGS. 11 and 12 show modifications of the control format of the oscillation frequency control signal VR. In the first or second embodiment, the bias current IC in the oscillator 810 is used.
Is a current control type oscillator circuit 101, 102 whose oscillation frequency is controlled by using as a driving power supply current. For these oscillator circuits 101 and 102, as the oscillation frequency control signal VR, the control unit 71 or the first control unit 72 converts the bias current IC or IC1 into a voltage value and propagates the control line VR to the oscillator unit. 8 is an example of a circuit configuration for reconverting into a driving power supply current and controlling in 810.

The first modification shown in FIG. 11 includes a controller 74 and an oscillator 83. The control unit 74 has a circuit configuration in which the PMOS transistor TP101 in the oscillation unit 810 of the first or second embodiment is incorporated in the control unit 71 or the first control unit 72, and a current mirror circuit including a PMOS transistor is used. The output of the bias current IC is supplied to the control line VR. The oscillating unit 83
This is a circuit configuration in which the PMOS transistor TP101 is removed from 0, and the bias current supplied from the control line VR is used as it is as a drive power supply current.

According to this structure, the controller 74 and the oscillator 8
Since the interface with 3 is a bias current IC, it is excellent in voltage noise resistance to the control line VR.

The second modification of FIG. 12 includes an oscillating section 84 instead of the oscillating section 83 of the first modification (FIG. 11).
The oscillating unit 84 is a circuit type controlled by a driving power supply voltage. The bias current IC propagating through the control line VR is converted into a voltage signal by the resistance element R. The converted voltage signal is supplied as a drive power supply voltage via the buffer circuit. The circuit form is suitable for ensuring the voltage noise resistance with respect to the control line VR by including the oscillating unit 84 in which the oscillation frequency is controlled by the drive power supply voltage.

Also in the first or second modified example, by providing the preset section A1 or A2, the same operation and effect as in the case of the first or second embodiment can be obtained. Further, the detecting units 51 and 52 (FIGS. 7 and 8) or the delay unit 61 (FIG. 9) may be provided.

In the third embodiment, for the voltage control type oscillator circuit whose oscillation frequency is controlled by the drive power supply voltage, the control unit 73 controls the drive power supply voltage as the oscillation frequency control signal VR. Here is an example.

By providing the semiconductor device 1000 (FIG. 13) and the semiconductor memory device 2000 (FIG. 14) with the oscillator circuit described above, the semiconductor device 1000 and the semiconductor memory device 2000 are provided with a voltage boosting / negative voltage generating circuit. In power supply circuit 200, a voltage corresponding to oscillation signal VOSC output from the oscillator circuit can be quickly and stably generated after activation by activation signal ACT.
Further, in the refresh control circuit 300, the refresh cycle according to the oscillation signal VOSC output from the oscillator circuit can be quickly and stably controlled after activation by the activation signal ACT.

As a result, the output period of the unstable oscillation signal VOSC when the operation is started by the activation signal ACT is minimized, and the unstable operation period of the boost / negative current circuit 200 or the refresh control circuit 300 is reduced. Is shortened, and stable circuit operation can be performed immediately after activation.

Specifically, the unstable high frequency oscillation signal VOSC is output, resulting in a large current consumption and a malfunction due to the voltage drop of the power supply voltage, or the semiconductor device 1000 due to excessive voltage generation. The reliability of the semiconductor memory device 2000 does not occur. On the contrary, the unstable low-frequency oscillation signal VOSC is output, which causes fluctuations in transistor characteristics and deterioration in noise resistance associated therewith, or the semiconductor memory device 20.
The loss of stored data at 00 does not occur.
Here, the transistor characteristic variation and the deterioration of noise resistance may be variation of the back gate bias voltage in the MOS transistor.

Needless to say, the present invention is not limited to the first to third embodiments, and various improvements and modifications can be made without departing from the spirit of the present invention. For example, the drive power supply current or drive power supply voltage to be controlled may be provided on the high power supply voltage side or the low power supply voltage side. Moreover, it is also possible to adopt a configuration provided on both the high power supply voltage side and the low power supply voltage side. Further, the control signal of the control line VR for controlling the oscillation frequency can be configured for each of the current signal and the voltage signal. The combination of the drive power supply current or drive power supply voltage and the control current or control voltage can be appropriately performed. In this case, it goes without saying that the circuit configurations of the control unit, the detection unit, etc. are appropriately changed depending on the insertion position of the drive power supply current or the drive power supply voltage. In addition, the logic level of the enable signal EN and the voltage level of the control line VR can be appropriately changed. Even in this case, it goes without saying that the logic levels of the control unit, the detection unit and the like can be appropriately changed and dealt with. In addition to the control for connecting / disconnecting the loop of the ring oscillator, the oscillation operation in the oscillating section is performed by connecting / disconnecting the output path of the oscillation signal VOSC in addition to this control. You can also do it. Although the oscillation frequency set by the oscillation frequency control signal VR is described as fixed, if the resistance element in the control unit is variable, the oscillation frequency control signal VR is set according to the resistance value.
The voltage level of can be made variable, and the oscillation frequency can be made variable. At this time, as the variable resistance, the ON resistance of the MOS transistor can be used by changing the bias to the gate terminal in addition to switching the resistance element. Further, although the case where the oscillator is configured by the ring oscillator has been described, the present invention is not limited to this, and performs an oscillating operation such as a bistable multivibrator or a method of repeatedly charging and discharging the capacitive component. Any circuit configuration can be applied regardless of the circuit system. Regarding the detection unit, the first
It is also possible to compare the signal output VR of the control unit and the signal output VR2 of the second control unit, and the detection signal from the detection unit can switch and control the switch unit.

(Supplementary Note 1) An oscillating section that oscillates at an oscillating frequency according to an oscillating frequency control signal, and the oscillating frequency control signal is output to the oscillating section through a control line when an oscillation enable signal is activated. A control unit; and a switch unit arranged between the signal generation circuit and the control line, which is conductive when the oscillation enable signal is inactive and supplies a predetermined signal from the signal generation circuit to the control line. Oscillator circuit. (Supplementary Note 2) An oscillation unit that oscillates at an oscillation frequency according to an oscillation frequency control signal, and a first control that outputs the oscillation frequency control signal to the oscillation unit through a control line by activating an oscillation permission signal. A pulse generator that outputs a pulse signal when the oscillation enable signal is activated, and a second pulse generator that is activated by the pulse signal and outputs a predetermined signal
An oscillator circuit, comprising: a control unit; and a switch unit which is arranged between the second control unit and the control line and which conducts by the pulse signal and supplies the predetermined signal to the control line. . (Supplementary Note 3) The oscillator circuit according to Supplementary Note 1 or 2, wherein the predetermined signal is a signal equivalent to the oscillation frequency control signal. (Supplementary Note 4) The oscillator circuit according to Supplementary Note 2, wherein the output drive capability of the second controller is larger than the output drive capability of the first controller. (Supplementary Note 5) The oscillator circuit according to Supplementary Note 2, wherein the first control unit and the second control unit have equivalent circuit configurations configured by equivalent circuit elements. (Supplementary note 6) The oscillator circuit according to Supplementary note 2, wherein the pulse signal is continued until the predetermined oscillation frequency control signal is output from the first control unit. (Supplementary Note 7) The oscillation frequency of the oscillator is controlled by a drive power supply current, and the oscillation frequency control signal is the drive power supply current or controls a current source for supplying the drive power supply current. 3. The oscillator circuit according to appendix 1 or 2, which is a current signal or a voltage signal. (Supplementary Note 8) The oscillation frequency of the oscillation unit is controlled by a drive power supply voltage, and the oscillation frequency control signal is the drive power supply voltage or controls a voltage source for supplying the drive power supply voltage. 3. The oscillator circuit according to appendix 1 or 2, which is a current signal or a voltage signal. (Supplementary Note 9) The oscillator circuit according to Supplementary Note 1 or 2, further comprising a detection unit that controls the oscillation unit according to a detection signal obtained by detecting a signal on the control line. (Supplementary Note 10) The oscillator circuit according to Supplementary Note 9, wherein the detection unit includes a comparison unit that compares the signal on the control line with a signal equivalent to the oscillation frequency control signal. (Additional remark 11) The signal of the control line is an analog voltage value, and the comparison unit includes a logic gate element whose threshold voltage is a signal equivalent to the oscillation frequency control signal. Oscillator circuit. (Additional remark 12) The said detection part is activated by activation of the said oscillation permission signal, The oscillator circuit of Additional remark 9 characterized by the above-mentioned. (Supplementary Note 13) The oscillator circuit according to Supplementary Note 1 or 2, further comprising: a delay unit that outputs a delay signal obtained by adding a predetermined delay time to the oscillation enable signal to control the oscillation unit. (Supplementary Note 14) The predetermined delay time is at least a time until the signal on the control line reaches a signal equivalent to the oscillation frequency control signal due to activation of the oscillation enable signal. 13. The oscillator circuit according to item 13. (Supplementary Note 15) The oscillator circuit according to Supplementary Note 13, wherein the delay unit has an equivalent circuit configuration configured by a circuit element equivalent to that of the control unit or the first control unit. (Supplementary Note 16) A semiconductor comprising: the oscillator circuit according to at least any one of Supplementary Notes 1 to 15; and a voltage generation circuit that generates a voltage in response to an oscillation signal output from the oscillator circuit. apparatus. (Supplementary Note 17) The voltage generation circuit is a booster circuit,
17. The semiconductor device according to Appendix 16, which generates a boosted voltage according to the oscillation signal. (Supplementary Note 18) The semiconductor device according to Supplementary Note 16, wherein the voltage generation circuit is a negative voltage generation circuit and generates a negative voltage according to the oscillation signal. (Supplementary Note 19) A semiconductor, comprising: the oscillator circuit according to any one of Supplementary Notes 1 to 15; and a voltage generation circuit that generates a voltage in response to an oscillation signal output from the oscillator circuit. Storage device. (Supplementary Note 20) The voltage generation circuit is a booster circuit,
20. The semiconductor memory device according to appendix 19, wherein a boosted voltage is generated according to the oscillation signal. (Supplementary Note 21) The semiconductor memory device according to Supplementary Note 19, wherein the voltage generation circuit is a negative voltage generation circuit and generates a negative voltage according to the oscillation signal. (Supplementary Note 22) The oscillator circuit according to at least one of Supplementary Notes 1 to 15, and a refresh control circuit that controls a refresh cycle in response to an oscillation signal output from the oscillator circuit. Semiconductor memory device. (Supplementary Note 23) When the oscillation operation is performed in response to the oscillation frequency control signal, the oscillation frequency control operation is activated by the activation of the oscillation enable signal, and the control state shifts to a preset setting state. A method of controlling an oscillator circuit in which the oscillation frequency shifts to a set value according to
A method of controlling an oscillator circuit, wherein the control state is maintained in a predetermined state by a signal from a signal generator when the oscillation enable signal is inactive. (Supplementary Note 24) When the oscillation operation is performed in response to the oscillation frequency control signal, the first control operation of the oscillation frequency is activated by activation of the oscillation permission signal, and the control state shifts to a preset setting state. A method of controlling an oscillator circuit in which the oscillation frequency shifts to a set value by going a predetermined period after the oscillation enable signal is activated,
A method of controlling an oscillator circuit, wherein a second control operation for shifting the control state to a predetermined state is activated. (Supplementary Note 25) The method of controlling an oscillator circuit according to Supplementary Note 23 or 24, wherein the predetermined state is a state equivalent to the set state. (Supplementary note 26) The control method of the oscillator circuit according to supplementary note 24, wherein the ability to shift to the predetermined state by the second control operation is larger than the ability to shift to the setting state by the first control state.

[0120]

According to the present invention, the transient instability period of the oscillation frequency at the start of oscillation of the oscillator circuit whose operation and stop can be controlled is shortened, and the oscillation frequency is stable immediately after the start of oscillation. It is possible to provide an oscillator circuit capable of outputting an oscillation signal, a semiconductor device including the oscillator circuit, a semiconductor memory device including the oscillator circuit, and a method for controlling the oscillator circuit.

[Brief description of drawings]

FIG. 1 is a first principle diagram of the present invention.

FIG. 2 is a second principle diagram of the present invention.

FIG. 3 is a circuit diagram of the first embodiment.

FIG. 4 is an operation waveform diagram of the first embodiment.

FIG. 5 is a circuit diagram of a second embodiment.

FIG. 6 is an operation waveform diagram of the second embodiment.

FIG. 7 is a circuit diagram showing a first specific example in the case of including a detection unit.

FIG. 8 is a circuit diagram showing a second specific example in the case of including a detection unit.

FIG. 9 is a circuit diagram showing a specific example in the case of including a delay unit.

FIG. 10 is a circuit diagram of a third embodiment.

FIG. 11 is a circuit diagram showing a first modification of the embodiment.

FIG. 12 is a circuit diagram showing a second modification of the embodiment.

FIG. 13 is a circuit block diagram showing a semiconductor device including an oscillator circuit.

FIG. 14 is a circuit block diagram showing a semiconductor memory device including an oscillator circuit.

FIG. 15 is a circuit block diagram of a conventional technique.

FIG. 16 is a circuit diagram showing a first specific example of a first conventional technique.

FIG. 17 is a circuit diagram showing a second specific example of the first conventional technique.

FIG. 18 is an operation waveform diagram of first and second specific examples of the first conventional technique.

FIG. 19 is a circuit diagram showing a third specific example of the first conventional technique.

FIG. 20 is an operation waveform diagram of a third specific example of the first conventional technology.

FIG. 21 is a circuit diagram of a second conventional technique.

FIG. 22 is an operation waveform diagram of the second conventional technique.

[Explanation of symbols]

1, 11 Switch unit 2 Signal generating unit 21 Potential generating unit 3, 31 Second
Control unit 4, 41 Pulse generation unit 5, 51, 52 Detection unit 6, 61 Delay unit 7, 71, 73, 74, 720, 740 Control unit 7, 72 First
Control unit 8, 82, 83, 84, 810, 830, 910 Oscillation unit 920 Pulse generation unit 100, 101, 102, 103 Oscillator circuit 200 Boost / negative power supply circuit 300 Refresh control circuit 1000 Semiconductor device 2000 Semiconductor memory device A1, A2 , A11 preset part VR control line EN enable signal IC, IC1, IC2 bias current MON, MON1, MON2 detection signal SET pulse signal VOSC oscillation signal VR oscillation frequency control signal

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Satoru Kawamoto             1844-2 Kozoji-cho, Kasugai-shi, Aichi             Within Fujitsu VIS Ltd. F-term (reference) 5J043 AA13 AA26 EE01 LL01 MM00

Claims (9)

[Claims] 1. An oscillating section that oscillates at an oscillating frequency according to an oscillating frequency control signal, and a control section that outputs the oscillating frequency control signal to the oscillating section via a control line when an oscillation enable signal is activated. And a switch unit arranged between the signal generation circuit and the control line, which conducts when the oscillation enable signal is inactive and supplies a predetermined signal from the signal generation circuit to the control line. And the oscillator circuit. 2. An oscillating section that oscillates at an oscillating frequency according to an oscillating frequency control signal, and a first output section that outputs the oscillating frequency control signal to the oscillating section via a control line by activating an oscillation enable signal. A controller, a pulse generator that outputs a pulse signal when the oscillation enable signal is activated, a second controller that is activated by the pulse signal and outputs a predetermined signal, and the second controller. An oscillator circuit, comprising: a switch unit arranged between the control line and the switch line, the switch unit being conductive by the pulse signal and supplying the predetermined signal to the control line. 3. The oscillator circuit according to claim 1, further comprising a detector that controls the oscillator according to a detection signal obtained by detecting the signal on the control line. 4. The oscillator circuit according to claim 1, further comprising a delay unit that outputs a delay signal obtained by adding a predetermined delay time to the oscillation enable signal to control the oscillation unit. . 5. The oscillator circuit according to claim 1, further comprising a voltage generation circuit that generates a voltage in response to an oscillation signal output from the oscillator circuit. Semiconductor device. 6. The oscillator circuit according to claim 1, further comprising: a voltage generating circuit that generates a voltage in response to an oscillation signal output from the oscillator circuit. Semiconductor memory device. 7. An oscillator circuit according to any one of claims 1 to 4, and a refresh control circuit for controlling a refresh cycle in response to an oscillation signal output from the oscillator circuit. And semiconductor memory device. 8. When the oscillation operation is performed in response to the oscillation frequency control signal, the oscillation frequency control operation is activated by activation of the oscillation permission signal, and the control state shifts to a preset setting state. A method of controlling an oscillator circuit in which the oscillation frequency shifts to a set value by
A method of controlling an oscillator circuit, wherein the control state is maintained in a predetermined state by a signal from a signal generator when the oscillation enable signal is inactive. 9. When the oscillation operation is performed in response to the oscillation frequency control signal, the first control operation of the oscillation frequency is activated by activation of the oscillation enable signal, and the control state shifts to a preset setting state. A method of controlling an oscillator circuit in which the oscillation frequency shifts to a set value by going forward, a predetermined period after the oscillation enable signal is activated,
A method of controlling an oscillator circuit, wherein a second control operation for shifting the control state to a predetermined state is activated.