JP2002058236A - Charge pump, dynamic regulator, and method of generating clock signal for use in charge pump - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low-power and high-speed dynamic regulation system. SOLUTION: A charge pump includes an input node which is coupled with a power source so as to receive input voltage, and an oscillator unit which generates a cyclic regulator enabling signal and a cyclic reset signal. A regulator clock unit is coupled with the oscillator unit, and it generates a precharge(PC) signal and a regulator reset signal, in answer to the regulator enabling signal, and a pump clock unit generates a plurality of pump clock signal, receiving a master clock signal, and a charge pump unit is coupled with the input node, and is controlled operably by a plurality of pump clock signals, and is coupled with an output terminal so as to generate an output signal (VPUMP), and a regulator unit is coupled so that it may receive the VPUMP signal, the PC signal, the reference signal, and the regulator enabling signal, and it operates in precharge mode or regulation mode, in answer to the regulator enabling signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates generally to integrated circuits, and more particularly, to an integrated circuit having a charge pump circuit that generates a power supply voltage from an external power supply voltage.

[0002]

2. Description of the Related Art Electronic systems typically include ICs manufactured by various techniques. Thus, it is necessary to supply multiple power supply voltages to a single printed circuit board to support various types of devices on a single printed circuit board. Standard IC voltages required in typical devices range from 5.0 volts to 3.3 volts, or lower. However, there are some devices that require power supply at various voltages in addition to the standard available voltage. Such devices often include data communication circuits that require a negative voltage, and +/-
Includes an interface circuit such as an RS232 interface that specifies a voltage in the range of 25V. Moreover, some ICs have different voltage requirements internally despite receiving power at industry standard power levels. The ability to generate a wide range of voltage levels, including negative voltages and voltages greater than the supplied voltage, provides great flexibility to circuit designers. In addition, higher voltage levels often allow faster switching and higher performance.

A practical solution to this imbalance is to provide a DC / DC converter circuit that changes the input DC voltage to a higher or lower DC voltage required by other devices. The negative charge pump operates to generate a negative voltage by charging the pump capacitor to the level of the power supply voltage during the first half cycle of the clock. During the second half cycle, the pump capacitor is disconnected from the power supply and switched in polarity and coupled to the storage capacitor, thereby pumping charge to the storage capacitor and providing an output that is substantially negative of the input voltage.

A more positive charge pump would operate to generate a voltage higher than the supply voltage by coupling the pump capacitor to the supply voltage during the first half cycle (ie, "step-up"). "converter). During the second half cycle, the positive terminal of the pump capacitor is disconnected from the supply voltage, and the negative terminal of the capacitor is instead coupled to the supply voltage. The positive terminal of the pump capacitor is then coupled to the storage capacitor, charging the storage capacitor to about twice the supply voltage.

[0005] Larger high power charge pumps operate at lower frequencies than normal and are not optimized in terms of size. The size of the large low frequency charge pump may be a limiting factor in trying to get the smallest possible IC chip. It is desirable to make the on-chip charge pump as small as possible, especially when the charge pump occupies a significant area of the chip. In order to obtain the target output current, the smaller the size of the charge pump, the higher the operating frequency must be in proportion thereto. Typically, for high current output (e.g., greater than 5-10 milliamp) charge pumps, the operating frequency of the pump is determined by the peak operating current and the rate of change of operating current (di / dt), and the driver and support circuitry. Determined by size.

One of the problems with higher frequency charge pumps
First, adjusting the output voltage level is more difficult because multiple cycles are required to turn the charge pump on and off, which may result in undesirable hysteresis. Charge pumps whose output capacity per pump cycle is large compared to the load it drives can change the voltage across the load by an appreciable amount. In this case, it is unacceptable to wait for more than one pump cycle after reaching the regulation point before turning the charge pump on or off.

To solve this problem, a direct current (d.
c. 2.) A fast and high power regulation method utilizing a differential amplifier is used. In this solution, a small portion of the beginning of a pump cycle is used to sense if the voltage across the load is at or below the reference level. If the voltage is lower, the pump is started. If the voltage is higher, no pumping takes place. As the operating frequency approaches 30 Mhz (33 ns period), about 20% of each clock cycle (ie, 7n
A shorter period than s) could be used for adjustment. A fast adjustment scheme can be achieved, but in this situation,
Most of the allocated charge pump current is used for regulation. High speed d. c. When using the differential adjustment scheme, power consumption becomes a problem.

[0008] The operation can be further complicated if a high frequency charge pump is implemented in an IC using active and standby modes. Even though power consumption during the active mode is acceptable, power consumption by the charge pump during the standby mode could still be a problem. Typically, the standby mode requires much lower power consumption, but again at least at some point the charge pump must be operational. Saving power is the purpose of the standby mode, but to save power, it is desirable to turn off the high powered regulator circuit when not in use. When still in standby mode, the high powered regulation circuit must be turned on and stabilized before entering a pump cycle that requires more complex control and timing circuits. Power is consumed during this stabilization time, and there is a high possibility that the power consumption specification during standby will increase.

Another approach to reducing power consumption during standby is to completely turn off the high powered regulator and instead use a very low power regulator that is always on. In this approach, the low power regulator takes some time to make the decision, so critical circuitry is needed to ensure that multiple or partial pumps do not occur. In another variation, the low power, low output current pump comprises:
Operable during the standby mode, with slow turn-on or turn-off, the output voltage will have little hysteresis. All of these conventional solutions require more circuitry and complex control logic.

[0010]

SUMMARY OF THE INVENTION The present invention is directed to a dynamic regulation system that is both low power and high speed. The regulator according to the present invention has a small device that compares the reference voltage to the input signal and is clocked to transition the internal regulator node to the power rail voltage quickly. Once the internal nodes are at the power rail voltage, little power is consumed. According to the invention, the load from the following circuits is kept at a minimum,
Small devices can be used to implement the internal regulator circuit. The smaller device allows the regulator according to the invention to be faster and consume less power. Although this embodiment relates to a positive charge pump, all of the techniques described are applicable to negative charge pumps.

Briefly stated, the present invention relates to a charge pump that includes an input node coupled to receive an input voltage from a voltage source, and an oscillator unit that generates a periodic regulator enable signal and a periodic reset signal. A regulator clock unit is coupled to the oscillator unit and generates a precharge (PC) signal and a regulator reset signal in response to the regulator enable signal. A pump clock unit receives the master clock signal and generates a plurality of pump clock signals.
A charge pump unit is coupled to the input node and is operatively controlled by the plurality of pump clock signals and is coupled to an output terminal coupled to generate an output signal (V _PUMP ). The regulator unit uses V _PUMP signal, PC
A signal, a reference signal, and a regulator enable signal are coupled, and the regulator unit operates in either a precharge mode or a regulation mode in response to the regulator enable signal.

In another aspect, the invention relates to a method of adjusting a charge pump wherein the dynamic regulator is disabled in a precharged or "fire ready" state. In this standby state, the dynamic regulator is shut down and essentially consumes no power. The internal nodes of the regulator are decoupled from the power supply so that no power is dissipated, but remain connected to the reference voltage and the input signal. Prior to the transition from the standby state to the enabled state, the internal node of the dynamic regulator has already had another precharge to avoid the inconvenience of the latency required to slew the internal node to the appropriate level. At the level that was done. Immediately after the transition to the enable state, the dynamic regulator is clocked without delay.

[0013]

DETAILED DESCRIPTION FIG. 1 shows, in block diagram form, a voltage upconverter according to the present invention. The electronic system is shown in FIG.
Are usefully represented as a collection of interacting functional units as shown in FIG. Oscillator 102 is enabled by an externally generated ENABLE signal. Oscillator 102
Outputs a regulator enable (ENREG) signal,
This signal is coupled to regulator clock unit 104 and regulator unit 106. ENRE
The G signal is used by the regulator clock unit 104 to derive a precharge (PC) signal and a regulator reset (RSTREG) signal, which are combined with the regulator unit 106.

The regulator clock unit 104 includes:
As described in further detail below, when the ENREG signal is low (ie, disabled), the PC signal from the regulator clock unit 104 goes high and operates to precharge the dynamic regulator unit 106. . Further, in the regulator unit 106, the regulator unit 106
With the sensitive reference voltage (V _REF ) and the signal voltage (V
_The ENREG signal is used to isolate from the _PUMP ) nodes, so that these sensitive nodes are not electrically disturbed during the amplification and latching process. In response (or synchronously) to the transition of the PC signal to a high state to precharge the regulator unit 106 for the next cycle, the regulator clock unit 1
04 generated by the regulator reset signal (RS
TREG) causes a low pulse to reset the regulator unit 106.

After ENREG transitions to a high state (ie, the enabled state), to stop the precharge and "clock" regulator unit 106 on all subsequent cycles in which the charge pump is enabled (see FIG. 4). The regulator clock unit 1 to quickly generate a low pulse on the PC signal (as shown)
04 is operable. The “clocking” regulator unit 106 provides the dynamic regulator V _REF
It is intended to amplify and latch the difference between the input and the V _PUMP input. The latched difference signal is processed (as described in more detail with reference to FIG. 2) to generate a master clock (MCLK) signal. The MCLK signal is used by the pump clock unit 108 to generate all the clocks needed to drive the charge pump unit 110. A detailed understanding of the operation and implementation of pump clock circuit 108 and charge pump circuit 110 is not necessary for understanding the present invention. Accordingly, these details are not provided to facilitate illustration and understanding of the invention.

FIG. 2 shows a regulator unit 106 including a dynamic regulator circuit 200 according to the present invention.
Is shown in more detail in a mixed schematic / block diagram. One of the inputs to the dynamic regulator 200 may be the pumped output V _{PU MP} itself.
More typically, a divided version of V _PUMP generated by voltage divider unit 202 is used. The V _REF input to dynamic regulator 200 includes a reference voltage generated by reference unit 204 that is compared to V _PUMP . In the example of FIG. 2, V _PUMP is divided by the voltage divider unit 202 and the regulator unit 106
Is operated near the positive power supply voltage. In this manner, V _REF can be provided by the positive supply voltage itself, eliminating the need for an additional reference voltage generator circuit.

However, it should be understood that V _REF need not be at the positive power supply, and that this particular example would readily apply to other reference voltage techniques. For example, V _REF
And such that V _PUMP to operate with a negative or near the power supply level to the regulator unit 106, are readily available complementary circuit. Other circuits are available for the inputs to operate at selected levels between the positive and negative power supplies. These and similar alternatives are equivalent to the specific examples shown here.

Regulator unit 106 generates an MCLK signal when the divided level of V _PUMP is below V _{REF and} operates to indicate that V _PUMP is below a desired voltage. If V _PUMP is at an appropriate level (ie V
_REF ), no MCLK is generated. The dynamic regulator 200 is connected to the node 21
4 includes a pair of cross-coupled inverters forming a latch 212 coupled to a load 228. Nodes 216 and 218 form the inverted and non-inverted outputs of latch 212. Load 228 includes a resistor-capacitor (RC) circuit that is easily implemented using conventional passive or active devices.

Regulator unit 106 includes a power supply node coupled to a V _CC power source or other available external power source. Node 214 serves as a power supply return node that completes the current flow path from the V _CC power source through regulator unit 106 to ground (or any available return current path to the V _CC power source). Load 2
28 is coupled with the return node 214 to prevent the node 214 from floating, but provides sufficient impedance so that the voltage on the node 214 is increased by the precharge device 222 and the clocked devices 226 and 23.
4 can be controlled. Manipulation of the voltage on node 214 causes node 21 to disable latch 212.
4 can be maintained at a voltage close enough to V _CC to operate the latch 212 in the sense mode, and
Can be operated in a latch mode in which the latch 212 is held at ground and the latch 212 is enabled.

The dynamic regulator 200 further includes
The precharge device 222 and the clock device 22
6 and 234. The precharge device 222
Regulator clock unit 104 (shown in FIG. 1)
It is controlled by these PC signals. Switch 207 and
209 responds to the RSTREG signal, and
216 and 218 to V_CCPrecharge to. Hope
Preferably, output nodes 216 and 218 are respectively
Switches 206 and 208 provide V_PUMPAnd V _REF
Can be controllably decoupled or separated from. Switch 20
6 and 208 are based on the ENREG signal described below.
Is controlled.

The PC signal is passed through an inverter 224
Coupled to generate a sense (SEN) signal that controls the clocking device 226. The SEN signal is coupled to generate a SET signal that controls a clocking device 234 through a first delay unit 232. Delay unit 232 is conveniently implemented as two serially coupled inverters to provide a difference between the SEN and SET signals corresponding to the delay of the two gates,
Any available delay technique may be used to implement delay 232. The SET signal is output to the second delay unit 23
6 to the deglitch unit 242 (LA)
T) coupled to generate a signal.

As shown in FIG. 2, inverted output 216 and non-inverted output 218 of latch 212 are coupled to deglitch unit 242. The deglitched signal from the deglitch unit 242 is the master clock signal (MC
LK) is coupled to the set input of output latch 244. Latch 244 may be reset by the application of an external RSTMCLKB signal to the reset input of latch 244.

In a specific example, ENREG is
It operates at about 30 Mhz with about 50% duty cycle as shown in FIG. During operation, ENREG signal is low (steady state)
, The PC signal is high and SE (shown in FIG. 5)
N, SET and LAT are low. Furthermore, ENR
Immediately after EG goes low, RSTMCLKB produces a low pulse, and immediately after PC goes high, RSTRECLKB goes low.
GB produces a low pulse and returns high. The combination of these signals in the state described above puts regulator unit 106 into a precharge mode. Regulator unit 106 is in the precharge mode during standby and during the low time of the ENREG cycle. When ENREG is low, the divided V _PUMP signal shown in FIG. 4 is coupled to latch 212 through device 206 and the reference input V _REF is coupled to latch 212 through device 208. Since the RSTREGB signal produces an earlier low pulse, both nodes 216 and 218 are substantially precharged to V _CC .
A high PC signal turns on the precharge device 222,
Clock devices 226 and 234 remain off.

The precharge device 222 preferably comprises
Provided as a minimum length n-channel transistor. This
In the state of FIG._CCMinimum length n lower than
Settling to a voltage substantially equal to the channel threshold.
This voltage on node 214 in latch 212 (FIG.
Turn off the inverter). In a specific implementation
In other words, the inverter in the latch 212
And node 218 is at V _CCIn the latch 212 when near
Inverters turn off (that is, do not pass current)
Thus, it is realized with a non-minimum length transistor. in this way
And nodes 216 and 218_CCAnd no
Node 214 and nodes 216 and 2
The only effect 18 will have on devices 206 and 208
These are the inputs to them.

FIG. 3 illustrates a preferred implementation of the deglitch unit 242 and latch 244 to reduce standby power usage. As shown in FIG.
And when node 218 is near V _CC (ie, the precharge state described above), node 302 is high and node 304 is low. Both low and low LAT signals at node 304 will turn off devices 306 and 310, and there will be no current path even if device 312 is on while RSTMCLKB is low. The input to the cross-coupled inverter 314 is therefore high and the generated MCLK signal is low. Thus, while the regulator unit 106 is in the precharge mode, there is no current path and the dynamic regulator 200 continuously samples the V _PUMP (or divided V _PUMP ) and V _REF inputs and the PC signal goes low. Ready to make adjustments as soon as they become available.

FIG. 5 shows two cycles, a first cycle without MCLK firing and a second cycle with MCLK firing. When the charge pump according to the present invention is enabled, ENREG goes high and the device 206 shown in FIG.
And 208 are turned off, maintaining the V _PUMP (or divided V _PUMP ) and V _REF input voltages on nodes 216 and 218. The PC immediately issues a low pulse, turns off the precharge device 222 and SEN goes high, turning on the clock device 226. In a specific example,
Clock device 226 is smaller than clock device 234. As node 214 is coupled to load 228, node 214 begins to slowly slew to ground from a voltage equal to the minimum length N-channel threshold below V _CC .

In a particular embodiment, clocking of dynamic regulator 106 includes two stages.
That is, the first stage slowly amplifies the difference between the inputs, and after a short delay, the second stage quickly latches the regulator in a state that reflects the state of the inputs. In one embodiment, this two-stage clocking is performed directly in regulator unit 106. During clocking, when a difference exists between nodes 216 and 218, node 214 slews low and latch 21
2 will start lowering the voltage of either node 216 or node 218. Specifically, if node 2
If 16 started below node 218,
Node 216 slews low. Similarly, if node 218 started below node 216, node 218 would initially slew low. Eventually, latch 212 causes the initially higher node to slew to VCC. Then, the nodes 216 and 218 advance in the opposite directions, and the SET signal becomes S
Going high after a delay time from EN, turns on the relatively larger clock device 234, causing output nodes 216 and 218 of latch 212 to quickly slew to their set values. Clock device 226 and clock device 23
A magnitude difference between 4 and 4 gives different slewing speed characteristics according to the invention.

Nodes 216 and 218 can both be characterized as starting high, with only one node going low and the side remaining high glitching low momentarily. The circuit shown in FIG.
6 and 218 teglitch unit 24 used to compensate for a momentary low drop
2 is realized. As mentioned earlier, both nodes 216 and 218 start high, with node 302 high and 304 low. Further, the input is the node 21
An inverter 316, which is six, is provided with a very low switching point (determined by the relative transistor size), while inverter 318 has a switching point below V _CC / 2. If node 216 goes low, node 304 goes high and node 21 goes high.
8 will experience a low glitch, but not less than V _CC / 2, so node 302 remains high. When LAT goes high after the delay time of SET, the input to cross-coupled inverter 314 is pulled low. MCLK is then set to allow the clock signal generated by pump clock unit 108 (shown in FIG. 1) to fire and drive charge pump 110.

However, if node 216 remains high but glitches low momentarily, inverter 316
Node 304 remains low on the non-glitch side below the switching point of. Node 218 goes low, and node 302 follows. When LAT goes high, both devices 306 and 308 are off,
The input to inverter 314 remains high and MCL
The generation of the K signal is prevented. If 216 and 218 start equal to each other, nodes 216 and 218 may both glitch very low first beyond the switching point of inverter 318 and secondly possibly beyond the switching point of inverter 316. It must be noted that The priority of the deglitch circuit is to not generate MCLK, so that under conditions in which both nodes 216 and 218 glitch low, inverter 318 will precede inverter 316 with node 302.
Will be brought low first, possibly causing node 304 to go high. The condition that node 302 is low and possibly node 304 is high will not cause an MCLK pulse. At some point, dynamic regulator 200 must make a decision and either node 216 or node 21
One of the eight must return high. If node 216 returns high, node 304 goes low and no MCLK pulse occurs when LAT fires, but if node 218 returns high, node 302 returns high and node 218 returns high. 304 is already high and generates a complete MCLK pulse. According to the deglitch method, no substantial MCLK pulse is generated.

In a particular example, MCLK can fire within about 7 ns after ENREG goes high so that regulation can begin. Thus, the method and apparatus according to the present invention are efficient as well as fast in that they use less power in standby. Further, the preferred implementation uses a small device that switches quickly, and consumes substantially no power once nodes 216 and 218 have transitioned to a power supply level. Thus, the regulator according to the present invention is efficient when active and when switched from standby to active.

Although the present invention has been described and illustrated with certain specificity, this disclosure is given by way of example only and departs from the spirit and scope of the invention as set forth in the appended claims. Rather, it should be understood by those skilled in the art that various changes in the combination and arrangement of parts may be envisioned.

[Brief description of the drawings]

FIG. 1 is a block diagram of a part of the present invention.

FIG. 2 is a diagram showing the regulator unit of the system shown in FIG. 1 in further detail in combination with a block diagram and a schematic diagram.

3 is a more detailed schematic diagram of the deglitch and MCLK latch portions of the regulator unit of FIG. 2;

FIG. 4 is an exemplary waveform chart showing the operation of the circuits shown in FIGS. 1 and 2;

FIG. 5 is another exemplary waveform chart showing the operation of the circuits shown in FIGS. 1 and 2;

[Explanation of symbols]

102 oscillator, 104 regulator clock unit, 106 regulator unit, 108 pump clock unit, 110 charge pump unit.

Continuation of the front page (72) Inventor Ryan Ti Hirose 80909 Colorado, Colorado Springs, St. Andrews Court, 4086 F-term (reference) 5F038 BG05 DF08 EZ20 5H730 AS04 BB02 DD04

Claims (18)

[Claims] 1. A charge pump, comprising: an input node coupled to receive an input voltage from a voltage source; an oscillator unit for generating a periodic regulator enable signal and a periodic reset signal; A regulator clock unit for generating a precharge (PC) signal and a regulator reset signal in response to a regulator enable signal; a pump clock unit for receiving a master clock signal and generating a plurality of pump clock signals; is operatively controlled by the plurality of pump clock signal, a charge pump unit coupled to an output terminal coupled to produce an output signal (V _pUMP), a reference unit for generating a reference signal, V _pUMP signal, PC signal, reference signal and regulator enable signal And a regulator unit operative to operate in either a precharge mode or a regulation mode in response to a regulator enable signal. 2. The charge pump according to claim 1, wherein the regulator unit precharges an internal regulator node in response to a PC signal during a precharge mode. 3. The charge pump according to claim 1, wherein the regulator unit further generates a master clock signal in response to a magnitude difference between the reference signal and the V _PUMP signal. 4. The apparatus of claim 1, further comprising a first isolation switch coupled between the V _PUMP signal and the regulator unit for selectively isolating the regulator unit from the V _PUMP signal in response to the regulator enable signal. Charge pump as described. 5. The system of claim 3, further comprising a second isolation switch coupled between the reference signal and the regulator unit for selectively isolating the regulator unit from the reference signal in response to the regulator enable signal. Charge pump. 6. The PC signal changes state after the regulator enable signal changes state to initiate a precharge mode.
The charge pump of claim 1, wherein the charge pump changes state to precharge an internal regulator node. 7. The charge of claim 1, wherein the regulator unit is further responsive to a regulator reset signal during a precharge mode, coupling the internal regulator node to a voltage source having a magnitude substantially equal to the reference signal. pump. 8. The regulator unit further includes: a power supply node coupled to an external power supply voltage; a power supply return node; and an operably controlled PC signal, coupling the power supply return node to a voltage substantially equal to the external power supply voltage. The charge pump of claim 1, further comprising: a first switch that is operatively controlled by the PC signal; and a second switch that is operatively controlled by the PC signal and that couples the power return node to ground. 9. A delay unit coupled to receive the PC signal and generating a delayed PC signal; and a third switch operatively controlled by the delayed PC signal and coupling the power return node to ground. The charge pump according to claim 8, further comprising: 10. The charge pump according to claim 9, wherein the third switch is larger than the second switch. 11. A dynamic regulator for generating a clock pulse for use in a charge pump unit, said dynamic regulator being coupled to a first input node coupled to an output node of the charge pump, and to a reference signal. A second input node, a first supply node coupled to a voltage source, a second supply node, a first signal node coupled to the first input node, and a second input node. A latch having a second signal node coupled thereto; and a load coupling the second supply node to ground, the load having a characteristic time constant; and the dynamic regulator further comprising a second supply node. And a precharge unit receiving a precharge control signal, the precharge unit connecting the second supply node to a voltage source. Binds selectively to return node, the dynamic regulator. 12. The precharge unit is further responsive to a precharge control signal to selectively couple the second supply node to a voltage selected to prevent the latch from latching. The dynamic regulator of claim 11, comprising a first switch. 13. The precharge unit is further operably controlled by a precharge control signal and includes a first current node coupled to a voltage source and a second current node coupled to a second supply node. The dynamic regulator according to claim 11, further comprising a first switch having the first switch. 14. The precharge unit is further operably controlled by a precharge control signal, and further comprising:
A first switch coupling the supply node to ground, a delay unit coupled to receive the precharge signal and generating a delayed precharge signal, operably controlled by the delayed precharge control signal; A second switch coupling the second supply node to ground. 15. The dynamic regulator according to claim 14, wherein the second switch has a lower on-resistance than the first switch. 16. A first isolation switch coupled between a first input node and a first signal node for selectively isolating a latch from the first input node, the first isolation switch comprising: The dynamic regulator of claim 11, wherein the switch is operably controlled by an external regulator enable signal. 17. A second isolation switch coupled between a second input node and a second signal node for selectively isolating a latch from the second input node, the second isolation switch comprising: 17. The charge pump of claim 16, wherein the switch is operatively controlled by an external regulator enable signal. 18. A method for generating a clock signal for use in a charge pump device, the method comprising: a regulator coupled to sense a reference voltage, a charge pump output voltage, and a periodic enable signal. Providing the regulator; precharging the regulator; precharging the internal node of the regulator during the precharge state; placing the regulator in a standby state; and connecting the internal node of the regulator during the standby state. Decoupling from the power supply, coupling the internal node of the regulator to the reference voltage and the charge pump output voltage during the standby state, placing the regulator in the enabled state, and transitioning to the enabled state. Immediately after, the dynamic regulator And generating a clock signal with a clock, the method.