JP2003330407A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stop the operation of an address driver circuit of a plasma display device when abnormality of the circuit occurs. <P>SOLUTION: The device consists of an electric power recovering circuit 20 which is arranged between an address driver circuit 11 and a power supply and recovers electric energy from a plasma display panel in accordance with the display operation of the panel, a middle point voltage detecting circuit 21 which detects a middle point voltage of the circuit 20, two reference voltage generating circuits 22 and 23 which are connected to the power supply and generate voltages having different voltage values, two voltage comparing circuits 24 and 25 which are respectively connected to the circuit 21 and the circuits 22 and 23 and a microcomputer 26 which controls electric discharging control operations by the signals outputted from the circuits 24 and 25. Having provided the constitution above, the operation of a display driving circuit is stopped when abnormality is occurred. <P>COPYRIGHT: (C)2004,JPO

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large screen,
The present invention relates to a plasma display device known as a lightweight display device. 2. Description of the Related Art A plasma display device can display at a higher speed and has a wider viewing angle than a liquid crystal panel.
Recently, the flat panel display technology has attracted particular attention because it is easy to increase the size and the display quality is high because it is a self-luminous type. Generally, in this plasma display device, an ultraviolet ray is generated by gas discharge, and a phosphor is excited by the ultraviolet ray to emit light, thereby performing color display. Then, a display cell partitioned by a partition is provided on the substrate, and a phosphor layer is formed on the display cell. This plasma display device is roughly classified into an AC type and a DC type in terms of driving, and there are two types of discharge types, a surface discharge type and a counter discharge type. At present, the mainstream of plasma display devices is a surface discharge type having a three-electrode structure, which has a pair of display electrodes that are adjacent to each other in parallel on one substrate, and the other is a plasma display device. It has address electrodes arranged on the substrate in a direction intersecting the display electrodes, partition walls, and a phosphor layer. The phosphor layer can be made relatively thick, which is suitable for color display by phosphor. SUMMARY OF THE INVENTION It is an object of the present invention to stop the operation of an address driver circuit in such a plasma display device when an abnormality occurs. In order to achieve the above object, a plasma display device according to the present invention comprises: an address driver circuit for supplying display data to the address electrodes of a plasma display panel; A power recovery circuit disposed between the circuit and a power supply and recovering energy from the plasma display panel in accordance with a display operation of the plasma display panel, and a midpoint voltage detection circuit detecting a midpoint voltage of the power recovery circuit And two reference voltage generation circuits connected to a power supply and having different voltage values, two voltage comparison circuits connected to the midpoint voltage detection circuit and the two reference voltage generation circuits, respectively. And control means for controlling the discharge control operation in accordance with the signal (1). With this configuration, the operation of the address driver circuit can be stopped when an abnormality occurs in the address driver circuit portion. [0008] That is, according to the first aspect of the present invention, a plurality of rows of display electrodes are formed on a pair of substrates facing each other so as to intersect with the display electrodes. A plasma display panel having a plurality of discharge cells configured by providing a plurality of columns of address electrodes arranged to face each other; an address driver circuit for supplying display data to the address electrodes of the plasma display panel; A power recovery circuit disposed between an address driver circuit and a power supply and recovering energy from the plasma display panel in accordance with a display operation of the plasma display panel; and a midpoint voltage detecting a midpoint voltage of the power recovery circuit. A detecting circuit; two reference voltage generating circuits connected to a power supply and having different voltage values; 2 connected to the circuit and two reference voltage generating circuits, respectively.
And a control means for controlling a discharge control operation by a signal from the voltage comparison circuit. Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 7, but the embodiment of the present invention is not limited to this. First, the structure of a plasma display panel in a plasma display device will be described with reference to FIG. As shown in FIG. 1, a plurality of rows of stripe-shaped display electrodes 2 formed of pairs of scan electrodes and sustain electrodes are formed on a transparent front-side substrate 1 such as a glass substrate, and cover the electrode group. The dielectric layer 3 is formed as described above, and a protective film 4 is formed on the dielectric layer 3. A plurality of columns covered with an overcoat layer 6 are provided on a rear substrate 5 opposed to the front substrate 1 so as to intersect with the display electrodes 2 of scan electrodes and sustain electrodes. Are formed. A plurality of partitions 8 are arranged on the overcoat layer 6 between the address electrodes 7 in parallel with the address electrodes 7, and the phosphor layers 9 are provided on the side surfaces between the partitions 8 and on the surface of the overcoat layer 6. I have. The substrate 1 and the substrate 5 are provided with a display electrode 2 of a scan electrode and a sustain electrode and an address electrode 7.
Are arranged so as to be substantially orthogonal to each other with a minute discharge space interposed therebetween, the periphery thereof is sealed, and one or a mixed gas of helium, neon, argon, xenon is discharged in the discharge space. Sealed as gas. The discharge space is partitioned into a plurality of partitions by partition walls 8, so that a plurality of discharge cells are provided at intersections between the display electrodes 2 and the address electrodes 7, and each of the discharge cells has a red, green, and blue color. The phosphor layers 9 are sequentially arranged for each color such that FIG. 2 shows an electrode arrangement of the plasma display panel. As shown in FIG. 2, the scan electrodes, sustain electrodes, and address electrodes have a matrix configuration of M rows × N columns, and are arranged in a row direction. M rows of scan electrodes SCN1 to SCNM and sustain electrode SUS1
To SUSM, and N columns of address electrodes D1 to DN are arranged in the column direction. In the plasma display panel having such an electrode configuration, an address discharge is performed between the address electrode and the scan electrode by applying a write pulse between the address electrode and the scan electrode, and after a discharge cell is selected. , Between the scan electrode and the sustain electrode,
By applying a periodic sustain pulse that is alternately inverted, sustain discharge is performed between the scan electrode and the sustain electrode, and a predetermined display is performed. FIG. 3 shows a configuration of a display driving circuit of the plasma display device according to the present embodiment. As shown in FIG. 3, the plasma display panel (PDP) 10 having the configuration shown in FIG.
Scan driver circuit 12, sustain driver circuit 1
3, discharge control timing generation circuit 14, power supply circuit 15,
16. A / D converter (analog / digital converter)
17, scan number conversion unit 18, and subfield conversion unit 1
9 is provided. In the circuit of FIG. 3, first, the video signal VD
Is input to the A / D converter 17. Further, the horizontal synchronizing signal H and the vertical synchronizing signal V are supplied to the discharge control timing generation circuit 14, the A / D converter 17, the scan number conversion unit 18,
It is provided to the subfield converter 19. The A / D converter 17 converts the video signal VD into a digital signal, and supplies the image data to the scan number converter 18. The scanning number converter 18 converts the image data into a PDP
Converted into image data of the number of lines corresponding to the number of pixels of 10,
The image data for each line is converted into a subfield conversion unit 19
Give to. The subfield conversion unit 19 divides each pixel data of the image data for each line into a plurality of bits corresponding to a plurality of subfields, and divides each bit of the pixel data for each subfield into the address driver circuit 11.
Output serially to The address driver circuit 11
The power supply circuit 15 is connected to the power supply circuit 15 and converts data serially provided for each subfield from the subfield conversion unit 19 into parallel data, and supplies voltages to a plurality of address electrodes based on the parallel data. The discharge control timing generation circuit 14 generates discharge control timing signals SC and SU based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the scan driver circuit 12 and the sustain driver circuit 13, respectively. The scan driver circuit 12 has an output circuit 121 and a shift register 122. The sustain driver circuit 13 has an output circuit 131 and a shift register 132. The scan driver circuit 12 and the sustain driver circuit 13 are connected to a common power supply circuit 16. The shift register 122 of the scan driver circuit 12 supplies the discharge control timing signal SC supplied from the discharge control timing generation circuit 14 to the output circuit 121 while shifting in the vertical scanning direction. Output circuit 121
Supplies a drive signal voltage to a plurality of scan electrodes sequentially in response to a discharge control timing signal SC supplied from the shift register 122. The shift register 132 of the sustain driver circuit 13 supplies the discharge control timing signal SU supplied from the discharge control timing generation circuit 14 to the output circuit 131 while shifting in the vertical scanning direction. Output circuit 131
Supplies a drive signal voltage to a plurality of sustain electrodes sequentially in response to a discharge control timing signal SU given from the shift register 132. FIG. 4 shows an example of a timing chart of a display drive circuit of the plasma display device.
As shown in FIG. 4, during the writing period, after all the sustain electrodes SUS1 to SUSM are held at 0 (V),
A positive write pulse voltage + Vw (V) is applied to predetermined address electrodes D1 to DN corresponding to the discharge cells to be displayed on the first row.
Are applied to the scan electrodes SCN1 in the first row with negative scan pulse voltages -Vs (V), respectively, and the predetermined address electrodes D1 to DN and the scan electrodes SCN1 in the first row are applied.
At the intersection with the write discharge. Next, a positive write pulse voltage + Vw (V) is applied to predetermined address electrodes D1 to DN corresponding to the discharge cells to be displayed in the second row, and the scan electrodes SCN in the second row are applied.
When a negative scan pulse voltage −Vs (V) is applied to each of the scan electrodes 2, a write discharge occurs at the intersection of the predetermined address electrodes D <b> 1 to DN and the scan electrode SCN <b> 2 in the second row. The same operation as described above is sequentially performed. Finally, a positive write pulse voltage + Vw (V) is applied to predetermined address electrodes D1 to DN corresponding to the discharge cells to be displayed on the Mth row.
Are applied to the scan electrode SCNM of the M-th row, respectively, by applying a negative scan pulse voltage −Vs (V) to the predetermined address electrodes D1 to DN and the scan electrode SCNM of the M-th row.
A write discharge occurs at the intersection with. In the next sustain period, all scan electrodes S
When CN1 to SCNM are once held at 0 (V) and a negative sustain pulse voltage -Vm (V) is applied to all the sustain electrodes SUS1 to SUSM, the scan electrodes SCN1 to SCN at the intersection where the write discharge has occurred are performed.
A sustain discharge occurs between M and the sustain electrodes SUS1 to SUSM. Next, all the scan electrodes SCN1 to SCN
By alternately applying the negative sustain pulse voltage −Vm (V) to M and all the sustain electrodes SUS1 to SUSM, sustain discharge continuously occurs in the discharge cells to be displayed. Panel display is performed by the light emission of the sustain discharge. In the next erasing period, when all the scan electrodes SCN1 to SCNM are once held at 0 (V) and the erasing pulse voltage -Ve (V) is applied to all the sustain electrodes SUS1 to SUSM, the erasing discharge is started. To stop the discharge. With the above operation, one screen is displayed in the plasma display device. FIG. 5 is a diagram showing a main circuit configuration of an address driver circuit portion in the display drive circuit shown in FIG. 3. As shown in FIG. 5, an address driver circuit 11 comprising an address driver IC and a power supply circuit 15 are provided. Between
A power recovery circuit 20 that recovers energy from the PDP 10 in accordance with the display operation of the PDP 10 is connected and arranged. Also, a midpoint voltage detecting circuit 21 for detecting a midpoint voltage of the power recovery circuit 20, two reference voltage generating circuits 22 and 23 connected to a power supply and having different voltage values, A voltage comparison circuit 24 connected to the circuit 21 and the reference voltage generation circuit 22; a voltage comparison circuit 25 connected to the midpoint voltage detection circuit 21 and the reference voltage generation circuit 23; A microcomputer (microcomputer) 26 as control means for controlling the control operation is connected and arranged. In general, in a plasma display device, the midpoint voltage of the power recovery circuit connected to the address driver circuit is always detected, and when an abnormality occurs, it is detected that the midpoint voltage becomes 0 V from the normal state, and the microcomputer is notified of the abnormality. By notifying, the operation of the discharge control circuit is stopped, and the operation of the power supply circuit is also stopped to minimize the destruction of components of the power recovery circuit. Conventionally, for this kind of purpose, as shown in FIG. 6, a midpoint voltage detecting circuit 21 for detecting the midpoint voltage of the power recovery circuit 20 is connected and arranged, and the midpoint voltage is constantly detected. When the power recovery circuit 20 detects an abnormality, it detects that the midpoint voltage becomes 0 V, sends an abnormality occurrence signal to the microcomputer 26, stops the discharge control circuit operation, and also stops the power supply circuit operation. Although the destruction of the components of the power recovery circuit has been minimized, there has been a problem in that it is not possible to detect an abnormality other than that the midpoint voltage becomes 0V. In the present invention, a midpoint voltage detecting circuit 21 for detecting a midpoint voltage of the power recovery circuit 20, and two reference voltage generating circuits 22, 23 connected to a power supply and having different voltage values.
And two voltage comparison circuits 2 connected to the midpoint voltage detection circuit 21 and the two reference voltage generation circuits 22 and 23, respectively.
4 and 25, and a microcomputer 26 for controlling the discharge control operation in accordance with signals from the voltage comparison circuits 24 and 25 are connected and arranged so that the midpoint voltage detection range and the reference voltage range are always compared to determine the midpoint voltage. When the detection range deviates from the reference voltage range, an abnormality occurrence signal is sent to the microcomputer 26 to stop the operation of the discharge control circuit and the operation of the power supply circuit. FIG. 7 shows the midpoint voltage detection range according to the present invention. According to the circuit configuration of the present embodiment, when an abnormality occurs in the power recovery circuit, the circuit is operated not only when the midpoint voltage becomes 0 V but also when the midpoint voltage is out of the normal operation range. The operation can be stopped to minimize the destruction of the circuit. As is apparent from the above description, according to the plasma display device of the present invention, when an abnormality occurs in the power recovery circuit, not only when the midpoint voltage becomes 0 V, but also when the midpoint voltage becomes zero. Has the effect of stopping the circuit operation even when it is out of the normal operation range and minimizing the destruction of the circuit.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a schematic configuration of a panel of a plasma display device according to an embodiment of the present invention. FIG. 2 is an explanatory diagram showing an electrode arrangement of the panel of the plasma display device. 3 is a block circuit diagram showing an example of a display driving circuit of the plasma display device. FIG. 4 is a signal waveform diagram showing an example of a driving method of the plasma display device. FIG. 5 is a main part of a display driving circuit of the plasma display device. FIG. 6 is a circuit diagram showing a circuit as a comparative example of the circuit according to the present invention shown in FIG. 5. FIG. 7 is an explanatory diagram showing an operation range of the circuit according to the present invention. 2 Display electrode 7 Address electrode 10 Plasma display panel 11 Address driver circuit 15 Power supply circuit 20 Power recovery circuit 21 Midpoint voltage detection circuits 22, 23 Reference power supply Generating circuits 24 and 25 the voltage comparator circuit 26 microcomputer

Claims (1)

Claims: 1. A plurality of columns of display electrodes and a plurality of columns of address electrodes disposed to face each other so as to intersect with the display electrodes are provided on a pair of substrates facing each other to form a discharge space. A plasma display panel having a plurality of discharge cells configured by the above, an address driver circuit for supplying display data to the address electrodes of the plasma display panel, and disposed between the address driver circuit and a power supply; A power recovery circuit that recovers energy from the plasma display panel in accordance with the display operation of the plasma display panel, a midpoint voltage detection circuit that detects a midpoint voltage of the power recovery circuit, and a voltage value that is different from a voltage connected to a power supply. Two reference voltage generation circuits, each of which is connected to the midpoint voltage detection circuit and each of the two reference voltage generation circuits Two voltage comparison circuit, a plasma display apparatus characterized by comprising a control means for controlling the discharge control operation by a signal from the voltage comparator circuit.