JP2003329712A - Unit and method for signal processing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing unit for precisely counting a frequency of an analog signal even when a noise component is contained in an input signal, and to provide a signal processing method. <P>SOLUTION: A first detector 10 used to detect a first timing at which a level of the input signal is changed over to a level lower than a first slice level from a level higher than the first slice level; a second detector 20 used to detect a second timing at which the level of the input signal is changed over to a level higher than a second slice level from a level lower than the second slice level; and a signal generater 30 in which an output level is changed over in a case where the second timing is detected in succession to the first timing, and in a case where the first timing is detected in succession to the second timing, and which generates an output signal holding an output level other than in both cases are installed. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device and a signal processing method for binarizing the level of an analog signal, for example.

[0002]

2. Description of the Related Art Conventionally, as a signal processing device for counting the frequency of the level of an analog input signal containing a predetermined vibration component, the level of the input signal is binarized with reference to one slice level (also called a threshold level). As a result, there is known a signal processing device that counts the frequency of the input signal level.

[0003]

However, since the above-described conventional signal processing device binarizes the level of the input signal with one slice level as a reference, for example, a noise component is present in the analog input signal. If it is included, there is a problem in that a malfunction may occur near the slice level due to a noise component and an incorrect count may be performed.

The present invention has been made in view of the above circumstances, and an object thereof is to accurately count the frequency of an analog signal even when a noise component is included in the input signal. It is to provide a signal processing device and a signal processing method capable of performing the same.

[0005]

In order to achieve the above object, the signal processing apparatus according to the first aspect of the present invention is arranged such that the level of the input signal is higher than the first threshold level.
First detection means for detecting a first timing at which the input signal is switched to a level lower than the second threshold level, and the level of the input signal is higher than the second threshold level from a level lower than the second threshold level. Second detection means for detecting a second timing for switching to a level, when the second timing is detected subsequent to the first timing, and the first timing subsequent to the second timing The output level is switched when is detected, and otherwise the signal generation means generates an output signal holding the output level.

According to the signal processing device of the first invention, the first
The detection means detects the first timing at which the level of the input signal switches from a level higher than the first threshold level to a level lower than the first threshold level. The second detection means detects the second timing at which the level of the input signal switches from a level lower than the second threshold level to a level higher than the second threshold level. Then, in the signal generating means, the output level is switched when the second timing is detected subsequent to the first timing and when the first timing is detected subsequent to the second timing, and other than that. In, an output signal holding the output level is generated.

[0007] Preferably, the signal generating means is the first
When the first timing is detected by the detection means of
An output signal that holds the first output level and that holds the second output level is generated when the second timing is detected by the second detection means.

Further, preferably, in accordance with the input signal,
It has a control means for controlling at least one of the first threshold level referred to by the first detection means and the second threshold level referred to by the second detection means.

[0009] Further, preferably, it has an analog-digital conversion means for converting an input signal which is an analog signal into a digital signal.

Further, in order to achieve the above object, a second
The signal processing method of the invention of claim 1, wherein the input signal level is higher than the first threshold level, the first timing to switch to a lower level than the first threshold level is detected, and the input signal is detected. Of a second timing at which the level of the second threshold is switched from a level lower than the second threshold level to a level higher than the second threshold level; and the second timing subsequent to the first timing. Is detected and when the first timing is detected subsequent to the second timing, the output level is switched, and otherwise, an output signal that holds the output level is generated. .

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram for explaining a general analog signal counting process. For example, generally, when counting the frequency of an analog signal, the level of the analog input signal is set to 1 as shown in FIG.
Binarization with one slice level as a reference, for example, an H (high level) digital signal is generated when the analog input signal level is higher than the slice level, or an L (low level) digital signal is generated when the analog input signal level is lower than the slice level. , By counting the frequency of the digital signal,
It was counting the frequency of analog signals.

However, when the analog input signal includes a noise component, for example, as shown in FIG. 1, when the level of the input signal exceeds or falls below the slice level due to the noise component near the slice level, There is a problem that an erroneous digital signal is generated and an erroneous count occurs.

FIG. 2 is a diagram for explaining the signal processing method according to the present invention. In the signal processing method according to the present invention,
A plurality of slice levels (corresponding to the threshold level according to the present invention) are provided in order to eliminate erroneous counting due to the noise component described above, and for example, as shown in FIG. 2 slice levels V
L is provided and the level of the input signal is the first slice level V
The timing of crossing H and the second slice level VL is detected, and an output signal having an output level according to the detection result is generated.

Specifically, for example, the first timing at which the level of the analog input signal shifts from a level higher than the first slice level VH to a timing lower than the first slice level VH is detected, and the analog input is detected. A second timing at which the signal level shifts from a level lower than the second slice level VL to a level higher than the second slice level VL is detected, and a second timing is detected subsequent to the first timing. The output level is switched when the first timing is detected after the second timing and when the second timing is detected, and the output signal Q that holds the output level is generated at other times. Then, the frequency of the output signal Q is counted to count the frequency of the analog input signal. Hereinafter, a signal processing device according to the present invention will be described with reference to FIGS.

FIG. 3 shows a first signal processing apparatus according to the present invention.
It is a whole block diagram of embodiment of this. The signal processing device 1 according to the present embodiment has a first detection unit 10, a second detection unit 20, a signal generation unit 30, and a counter 40, as shown in FIG. 3, for example. The first detector 1 is connected to the terminal t1.
0 and the second detection unit 20 are connected, and the first detection unit 1
A signal generation unit 30 is connected to the 0 and second detection units 20, and a counter 40 is connected to the signal generation unit 30 via a terminal t2, for example.

The first detecting section 10 has, for example, a terminal t1.
A first timing at which the level of the input signal shifts from a level higher than the first slice level VH to a level lower than the first slice level VH, based on the input signal from Output to 30. For example, the first slice level VH is the first slice level VH according to the present invention.
Corresponding to the threshold level of.

The second detecting section 20 changes the level of the input signal from the level lower than the second slice level VL to the level higher than the second slice level VL based on the input signal from the terminal t1, for example. The second timing of shifting to is detected and output to the signal generator 30. For example, the second slice level VL corresponds to the second threshold level according to the present invention. For example, the second slice level VL is lower than the first slice level VH.

The signal generator 30 switches the output level when the second timing is detected after the first timing and when the first timing is detected after the second timing. Otherwise, the output signal Q holding the output level is generated. Specifically, for example, when the first detection unit 10 detects the first timing and then the second detection unit 20 detects the second timing, the signal generation unit 30, for example, outputs L ( Low level)
To H (high level), the output level of the output signal Q is switched. Further, for example, in the signal generation unit 30, when the second detection unit 20 detects the second timing and then the first detection unit 10 detects the first timing, for example, H (high level) is generated. The output level of the output signal Q from L to low (low level). In addition, the signal generator 30
Holds the output level of the output signal Q in cases other than the above.

More specifically, in the signal generating section 30, for example, when the first detecting section 10 detects the first timing and then the first detecting section 10 detects the first timing. Holds the output level of the held output signal Q without switching. Further, in the signal generation unit 30, when the second detection unit 20 detects the second timing, and when the second detection unit 20 subsequently detects the second timing, the output signal Q held is held. Hold the output level without switching. The signal generation unit 30 has the above-described function, for example, an RS-FF (Reset-set flip-flop) circuit or a JK.
-It is realized by an FF circuit or the like.

The counter 40 counts the digital signal Q generated and output by the signal generator 30 via the terminal t2, for example. For example, the counter 40 may count the digital signal Q for a predetermined period and measure the frequency of the predetermined period.

FIG. 4 shows a first signal processing device according to the present invention.
It is a figure which shows the whole structure of the specific example of. Specifically, the signal processing device 1a includes an operational amplifier 11, a power supply 12, a D latch 13, an inverter 14, an adder 15, a D latch 16, an operational amplifier 21, a power supply 22, as shown in FIG.
Reset / set (RS) which is the D latch 23, the inverter 24, the adder 25, the D latch 26, and the signal generation unit 30.
It has a circuit 31.

Operational amplifier 11, power supply 12, D-latch 1
3, inverter 14, adder 15, and D latch 16
Corresponds to a first detection unit, and includes an operational amplifier 21, a power supply 22,
D latch 23, inverter 24, adder 25, and D
The latch 26 corresponds to the second detector. The counter 40 is not shown here for the sake of simplicity.

The operational amplifier 11 outputs to the D-latch 13 a signal according to the differential voltage between the level of the analog input signal input from the input terminal t1 and the first slice level set by the power supply 12. Specifically, for example,
The operational amplifier 11 outputs a signal having a positive level higher than the reference potential when the level of the input signal is lower than the first slice level, and is negative than the reference potential when the level is lower than the first slice level. Output level signal.

The D latch 13 delays the output level corresponding to the level of the signal output from the operational amplifier 11 by one cycle and outputs the delayed output level to the inverter 14. Specifically, D
The latch 13 operates, for example, in response to the rising edge of the pulse of the clock signal CK output from the clock signal generation circuit (not shown), and determines whether the signal output from the operational amplifier 11 to the D1 terminal is higher or lower than a predetermined threshold value. The corresponding level is latched for only one cycle and output from the Q1 terminal to the inverter 14. For example, in the D latch 13, a predetermined threshold value is set to a value near the reference potential.

The inverter 14 inverts the output level of the signal output from the D latch 13 and outputs it to the adder 15. For example, the inverter 14 outputs to the adder 15 via the node A1. The adder 15 adds the signal output from the inverter 14 and the signal output from the operational amplifier 11, and outputs the result to the D latch 16.

The D latch 16 latches the level of the signal output from the adder 15 for one cycle according to the clock signal, and outputs it to the RS circuit 31. Specifically, the D latch 16 operates, for example, in response to the rising edge of the pulse of the clock signal CK output from the clock signal generation circuit (not shown), and the level of the signal input from the adder 16 to the D2 terminal for one cycle. Latch from the Q2 terminal
Output to the R terminal of the S circuit 31.

The operational amplifier 21 outputs to the D-latch 23 a signal according to the differential voltage between the level of the analog input signal input from the input terminal t1 and the second slice level set by the power supply 22. Specifically, for example,
The operational amplifier 21 outputs a signal having a positive level higher than the reference potential when the level of the input signal is higher than the second slice level, and is negative than the reference potential when the level is lower than the second slice level. Output level signal.

The D latch 23 delays the output level corresponding to the level of the signal output from the operational amplifier 21 by one cycle and outputs it to the inverter 24. Specifically, D
The latch 23 operates, for example, in response to a rising edge of a pulse of the clock signal CK output from a clock signal generation circuit (not shown), and has a level depending on whether the signal output from the operational amplifier 21 is higher or lower than a predetermined threshold value. 1
Latches only for cycles and outputs to the inverter 24. For example, the D latch 23 sets a predetermined threshold value to a value near the reference potential.

The inverter 24 inverts the output level of the signal output from the D latch 23 and outputs it to the adder 25. The adder 25 adds the signal output from the inverter 24 and the signal output from the operational amplifier 21, and outputs the result to the D latch 26.

The D latch 26 latches the level of the signal output from the adder 25 for one cycle according to the clock signal, and outputs it to the RS circuit 31. Specifically, the D latch 26 operates, for example, in response to the rising edge of the pulse of the clock signal CK output from the clock signal generation circuit (not shown), and latches the level of the signal input from the adder 26 for one cycle. And outputs it to the S terminal of the RS circuit 31.

FIG. 5 is a diagram for explaining one specific example of the operation of the signal processing device shown in FIG. Signal processing device 1
The above operation, for example, a specific example of the operation of the first detection unit 10 will be described with reference to FIG. In this specific example, the signal processing device 1a operates according to the rising edge of the pulse of the clock signal CK.

In the first detector 10, the timing t
At 0, as shown in FIG. 5, the D1 terminal of the D latch 13 has a predetermined level (for example, a negative level in this case),
The Q1 terminal is set to low level, the node A1 on the output side of the inverter 14 is set to high level, the D2 terminal of the D latch 16 is set to low level, and the Q2 terminal is set to low level.

When the signal output from the operational amplifier 11 becomes a positive level (high level), the D latch 13 holds the level corresponding to the level at the timing t1. In the D latch 16, the D2 terminal is switched to the high level by the adder 15 and holds the level. At the timing t2, the D latch 13 outputs D
The high level latched from the 1 terminal is output from the Q1 terminal, the inverted level is output by the inverter 14, and the node A1 becomes the low level. In the D latch 16, the D2 terminal is switched to the low level by the adder 15, and the level latched at the Q2 terminal (high level)
And is output to the RS circuit 31. At the timing t3, the Q2 terminal of the D latch 16 is switched to the low level.

As described above, in the first detector 10,
Based on the input signal, the first timing at which the level of the input signal shifts from a level higher than the first slice level VH to a level lower than the first slice level VH is detected and output to the signal generator 30. be able to. The operation of the second detection unit 20 is almost the same, and the level of the input signal shifts from the level lower than the second slice level VL to the level higher than the second slice level VL based on the input signal. Detect the second timing,
The signal is output to the signal generator 30.

The RS circuit 31 is, for example, a so-called RS.
-FF circuit, the first detection unit 10 at the reset terminal
Are connected, and the second detection unit 20 is connected to the set terminal. The RS circuit 31 sets the output level of the output signal Q to the high level (H) when the signal indicating the second timing is input from the second operational amplifier 21 to the set terminal.
The output level H is maintained. R
The S circuit 31 further includes the second operational amplifier 21 to the second operational amplifier 21.
Even when a signal indicating the timing of is input to the set terminal, the output level H is maintained.

When the signal indicating the first timing is input to the reset terminal from the first operational amplifier 11, the RS circuit 31 resets the held output level H and switches it to the output level L, and The output level L is held. The RS circuit 31 further includes the first operational amplifier 11
Even when the signal indicating the first timing is input to the reset terminal, the output level L is held.

FIG. 6 is a flow chart for explaining the operation of the signal processing device shown in FIG. The operation of the signal processing device 1 will be described with reference to FIGS. 6, 2 and 4.

First, an analog input signal is input to the signal processing device 1. Specifically, the analog input signal is the terminal t
1 through the first detection unit 10 and the second detection unit 20
Entered in.

In step ST1, the signal generator 30
Then, for example, as shown in FIG. 2, the first detection unit 10 changes the level of the input signal to the first slice level VH.
A first timing of switching from a higher level to a level lower than the first slice level VH is detected,
Subsequently, when the second detection unit 20 detects the second timing at which the level of the input signal switches from the level lower than the second slice level VL to the level higher than the second slice level VL (ST1). , The level of the output signal Q is switched from the high level to the low level (ST2), and the output level is held (ST3).

Specifically, for example, in the signal generation section 30, the first detection section 10 makes the level of the input signal the first level.
When the first timing of switching from a level higher than the slice level VH to a level lower than the first slice level VH is detected, a signal indicating that the first timing is detected is input to the reset terminal. . In the signal generator 30, when the signal is input to the reset terminal,
The output level of the set output signal is reset, for example, switched to low level.

Subsequently, in the signal generation unit 30, the second detection unit 20 causes the level of the input signal to change from the level lower than the second slice level VL to the second slice level VL.
When the second timing for switching to a higher level is detected, a signal indicating that the second timing has been detected is input to the set terminal. In the signal generator 30, when the signal is input to the set terminal, the output level of the output signal is switched from the low level to the high level, the output level is held, and the process proceeds to step ST4.

On the other hand, when it is determined in step ST1 that the second timing is not detected following the first timing in the signal generating section 30, the process proceeds to step ST4.

In step ST4, the signal generator 30
Then, for example, the second detection unit 20 detects the second timing at which the level of the input signal switches from a level lower than the second slice level VL to a level higher than the second slice level VL, and then continues. When the first detection unit 10 detects the first timing at which the level of the input signal is switched from the level higher than the first slice level VH to the level lower than the first slice level VH (ST4). , The level of the output signal Q is switched from low level to high level (ST
5) The output level is held (ST6), and the process returns to step ST1.

Specifically, for example, in the signal generation section 30, the second detection section 20 detects the second timing, and then the first detection section 10 changes the level of the input signal to the first slice. Level 1 to higher than level VH
When the first timing for switching to a level lower than the slice level VH is detected, a signal indicating that the first timing has been detected is input to the reset terminal. In the signal generator 30, when the signal is input to the reset terminal, the output level of the output signal that has been set is reset, for example, switched from the high level to the low level, and the output level is held.

On the other hand, if it is determined in step ST4 that the first timing has not been detected following the second timing, the process proceeds to step ST6 and the output level of the output signal Q is held.

Then, for example, the counter 40 counts the frequency in a predetermined time unit based on the output level of the output signal Q.

As described above, the signal generating section 30 outputs when the second timing is detected after the first timing and when the first timing is detected after the second timing. Since the output level of the signal Q is switched and the output level is maintained in other cases, the counter 40 outputs a digital signal whose frequency can be accurately counted even when an analog input signal including a noise component is input to the terminal t1. be able to.

In the signal processing device 1, the RS circuit 31 holds the output level H once the signal is input to the set terminal and keeps the output level unless the signal is input to the reset terminal. Even if an analog signal including a noise component is input, it does not affect the output level of the output signal Q. Further, in the RS circuit 31, once the signal is input to the reset terminal and the output level L is held, the output level is kept held unless the signal is input to the set terminal. Therefore, for example, an analog signal including a noise component is input. However, it does not affect the output level of the output signal Q. Therefore, even if the input signal contains a noise component, the frequency of the analog signal can be accurately counted.

Further, as described above, the frequency of the analog signal can be accurately counted even when the input signal contains some noise components, so that, for example, measures against noise on the analog input signal line are taken. It can be simplified.

FIG. 7 shows a second signal processing apparatus according to the present invention.
It is a figure which shows the whole structure of the specific example of. The difference between the signal processing device 1b according to the present specific example and the signal processing device 1b according to the first specific example described above is that an analog input signal is converted into a digital signal and the predetermined process described above is digitally processed. That is the point.

As shown in FIG. 7, for example, the signal processing apparatus 1b according to the present specific example has an A / D (analog / digital converter) 2, an adder 11b, a setting level 12b, an inverter 12c, a D latch 13, and an inverter. 14, adder 1
5, D latch 16, adder 21b, setting level 22b,
Inverters 22c and 22d, D latch 23, inverter 24, adder 25, D latch 26, and signal generation unit 3
It has an RS circuit 31 which is zero. The counter 40 is not shown for the sake of simplicity. Adder 11b, setting level 12
b, inverter 12c, D latch 13, inverter 1
4, the adder 15, and the D latch 16 correspond to the first detection unit 10, and include the adder 21b, the set level 22b, the inverters 22c and 22d, the D latch 23, and the inverter 2.
4, the adder 25, and the D latch 26 are the second detection unit 2
Equivalent to 0. The description of the components having the same functions as those of the first specific example will be omitted, and the differences will be described.

A / D (analog / digital converter) 2
Performs predetermined processing based on the level of the analog input signal input from the terminal t1, converts it into a digital signal having a predetermined bit length, and outputs the digital signal. The adder 11b receives the value of the digital signal output from the A / D 2 and the first set level 1
The value of the digital signal output from 2b via the inverter 12c is added and output to the D latch 13.

The setting level 12b generates data indicating the first slice level, for example, the slice level VH, and outputs it to the adder 11b via the inverter 12c.
The inverter 12c performs, for example, a process of inverting the polarity of the value of the digital signal input from the setting level 12b (a process of inverting the positive / negative sign), and outputs it to the adder 11b.

The adder 21b adds the value of the digital signal output from the A / D 2 and the value of the digital signal output from the set level 22b via the inverter 22c, and the D latch via the inverter 22d. To 23. The setting level 22b generates data indicating the second slice level, for example, the slice level LH, and outputs the data to the adder 21b via the inverter 22c.

The inverter 22c performs, for example, a process of inverting the polarity of the value of the digital signal input from the setting level 22b (a process of inverting the positive / negative sign), and the adder 2c
Output to 1b. The inverter 22d performs a process of inverting the polarity of the value of the digital signal output from the adder 21b (a process of inverting the positive / negative sign), and outputs it to the RS circuit 31.

The operation of the signal processing device 1b having the above configuration will be briefly described. First, an analog input signal is input to the signal processing device 1b. Specifically, the analog input signal is input to the A / D 2 via the terminal t1. In the A / D 2, the analog input signal is converted into a digital signal by a predetermined process and output to the first detection unit 10 and the second detection unit 20.

In the adder 11b of the first detection section 10, A
The value of the digital signal input from / D2 and the negative value of the value of VH indicating the first slice level input from the set level 12b via the inverter 12c are added,
It is output to the D latch 13. The subsequent operation is the same as that of the above-described first specific example, and therefore the description thereof is omitted. In the configuration described above, the adder 11b outputs a positive or negative value. The first timing is when the value output from the adder 11b changes from a negative value to a positive value.

In the adder 21b of the second detecting section 20, A
The value of the digital signal input from / D2 and the negative value of the value of VL indicating the second slice level input from the set level 22b via the inverter 22c are added and output to the inverter 22d. In the inverter 22d,
The polarity of the value input from the adder 21b is inverted and D
It is output to the latch 23. The operation thereafter is the first described above.
Since it is the same as the specific example of 1, the description is omitted.

In the above configuration, the adder 21b outputs a positive or negative value via the inverter 22d. The second timing is when the value output from the adder 21b via the inverter 22d changes from a negative value to a positive value.

In the RS circuit 31, when the signal is input to the reset terminal from the first detection section 10, the output level of the held output signal Q is reset as in the first specific example. , Low level (L), and the output level L is held. Further, in the RS circuit 31, when a signal is input to the set terminal from the second detection unit 20, the output level of the output signal Q is reset,
It is switched to the high level (H) and its output level H is held. Then, the counter 40 counts based on the output signal Q, for example, the frequency in a predetermined time unit.

As described above, in the signal processing device 1b according to the second specific example, the analog input signal is converted into the A / D2 signal.
Since the digital signal is converted into a digital signal and the so-called digital processing is performed, the above-described predetermined processing can be performed more accurately than the processing by the analog circuit.

FIG. 8 shows a second signal processing device according to the present invention.
It is a figure which shows the whole structure of embodiment of this. As shown in FIG. 8, the signal processing device 1c according to the present embodiment has a first detection unit 10, a second detection unit 20, a signal generation unit 30, and a control unit 50. Counter 40 for brief explanation
Is not shown.

A signal processing device 1c according to the present embodiment,
The difference from the signal processing device 1 according to the first embodiment is that
This is the point where the control unit 50 is provided. The other components have almost the same functions, and therefore their explanations are omitted and only the differences will be explained.

The controller 50 controls the first slice level VH referred to by the first detector 10 based on the level of the input signal, for example. Further, the control unit 50 may control the first slice level VH based on the output level of the output signal Q.

Specifically, the control unit 50 controls the digital signal output from the terminal t2 to have a desired waveform according to the maximum value of the level of the input signal and the magnitude of the noise component, for example. The value of the slice level VH of 1 is increased or decreased.

For example, as shown in the first specific example,
When the first slice level VH is set by the power supply voltage, the voltage is controlled to control the first slice level VH.
Control the value of H. Further, as shown in the second specific example, when performing digital processing, as shown in FIG. 8, the value of the first setting level 12b is increased / decreased and controlled.
Then, the first detection unit 10 performs the above-described predetermined detection processing according to the value of the set first slice level VH.

The control unit 50 also performs the same processing on the second detection unit 20. The control unit 50 controls the second slice level VL referred to by the second detection unit 20 based on the level of the input signal, for example. In addition, the control unit 50
May control the second slice level VL based on the output level of the output signal Q.

More specifically, the control unit 50 controls the terminal t according to the minimum value of the input signal and the magnitude of the noise component.
The value of the second slice level VL is increased or decreased so that the digital signal output from 2 has a desired waveform. For example, as shown in the first specific example, when the second slice level VL is set by the power supply voltage, the voltage is controlled to control the value of the second slice level VL.

When performing digital processing as shown in the second specific example, the value of the set level 22b is increased or decreased as shown in FIG. Then, the second detection unit 20 performs the above-described predetermined detection processing according to the value of the set second slice level VL.

The operation of the above-described structure will be briefly described centering on the operation of the control section 50. When a signal is input to the terminal t1, the control unit 50 outputs the digital signal output from the terminal t2 in accordance with the maximum value and the minimum value of the input signal for a predetermined period, the noise component, and the output signal Q, for example. The values of the first and second slice levels are controlled so as to obtain a desired waveform that is not affected by the noise component.

In the control unit 50, for example, when the noise component of the input signal is large, the first slice level VH
Is controlled to have a larger value, and the second slice level VL is controlled to have a smaller value. Then, the output signal Q having a desired waveform that is not affected by the noise component is output from the terminal t2. The operation of the other constituent elements is the same, and the description thereof is omitted.

As described above, by providing the control unit 50, for example, the first slice level VH is set in accordance with the maximum value and the minimum value of the input signal for a predetermined period, the noise component, and the output signal Q. Since the second slice level VL is controlled, the output signal Q that is not affected by the noise component is generated and output without extra setting, for example. And the counter 40 is more accurate,
For example, the frequency of the signal can be counted.

The present invention is not limited to this embodiment, and various suitable modifications can be made. For example, in the signal processing devices according to the first and second embodiments, the level of the input signal is switched from a level higher than the first slice level VH to a level lower than the first slice level VH. The second timing at which the input signal switches from a level lower than the second slice level VL lower than the first slice level to a level higher than the second slice level VL. The output level is switched when the second timing is detected following the first timing after the detection and the first timing is detected subsequent to the second timing, and the output level is held at other times. However, it is not limited to this form.

For example, the third timing at which the level of the input signal is changed from the level lower than the first slice level VH to the level higher than the first slice level VH is detected, and the level of the input signal is changed to the first level. The fourth timing of switching from a level lower than the second slice level VL lower than the first slice level VL to a level lower than the second slice level VL is detected,
The output level of the output signal Q is switched when the fourth timing is detected subsequent to the third timing and when the third timing is detected subsequent to the fourth timing, and the output level is changed otherwise. You may keep it.

In addition, the first and second embodiments of the first embodiment
It is sufficient that the technical idea of the present invention is realized even if the circuit is not the specific example or the circuit shown in the second embodiment.

Further, for example, by converting into a digital signal,
For example, the above-described predetermined processing may be performed by executing a program that realizes the above-described functions on a general-purpose computer such as a DSP (Digital signal processor) or a personal computer.

Further, in the first and second embodiments, the signal generator 30 realizes the above-mentioned function by the RS-FF circuit, but the present invention is not limited to this form. For example, the signal generation unit 30 detects when the second timing is detected following the first timing and when the second timing is detected.
When the first timing is detected subsequent to the timing of 1), the held output level is switched, and other than that, it may have a function of holding the output level.

[0078]

As described above, according to the present invention, it is possible to provide a signal processing device and a signal processing method capable of performing accurate counting even when an input signal contains noise.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a general analog signal counting process.

FIG. 2 is a diagram for explaining a signal processing method according to the present invention.

FIG. 3 is an overall configuration diagram of a first embodiment of a signal processing device according to the present invention.

FIG. 4 is a diagram showing an overall configuration of a first specific example of a signal processing device according to the present invention.

5 is a diagram for explaining a specific example of the operation of the signal processing device shown in FIG.

FIG. 6 is a flowchart for explaining the operation of the signal processing device shown in FIG.

FIG. 7 is a diagram showing an overall configuration of a second specific example of the signal processing device according to the present invention.

FIG. 8 is a diagram showing an overall configuration of a second embodiment of a signal processing device according to the present invention.

[Explanation of symbols]

1, 1a, 1b, 1c ... Signal processing device 1, 10 ... 1st detection part, 11 ... Operational amplifier, 11b ... Adder, 12 ... Power supply, 13 ... D latch, 14 ... Inverter, 15 ... Adder, 16 ... D latch, 20 ... 2nd detection part, 21 ... Operational amplifier, 21b ... Adder, 22 ... Power supply, 23 ... D latch, 24 ... Inverter, 25 ... Adder, 26 ... D latch, 30 ... Signal generation part, 31 ... reset / set (R
S) Circuit, 40 ... Counter, 50 ... Control section.

Continued front page    (72) Inventor Hidenobu Noda             134, Kobe-cho, Hodogaya-ku, Yokohama-shi, Kanagawa               Sony LSI Design Stock Association             In-house F term (reference) 2G029 AA02 AB00 AD01 AH01 AH04                 2G035 AA08 AB04 AC19 AC24 AD20                       AD24 AD25 AD29 AD56 AD65                 5J039 DA12 DB06 DC03 DC04 KK05                       KK09 KK10 MM08 NN00

Claims (5)

[Claims] 1. A first detecting means for detecting a first timing at which a level of an input signal is switched from a level higher than a first threshold level to a level lower than the first threshold level, and the input. Second detection means for detecting a second timing at which the signal level is switched from a level lower than the second threshold level to a level higher than the second threshold level, and following the first timing. When the second timing is detected and when the first timing is detected subsequent to the second timing, the output level is switched, and otherwise the output signal that holds the output level is generated. Signal processing device having a signal generating means for performing. 2. The signal generating means holds a first output level when the first timing is detected by the first detecting means, and the second timing is detected by the second detecting means. The signal processing device according to claim 1, wherein the signal processing device generates an output signal that holds the second output level when the signal processing is performed. 3. A first threshold level referred to by the first detecting means in response to the input signal, and the second threshold level.
The signal processing device according to claim 1, further comprising a control unit that controls at least one of the second threshold levels referred to by the detection unit. 4. The signal processing device according to claim 1, further comprising an analog-digital conversion means for converting an input signal which is an analog signal into a digital signal. 5. A procedure for detecting a first timing at which a level of an input signal is switched from a level higher than a first threshold level to a level lower than the first threshold level, and the level of the input signal is A procedure of detecting a second timing at which the level lower than the second threshold level is switched to a level higher than the second threshold level, and the second timing is detected following the first timing. The output level is switched when the first timing is detected subsequent to the second timing, and otherwise, an output signal that holds the output level is generated. .