JP2003318707A - Signal processing circuit and signal processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing circuit and a signal processing method for signal-processing a pulse signal with accurate periods. <P>SOLUTION: The signal processing circuit 30, provided at a wobble signal processing portion 48, is constituted of a positive electrode gate 71, a negative electrode gate 72, a counter circuit (positive electrode) 73, a counter circuit (negative electrode) 74, latching circuits 75 and 76, a change-over circuit 78, a digital LPF 79, R-S flip-flop 77, delay circuits 80, 81 and 82 and an OR gate 83. Chattering is eliminated, and the signal process is conducted at more accurate period by providing the signal processing circuit with two gates, the positive electrode one and the negative electrode one. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit and a signal processing method, and more particularly, to an optical disk device having an optical disc drive.
The present invention relates to a signal processing circuit and a signal processing method for processing a digital signal generated from an M (Frequency Modulation) modulated signal.

[0002]

2. Description of the Related Art Conventionally, an FM modulated signal is converted into a digital FM signal.
A signal processing circuit that generates a signal is provided in a reproduction system such as an optical disk device.

FIG. 8 shows a block diagram of a conventional signal processing circuit. Further, FIG. 9 shows an ideal timing chart in the conventional signal processing circuit. In FIG. 8, the signal processing circuit 10 includes a double-edge detection circuit 11, a counter circuit 12, a latch circuit 13, and a digital LPF circuit 1.
It is composed of 4.

The both edge detection circuit 11 is supplied with the FM modulation signal shown in FIG. The both-edge detection circuit 11 detects the supplied FM modulation signal as shown in FIG.
It is converted into the FM pulse signal shown in (B). The FM pulse signal is converted such that the level of the FM modulated signal is High when the level is higher than zero level, and Low when the level is low. The both-edge detection circuit 11 detects the rising edge and the falling edge of the converted FM pulse signal and generates the both-edge signal 18 shown in FIG. 9C. The both edge signals are supplied to the counter circuit 12, the latch circuit 13 and the digital LPF 14 (18).

The counter circuit 12 is supplied with a clock pulse from the terminal 16 and both edge signals from both edge detection circuits 11. The counter circuit 12 counts the clock pulse and supplies the count values Q1 to Qn to the latch circuit 13 (19). The counter circuit 12 is reset by both edge signals and counts between the edges.

Explaining with the count value of FIG. 9 (D), when the count value is counted up to N1, it is reset by the edge output of both edge signals shown in FIG. 9 (C),
The count value becomes 0. After the reset, the counting of the count value is restarted, and when the count value reaches N2, it is reset by the edge output of both edge signals. In this way, the count value when reset by both edge signals becomes N1, N2, N3, N4.

The latch circuit 13 is supplied with the count value from the counter circuit 12 and both edge signals from both edge detection circuits 11. The latch circuit 13 latches the count values Q1 to Qn based on the timing of the edge output of both edge signals. In the count value of FIG. 9D, the latch circuit 13 has count values N1, N2, N.
3 and N4 are latched at the reset timing. The latched count value is supplied to the digital LPF 14.

The count value from the latch circuit 13 and both edge signals from both edge detection circuits 11 are supplied to the digital LPF 14. The digital LPF 14 performs digital processing based on the count value supplied from the latch circuit 13 to remove the high frequency components of the FM modulated signal. The digitally processed FM signal is supplied to the terminal 17. Signal processing is performed based on the output digital data of the digital LPF 14.

As described above, the signal processing circuit detects both edge signals of the FM pulse signal generated from the FM modulated signal, counts the number of clocks by the counter at the timing of the both edge signals, and based on the count value. Performs digital processing and signal processing.

Further, when the signal processing is performed at the ideal timing as shown in FIG. 9, a signal and a count value corresponding to the FM modulated signal can be obtained, and an accurate digital FM signal can be obtained. However, noise is superimposed on the actual FM modulated signal.

FIG. 10 shows an actual FM modulation signal and an enlarged view around the zero level. In FIG. 10, near the zero level, the FM modulated signal and the zero level cross a plurality of times due to the noise of the FM modulated signal, so that each of the rising edge and the falling edge of the signal is detected a plurality of times. Therefore, the double-edge signal supplied from the double-edge detection circuit 11 shown in FIG. 8 is not accurately detected.

FIG. 11 shows a timing chart in an actual signal processing circuit. FIG. 11A shows an FM pulse signal,
11B shows both edge signals, FIG. 11C shows a clock pulse (CLK), and FIG. 11D shows a count value. The timing charts shown in FIGS. 11A to 11D are generated by the FM-modulated signal in which actual noise shown in FIG. 10 occurs.

The FM pulse signal of FIG. 11A is as shown in FIG.
Since the noise of the FM modulated signal shown in (1) crosses the zero level a plurality of times, a plurality of rising edges and falling edges occur during the rising period T1 and the falling period T2 of the signal. A plurality of rising and falling edges that occur in the periods T1 and T2 are called chattering.

Due to the chattering generated in the FM pulse signal, a plurality of edges are detected in the periods T1 and T2 as shown in FIG. 11 (B). Since a plurality of edges are detected, the count start position of the clock pulse in FIG. 11C cannot be accurately determined, and FIG.
The count value of can not be obtained accurately.

Therefore, when an actual FM modulated signal is processed by the signal processing circuit, chattering occurs in the FM pulse signal because noise occurs in the FM modulated signal, and accurate signal processing of the digital FM signal must be performed. I couldn't.

Therefore, the method described below is used so that an accurate digital FM signal can be obtained even when the FM pulse signal in which chattering has occurred is processed.

FIG. 12 shows a timing chart for removing conventional chattering. Figure 12 (A) shows FM
A pulse signal, FIG. 12B shows an FM pulse signal after chattering removal, and FIG. 12C shows both edge signals.
The FM pulse signal shown in FIG.
Chattering is removed by 1 and F of FIG.
It becomes an M pulse signal. Both edge signals of FIG. 12C are generated based on the FM pulse signal of FIG. 12B.

The chattering-removed FM pulse signal shown in FIG. 12B has a timing t2 at which chattering disappears when chattering occurs at timing t1.
The rising edge is not fixed until. After that, the FM pulse signal continues at the same level for a certain period of time T3, and at timing t3, the FM pulse signal determines rising edge detection. At this time, the period until the detection of the rising edge of the FM pulse signal is confirmed after the chattering is removed is Tx.

Next, when chattering occurs at the timing t4, the falling edge is not fixed until the timing t5 when the chattering disappears. After that, the FM pulse signal has the same level and is continued for a certain period of time T3, and at timing t6, the FM pulse signal determines the falling edge detection. At this time, the period until the detection of the falling edge of the FM pulse signal after the chattering is removed is Ty.

On the other hand, at timings t7 and t9 at which chattering does not occur in the FM pulse signal, a predetermined period T3 is delayed to determine the rising and falling edge detection.

As described above, the chattering-removed FM pulse signal is generated by a method of determining the rising and falling edge detection when the FM pulse signal reaches the same level for a certain period. In this method, when chattering occurs, the amount of delay in the period until the edge detection is confirmed is the sum of the period until chattering disappears and a fixed period, and when chattering does not occur, only a fixed period is delayed. It becomes the amount.

[0022]

As described above, noise is present in an actual signal, and the rising and falling edges of this signal are not detected at a constant cycle, so that accurate signal processing can be performed. Absent.

Further, in order to remove the noise, when the period in which the noise is generated and a certain period are delayed to confirm the edge detection, the edge detection is performed when the noise is present and when it is not present. The amount of delay is different, and the signal cycle changes. As a result, the counter value becomes an abnormal value, and accordingly, the value held in the latch circuit also increases or decreases with respect to the normal value. As a result, an accurate signal cannot be obtained.

Therefore, the present invention solves the above problems,
An object of the present invention is to provide a signal processing circuit and a signal processing method capable of processing an input pulse signal in an accurate cycle.

[0025]

According to a first aspect of the invention, in a signal processing circuit for generating a digital signal according to an input pulse signal, a predetermined period including at least one pulse of the input pulse signal, A clock pulse output means for outputting a clock pulse with one of the polarities, a counting means for counting the clock pulses, a setting means for setting a predetermined period based on a predetermined count value with one of the polarities, and a counting means. Output means for outputting an output digital signal based on the count value of the means.

According to the first aspect of the present invention, the clock pulse output means for outputting the clock pulse with one of the polarities in the predetermined period including at least one pulse of the input pulse signal, and the clock pulse By having the counting means for counting and the output means for outputting the output digital signal based on the count value of the counting means, it is possible to have a plurality of pulse signals for counting clock pulses, You can get the count value. A more accurate output digital signal can be output based on the count values of the plurality of pulse signals.

According to a second aspect of the present invention, the clock pulse output means outputs the clock pulse when the input pulse signal has a positive polarity, and the clock pulse output means outputs the clock pulse when the input pulse signal has a negative polarity. A second clock pulse output means for outputting a pulse, wherein the counting means comprises a first counting means for counting the clock pulses from the first clock pulse output means and a second clock pulse output means for counting the clock pulses from the first clock pulse output means. A second counting means for counting the clock pulses.

According to the second aspect of the invention, the clock pulse output means has first clock pulse output means and second clock pulse output means, and the counting means is the first counting means. By including the second counting means, more precise signal processing can be performed.

According to a third aspect of the invention, the first counting means outputs the first timing signal with a predetermined count value, and the second counting means outputs the second timing signal with a predetermined count value. The output means outputs the second count value of the second count means with the first timing means and the first latch means for latching the first count value of the first count means with the second timing signal. And a second latching means for latching.

According to a third aspect of the invention, the counting means counts the clock pulses from the second clock pulse output means and the third counting means for counting the clock pulses from the first clock pulse output means. The setting means sets the predetermined period based on predetermined count values of the third counting means and the fourth counting means.

According to the invention described in claim 3, the counting means has the third counting means and the fourth counting means, and by setting a predetermined period by these count values, a plurality of pulses can be obtained. The count value of the signal can be obtained. A more accurate output digital signal can be output based on these count values.

According to a fourth aspect of the present invention, the third counting means outputs the first timing signal with a predetermined count value, and the fourth counting means outputs the second timing signal with a predetermined count value. And the setting means outputs a signal that determines a predetermined period according to the first timing signal and the second timing signal.

According to the invention described in claim 4, the third counting means outputs the first timing signal, the fourth counting means outputs the second timing signal, and the setting means outputs the first timing signal. By outputting a signal that defines a predetermined period from the signal and the second timing signal, more precise signal processing can be performed.

The invention described in claim 5 is characterized in that the setting means has a flip-flop set by the first timing signal and reset by the second timing signal.

According to the fifth aspect of the present invention, by having the setting means for setting and resetting by the flip-flop, more precise processing of the input pulse signal can be performed and the accuracy of the output signal can be improved. Can be improved.

According to a sixth aspect of the invention, one of the third counting means and the fourth counting means resets the count value in response to the reset of the flip-flop.

According to the sixth aspect of the invention, one of the third counting means and the fourth counting means resets the count value in response to the resetting of the flip-flop, so that a more precise input is performed. The pulse signal can be processed, and the accuracy of the output signal can be improved.

According to the seventh aspect of the invention, the output means outputs the third timing signal in response to the up edge of the Q output of the flip-flop, and the down edge of the Q output of the flip-flop. Down edge output means for outputting a fourth timing signal, first latch means for latching the count value of the first counting means in response to the fourth timing signal, and first latch means for responding to the third timing signal. A second latching means for latching the count value of the second counting means.

According to the seventh aspect of the invention, the output means outputs up-edge output means and down-edge output means for outputting the third and fourth timing signals in response to the edge of the Q output of the flip-flop, and By having the first and second latching means for latching the count value according to the third and fourth timing signals, more precise processing of the input pulse signal can be performed and the accuracy of the output signal can be improved. Can be improved.

According to the eighth aspect of the invention, the output means delays the third timing signal to output the fifth timing signal, and the fourth delay signal delays the sixth timing signal to generate the sixth timing signal. Second delay means for outputting the timing signal of the first counting means is reset in response to the fourth timing signal, and the second counting means is reset in response to the third timing signal. It is characterized by being done.

According to the invention described in claim 8, the output means delays the third and fourth timing signals to output the fifth and sixth timing signals, and the first delay means and the second delay means. And the first and second counting means are reset according to the sixth and fifth timing signals, respectively, so that more precise processing of the input pulse signal can be performed, and the output signal The accuracy of can be improved.

According to a ninth aspect of the present invention, the output means has a first count value latched by the first latch means and a second count value latched by the second latch means according to the output of the flip-flop. It is characterized by having a switching means for switching the output of the value.

According to the invention described in claim 9, the output means has a switching means for switching the output of the first count value and the output of the second count value, thereby performing more precise processing of the input pulse signal. Therefore, the accuracy of the output signal can be improved.

According to a tenth aspect of the present invention, the output means generates the phase difference pulse signal having a predetermined phase difference from the input pulse signal, and the third timing according to the rising edge of the phase difference pulse signal. Up edge output means for outputting a signal, down edge output means for outputting a fourth timing signal in response to a down edge of the phase difference pulse signal, and count value of the first counting means in response to a third timing signal And a second latching means for latching the count value of the second counting means in response to the fourth timing signal.

According to the tenth aspect of the invention, the output means outputs up-edge output means and down-edge output means for outputting the third and fourth timing signals in response to the up-edge of the phase difference pulse signal, and By having the first and second latching means for latching the count value according to the third and fourth timing signals, more precise processing of the input pulse signal can be performed and the accuracy of the output signal can be improved. Can be improved.

In the eleventh aspect of the present invention, the output means delays the third timing signal to output the fifth timing signal, and the fourth delay signal delays the sixth timing signal. Second delaying means for outputting the timing signal of the first counting means is reset in response to the fifth timing signal, and the second counting means is reset in response to the sixth timing signal. It is characterized by being done.

According to the eleventh aspect of the present invention, the output means delays the third and fourth timing signals to output the fifth and sixth timing signals, and the first delay means and the second delay means. And the first and second counting means are reset according to the fifth and sixth timing signals, respectively, so that more precise processing of the input pulse signal can be performed, and the output signal The accuracy of can be improved.

According to a twelfth aspect of the present invention, the output means has third delay means for delaying the output of the phase difference pulse signal and outputting the delayed phase difference pulse signal, and outputs the delayed phase difference pulse signal. It is characterized by further comprising switching means for switching between outputting the first count value latched by the first latch means and the second count value latched by the second latch means.

According to the twelfth aspect of the present invention, the output means outputs the delayed phase difference pulse signal, the third delay means, and the first count value and the second count value according to the output of the delayed phase difference pulse signal. By including a switching unit that switches the output of the count value of, it is possible to perform more precise processing of the input pulse signal and improve the accuracy of the output signal.

The invention described in claim 13 is characterized in that the output means includes a digital low-pass filter.

According to the thirteenth aspect of the present invention, by using the digital low pass filter, a more accurate output digital signal can be output based on the processed signal.

According to a fourteenth aspect of the present invention, in a signal processing method for generating a digital signal according to an input pulse signal, either polarity is applied in a predetermined period including at least one pulse of the input pulse signal. A clock pulse output procedure for outputting a clock pulse, a count procedure for counting clock pulses, a setting procedure for setting a predetermined period based on a predetermined count value in one of the polarities, and a count value for the count procedure It is characterized in that it has an output procedure for outputting an output digital signal.

According to the fourteenth aspect of the present invention, a clock pulse output procedure for outputting a clock pulse with either polarity during a predetermined period including at least one pulse of the input pulse signal, and the clock pulse By having a counting procedure for counting, a setting procedure for setting a predetermined period based on a predetermined count value in one of the polarities, and an output procedure for outputting an output digital signal based on the count value of the counting procedure. It is possible to have a plurality of pulse signals for counting clock pulses, and it is possible to obtain count values of the plurality of pulse signals. A more accurate output digital signal can be output based on the count values of the plurality of pulse signals.

[0054]

1 is a block diagram of an optical disk device according to an embodiment of the present invention.

In FIG. 1, the optical disk device 100 is
Disk 40, optical system 41, spindle motor 42, sled motor 43, laser driver 44, front monitor 45, ALPC (Absolute Time In)
Pregroove) 46, memory compensation circuit 47, wobble signal processing unit 48, RF amplifier 49, focus / tracking servo circuit 50, feed servo circuit 51, spindle servo circuit 52, CD encode / decode circuit 53, D / A converter 54, audio Amplifier 55,
RAM 56, 58, CD-ROM encode / decode circuit 57, interface / buffer controller 5
9, a CPU 60, a host computer 61 and the like.

A signal processing circuit for carrying out the signal processing of the present invention is provided in the wobble signal processing section 48. The FM modulated signal is processed by this circuit to generate a digital FM signal. The recording system is composed of an optical system 41, a laser driver 44, a front monitor 45, an ALPC 46, a memory compensating circuit 47, a wobble signal processing section 48 and the like.
A signal is recorded in a storage medium such as an optical disk by these circuits.

The optical system 41 represents an optical head for reading the signal of the disk 40, and includes an objective lens, an actuator,
1/4 wave plate, collimator lens, beam splitter,
It is composed of a light emitting element (laser diode), a light receiving element (photodetector), and the like. The optical system 41 is controlled by a sled motor 43 and a focus / tracking servo circuit 50.

The sled motor 43 is used by the feed servo circuit 5
The drive control of 1 moves the optical pickup in the radial direction of the disc. Focus / tracking servo circuit 5
0 controls focus servo and tracking servo.

The disc 40 is a CD-R (write-once disc), a CD-RW (rewritable disc), or the like.
It is controlled by the spindle motor 42.

The spindle motor 42 is controlled by the spindle servo circuit 52 so as to rotate the disk at a predetermined rotation speed.

The focus / tracking servo circuit 50, the feed servo circuit 51, and the spindle servo circuit 5 described above.
2 is controlled based on signals from the CPU 60 and the RF amplifier 49. The RF amplifier 49 is a head amplifier that amplifies a reproduction signal. RF amplifier 49 shown here
Includes a matrix amplifier and takes out various servo signals in addition to the main signal and outputs them to each servo control circuit.

The desired disk 4 is controlled by these control circuits.
The position of 0 is determined, and the signal of the disc 40 is sent from the optical system 41 to the RF amplifier 49. The RF amplifier 49 sends the EFM signal to the CD encode / decode circuit 53. The CD encode / decode circuit 53 is a CI
RC (Cross Interleaved Reed)
-Solomon Code) encoding / decoding, EFM (Eightto Fourteen Mo)
processing) such as modulation / demodulation and synchronization detection. In addition, the CD encode / decode circuit 53
A clock pulse is sent from the CPU 60 and demodulation processing is performed. The demodulated signal is sent to the CD-ROM encode / decode circuit 57. In this CD-ROM encode / decode circuit 57, the E specific to the CD-ROM is used.
CC (Error Correction Codin)
g) Encoding / decoding, header detection, etc. are performed. Data is temporarily stored using the RAM 56 to perform the processing. The processed data is sent to the interface / buffer controller 59. The interface / buffer controller 59 sends and receives data to and from the host computer and controls the data buffer. Data is temporarily stored using the RAM 58 to perform the processing.

CD-ROM encode / decode circuit 57, interface / buffer controller 59
Is also controlled by the CPU 60. interface/
After the processing by the buffer controller 59, the processing result is sent to the host computer 61, and the processing corresponding to the data is performed.

On the other hand, when outputting sound, the demodulated signal from the CD encode / decode circuit 53 is sent to the D / A converter 54 and converted from digital to analog.
This analog-converted signal is amplified by the audio amplifier 55, and this audio signal is output.

In this way, the optical disk device 100 performs the reproduction / recording process, and the signal processing circuit of the present invention is provided on the wobble signal processing section 48 and processes the digital FM signal generated from the FM modulated signal. To do.

FIG. 2 shows a block diagram of a signal processing circuit according to an embodiment of the present invention. In FIG. 2, the signal processing circuit 30 provided in the wobble signal processing unit 48 includes a positive polarity gate 71, a negative polarity positive gate 72, and a counter circuit (positive polarity) 7.
3, counter circuit (negative polarity) 74, latch circuits 75, 7
6, switching circuit 78, digital LPF 79, RS flip-flop 77, delay circuits 80, 81, 82, OR
It is composed of a gate 83.

The positive polarity gate 71 and the negative polarity gate 72 are
The wobble FM pulse signal terminal 84 and the clock terminal 85 are connected. Positive polarity gate 71, negative polarity gate 72
Is supplied with a zero level 70 from the wobble FM pulse signal terminal 84 and a clock pulse signal from the clock terminal 85.

The positive polarity gate 71 outputs a clock pulse to the counter circuit 7 when the level of the FM modulation signal is higher than the zero level, that is, when the FM pulse signal is at the high level.
Send to 3. The negative polarity gate 72 is F for zero level.
When the M modulation signal level is low, that is, when the FM pulse signal is low level, the clock pulse is sent to the counter circuit 74.

The counter circuit 73 has a reset input and a carry output, and counts the clock pulse supplied from the positive polarity gate 71. Counter circuit 73
Resets the count values Q1 to Qn by the signal input from the reset input. In addition, the counter circuit 73
Outputs a pulse from the carry output to the delay circuit 81 and the latch circuit 76 when the count reaches a predetermined value.

The delay circuit 81 delays the carry output of the counter 73 for a predetermined period and supplies it to the reset input of the counter circuit 74, the set of the RS flip-flop 77 and the OR gate 83.

The latch circuit 75 latches the count value of the counter circuit 73 by the carry output of the counter circuit 74. The latched count value is switched to the switching circuit 78.
Is supplied to the B input of.

The counter circuit 74 has a reset input and a carry output, and counts the clock pulse supplied from the negative polarity gate 72. Counter circuit 74
Resets the count value by the pulse input from the reset input. Further, the counter circuit 74 outputs a pulse from the carry output to the delay circuit 80 and the latch circuit 75 when the count reaches a predetermined value.

The delay circuit 80 delays the carry output of the counter circuit 74 for a predetermined period, reset input of the counter circuit 73, reset of the RS flip-flop 77, and OR.
Supply to the gate 83.

The latch circuit 76 latches the count value of the counter circuit 74 by the carry output of the counter circuit 73. The latched count value is switched to the switching circuit 78.
Sent to input A of.

The switching circuit 78 includes the latch circuits 76 and 7
The output of the count value supplied from 5 to the A input and the B input is switched according to the pulse from the RS flip-flop 77.

The RS flip-flop 77 is a flip-flop having a reset set, and controls switching of the switching circuit 78 by Q output. The Q output output from the RS flip-flop 77 is sent to the switching circuit 78.

The outputs of the A and B inputs are switched based on the above Q output. A input or B output by switching
The input is supplied to the digital LPF 79 and the digital FM
The signal is output from the terminal 86.

In the digital LPF 79, the OR gate 83
A pulse whose output is delayed by a delay circuit 82 is supplied. The digital LPF 79 outputs a digital FM signal based on the supplied pulse.

In this way, the signal processing circuit is provided with two gates of positive and negative polarities to obtain the timing when counting the high level and the low level of the FM pulse signal, and to set the high or low period including chattering. By counting, the high period and the low period of the FM pulse signal can be reliably determined.

FIG. 3 shows a timing chart of the signal processing circuit of the present invention. FIG. 3A shows an FM pulse signal, and FIG.
3B shows a clock pulse (CLK), FIG. 3C shows a positive polarity gate, FIG. 3D shows a negative polarity gate, FIG. 3E shows a positive polarity count value, and FIG. 3F shows a negative polarity count. Value, Figure 3
(G) is a carry pulse (positive), FIG. 3 (H) is a carry pulse (negative), FIG. 3 (I) is a delayed (Delay) pulse (positive), and FIG. 3 (J) is a delayed (Delay) pulse (negative). ), FIG. 3 (K) is an RS flip-flop, and FIG.
3L shows an output count value, FIG. 3M shows an OR gate output, and FIG. 3N shows a delayed pulse (OR).

The FM pulse signal of FIG. 3 (A) and FIG. 3 (B)
Clock pulses are supplied to the positive polarity gate and the negative polarity gate. The positive polarity gate is closed when the FM pulse signal is at low level, while the negative polarity gate is open and is output as shown in FIGS. 3C and 3D.

At time t1, the FM pulse signal changes to high level. At this time, the positive polarity gate is opened and the clock pulse is supplied to the counter circuit 73.
The counter circuit 73 counts the supplied clock pulse. The positive count value is as shown in FIG.

From time t1 to t2, chattering occurs in the FM pulse signal. At this time, since the pulse supply from the positive polarity gate is intermittent, the positive polarity count value gradually increases.

After a lapse of a fixed period Tc from the time t1 when the clock pulse signal is supplied to the counter circuit 73, the counter circuit 73 supplies the carry pulse (positive) of FIG. 3G to the delay circuit 81 and the latch circuit 76. . At this time, time t
It is 3. Further, here, the period Tc is determined by the count value.

At time t3, the latch circuit 76 latches the count value of the counter circuit 74 based on the carry pulse (positive) from the counter circuit 73. After that, the carry pulse (positive) from the counter circuit 73 is delayed by the delay circuit 8.
Delayed by 1. The delayed delayed pulse (positive) shown in FIG. 3 (I) is supplied to the reset input of the counter circuit 74. After that, the count value of the counter circuit 74 is reset. The delay pulse (positive) by the delay circuit 81 is
It is set in consideration of the latch period.

From time t2 to time t4, the high level state of the FM pulse signal is maintained, so that the positive polarity count value shows a constant increase.

At time t4, the FM pulse signal changes to low level. At this time, the negative polarity gate is opened and a clock pulse is supplied to the counter circuit 74.
The counter circuit 74 counts the supplied clock pulse. The negative count value is as shown in FIG.

From time t4 to t5, chattering occurs in the FM pulse signal. At this time, the positive gate 71
And the clock pulse supplied from the negative polarity gate 72 becomes intermittent. Therefore, the positive polarity count value and the negative polarity count value gradually increase.

After a lapse of a certain period Tc from the time t4 when the clock pulse signal is supplied to the counter circuit 74, the counter circuit 74 outputs the carry pulse (negative) of FIG. 3H to the latch circuit 75, the positive polarity gate 71, It is supplied to the delay circuit 80. At this time, it is time t6.

At time t6, the latch circuit 75 latches the count value of the counter circuit 73 based on the carry pulse (negative) from the counter circuit 74. Then, the carry pulse (negative) from the counter circuit 74 is delayed by the delay circuit 80. The delayed delay pulse (negative) shown in FIG. 3 (J) is supplied to the reset input of the counter circuit 73. After that, the count value of the counter circuit 73 is reset.

From time t6 to t7, the low level state of the FM pulse signal is maintained, so the negative polarity count value shows a constant increase.

The RS flip-flop 77 shown in FIG. 3K is set by the delay pulse (positive) from the delay circuit 81. Further, it is reset by the delay pulse (negative) from the delay circuit 80. The Q output generated based on these sets and resets is supplied to the switching circuit 78.

The switching circuit 78 switches to output the A input when the Q output is at the high level, and switches to output the B input when the Q output is at the low level. This output is
The output count value shown in FIG. That is, the carry pulse (positive) of the counter circuit 73 switches the output of the A input, and the carry pulse (negative) of the counter circuit 74 switches the output of the B input. When these carry pulses are supplied to the OR gate 83, FIG.
An OR gate output as shown in (M) is output. OR
The output from the gate 83 is supplied to the delay circuit 82 and delayed as shown in FIG. The delay amount of the delay circuit 82 is determined in consideration of the period required for the output of the switching circuit 78.

The output data from the switching circuit 78 and the clock pulse delayed by the delay circuit 82 are the digital LP.
It is sent to F79. The data sent to the digital LPF 79 is signal-processed based on the delayed clock pulse.

In this manner, in the FM pulse signal in which chattering has occurred, the positive / negative gate is switched depending on the period Tc, that is, the count value of each polarity, so that a more accurate cycle count value can be obtained. it can. Therefore, appropriate signal processing can be performed.

On the other hand, when chattering does not occur as at times t7 to t10, the negative / positive polarity gate is switched after the lapse of the period Tc from the rise and fall of the FM pulse signal. Then, similarly to the above, each counter circuit and each latch circuit are controlled to perform signal processing.

As described above, even when chattering does not occur, the positive / negative period is obtained depending on the period Tc, that is, the count value of each polarity.
By switching the negative polarity gate, a more accurate count value of the cycle can be obtained. Therefore, appropriate signal processing can be performed.

FIG. 4 shows a block diagram of a modification of the signal processing circuit shown in FIG. In the signal processing circuit shown in FIG. 4, the same components as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 4, the signal processing circuit 31 is an AN
D gates 87, 88, inverter 89, high gate counter 90, low gate counter 93, counter circuit (positive polarity) 97, counter circuit (negative polarity) 95, gate circuits 91, 94, latch circuits 96, 98, RS flip-flops. And a high edge output circuit 99, a low edge output circuit 102, delay circuits 101 and 103, and the like.

The AND gate 87 is connected to the FM pulse signal terminal 84 and the clock terminal 85. The AND gate 87 performs a logical product operation on the supplied clock pulse and FM pulse signal. The AND gate 88 is connected to the FM pulse signal terminal 84 and the inverter 89. A
The ND gate 88 performs a logical product operation with the clock pulse and the inverted signal of the FM pulse signal from the inverter 89.

The high gate counter 90 counts the clock pulse from the AND gate 87. The high gate counter 90 counts clock pulses while the FM pulse signal is at a high level. High gate counter 9
0 supplies the counted count values Q1 to Qn to the gate circuit 91.

The gate circuit 91 outputs a pulse to the RS flip-flop when the supplied count value reaches a predetermined value, for example, a value corresponding to half the minimum half cycle of the FM pulse signal. It is supplied to the set terminal of 92.

The low gate counter 93 has the same structure as the high gate counter 90, and the AND gate 88
Count clock pulses from. The low gate counter 93 counts clock pulses while the FM pulse signal is at a low level. Low gate counter 90
Supplies the lower bits Q1 to Qk of the counted count values Q1 to Qn to the gate circuit 94.

The gate circuit 94 outputs a pulse to the RS flip-flop when the supplied count value reaches a predetermined value, for example, a value corresponding to half the minimum half cycle of the FM pulse signal. It is supplied to the reset terminal 92.

In the RS flip-flop 92, when a pulse is input from the gate circuit 91 to the set terminal, Q
The output is supplied to the low gate counter 93 to start counting. When a pulse is input from the gate circuit 94 to the reset terminal, the inverted Q output is the high gate counter 90.
Is supplied to and starts counting. The Q output is supplied to the switching circuit 78, the high edge output circuit 99, and the low edge output circuit 102.

The high edge output circuit 99 supplies a pulse to the delay circuit 101 and a pulse to the latch circuit 96 in response to the rising edge of the Q output. Delay circuit 101
Delays the pulse from the high edge output circuit 99,
It is supplied to the counter circuit 95 and the OR gate 83.

The low edge output circuit 102 supplies a pulse to the delay circuit 103, and supplies a pulse to the latch circuit 98 in response to the falling edge of the Q output. Delay circuit 10
3 delays the pulse from the low edge output circuit 102 and supplies it to the counter circuit 97 and the OR gate 83.

The counter circuit 95 has a reset input and a carry output, and counts the clock pulse from the AND gate 88. The counter circuit 95 is FM
Clock pulses are counted while the pulse signal is at a low level. The counter circuit 95 has count values Q1 to Qn.
Is supplied to the latch circuit 96. In addition, the counter circuit 95
The count value of is cleared by the pulse from the delay circuit 101.

The latch circuit 96 latches the count value of the counter circuit 95 by the pulse from the high edge output circuit 99. The latched count value is supplied to the A input of the switching circuit 78.

The counter circuit 97 is the counter circuit 9 described above.
The configuration is the same as that of 5, and counts the clock pulses from the AND gate 87. The counter circuit 97 counts clock pulses while the FM pulse signal is at a high level. The counter circuit 97 supplies the count values Q1 to Qn to the latch circuit 98. The count value of the counter circuit 97 is cleared by the pulse from the delay circuit 103.

The latch circuit 98 latches the count value of the counter circuit 95 by the pulse from the low edge output circuit 102. The latched count value is supplied to the B input of the switching circuit 78.

FIG. 5 shows a timing chart of the signal processing circuit shown in FIG. 5A is an FM pulse signal, FIG. 5B is a clock pulse (CLK), and FIG. 5C is A.
ND gate 87, FIG. 5 (D) is an inverter 89, FIG.
5E shows an AND gate 88, FIG. 5F shows an R-SFF set input, FIG. 5G shows an R-SFF reset input, and FIG.
(H) is Q output, FIG. 5 (I) is inverted Q output, FIG. 5 (J)
Is a high edge output, FIG. 5 (K) is a low edge output, FIG.
(L) is the delayed pulse 101, and FIG. 5 (M) is the delayed pulse 1
03 is shown.

The FM pulse signal of FIG. 5A is supplied to the AND gate 87 and the inverter 89, and the clock pulse of FIG. 5B is supplied to the AND gates 87 and 88. The inverter in FIG. 5D shows a signal obtained by inverting the FM pulse signal in FIG. 5A. AND gate 87
Outputs a signal as shown in FIG. 5C by performing a logical product operation of the clock pulse and the FM pulse signal. The AND gate 88 integrates the clock pulse and the inverted signal of the FM pulse signal and outputs a signal as shown in FIG.

For example, the low gate counter 93 is AND
The clock pulse from the gate 88 is counted and the count value is supplied to the gate circuit 94. The gate circuit 94 is
When the count value reaches a constant value, a pulse is supplied to the reset input of the RS flip-flop 92.

At time t1, the low gate counter 9
3 has a count value reset when the inverted Q output becomes high level as shown in FIG. 5 (I), and a pulse is supplied to the reset input of the RS flip-flop 92 as shown in FIG. 5 (G). It Also, the high gate counter 90
Counts clock pulses from the AND gate 87 of FIG. 5C because the Q output of FIG. 5H is in the low level state.

At time t2, the counter circuit 97 is activated by the delay pulse from the delay circuit 103 shown in FIG.
The count value of is reset. The period from time t1 to t2 is the delay period T of the pulse output from the delay circuit 103.
It is 4.

At time t3, high gate counter 9
When the count value of 0 becomes a constant value, the count value becomes
It is supplied to the set input of the RS flip-flop 92 as shown in (F).

The RS flip-flop 92 sets the Q output of FIG. 5 (H) to the high level in response to the set input, and
The inverted Q output of (I) is set to low level. When the Q output becomes high level, the low gate counter 93
The clock pulse from the AND gate 88 in FIG. 5E is counted. In the high gate counter 90, Q
When the output becomes low level, the count value is reset.

Further, the high edge output of FIG.
Latch circuit 9 outputs a pulse according to the rising edge of the output
6, supplied to the delay circuit 101. The latch circuit 96 latches the count value of the counter circuit 95 according to the high edge output. The pulse delayed by the delay circuit 101 is output as shown in FIG.

At time t4, the counter circuit 9 is activated by the delay pulse 101 from the delay circuit 101 shown in FIG.
The count value of 5 is reset. The period from time t3 to t4 is the delay period T4 of the pulse output from the delay circuit 101.

At time t5, the low gate counter 9
When the count value of 3 reaches a constant value, the gate circuit 94 supplies a pulse to the reset input of the RS flip-flop 92.

The RS flip-flop 92 sets the Q output of FIG. 5 (H) to low level in response to the set input, and
The inverted Q output of (I) is set to high level. When the inverted Q output becomes high level, the high gate counter 90
Counts the clock pulses from the AND gate 87 of FIG. In the low gate counter 93, the count value is reset when the inverted Q output becomes low level.

Further, the low edge output of FIG.
Latch circuit 9 outputs a pulse according to the rising edge of the output
8, supplied to the delay circuit 103. The latch circuit 98 latches the count value of the counter circuit 97 according to the high edge output. The pulse delayed by the delay circuit 103 is output as shown in FIG.

At time t6, the counter circuit 9 is activated by the delay pulse 103 from the delay circuit 103 of FIG.
The count value of 7 is reset. The period from time t5 to t6 is the delay period T4 of the pulse output from the delay circuit 103.

The switching circuit 83 outputs the A input when the Q output is at the high level, and outputs the A input when the Q output is at the low level.
Switch to output input. That is, the delay circuit 10
The delay circuit 103 is switched to the A input by the signal from 1.
It switches to B input by the signal from.

According to this modification, the same operational effect as the signal processing circuit shown in FIG. 2 is obtained.

FIG. 6 shows a block diagram of a modification of the signal processing circuit shown in FIG. 7 shows a timing chart of the signal processing circuit shown in FIG. In the signal processing circuit shown in FIG. 6, the same components as those in FIG. 4 are designated by the same reference numerals and description thereof will be omitted. The signal processing circuit of this modification is
It differs from the signal processing circuit of FIG. 4 in that a high gate counter 90, a low gate counter 93, gate circuits 91 and 94, and a PLL circuit 105 and a delay circuit 104 are provided in place of the RS flip-flop 92. These PLL circuits 1
05, the delay circuit 104 will be described below.

The PLL circuit 105 includes a 90 ° phase comparison circuit 106 and a VCO (Voltage Controlled).
Oscillator) 107 and 1 / N division period 108
It consists of and. The PLL circuit 105 shown in FIG.
When the PLL input signal shown in (A) is supplied, the period shown in FIG.
The LL output signal is output. 90 ° phase comparison circuit 106
Compares the phases of the FM pulse signal and the output signal of the PLL circuit 105, and outputs the FM pulse signal so that the phase difference becomes 90 °. The FM pulse signal is supplied to the VCO 107. The VCO 107 generates a clock pulse having a predetermined frequency based on the supplied FM pulse signal.
The generated clock pulse is supplied to the 1 / N cycle 108. In the 1 / N division period 108, the clock pulse from the VCO 107 is divided by a predetermined division ratio (1 / N) and an FM pulse signal with a phase difference of 90 ° is output. 90 ° phase difference
The FM pulse signal is supplied to the delay circuit 104, the high edge output circuit 99, the low edge output circuit 102, and the 90 ° phase comparison circuit 106.

The delay circuit 104 delays the FM pulse signal supplied from the PLL 105 and supplies it to the switching circuit 78.

The count value of the counter circuit 95 is
It is cleared by the pulse from the delay circuit 103. The latch circuit 96 latches the supplied count value of the counter circuit 95 by the pulse from the low edge output circuit 102.

The count value of the counter circuit 97 is cleared by the pulse from the delay circuit 101. The latch circuit 98 outputs the supplied count value of the counter circuit 97 to
It is latched by the pulse from the high edge output circuit 99.

FIG. 7A shows an ideal PLL input signal (FM pulse signal), FIG. 7B shows a PLL output signal, and FIG. 7C.
Actual FM pulse signal (input signal), FIG. 7 (D) is a clock pulse, FIG. 7 (E) is an AND gate 87, FIG.
(F) is an inverter 89, and FIG. 7 (G) is an AND gate 8.
8, FIG. 7 (H) is a high edge output, FIG. 7 (I) is a delayed pulse 101, FIG. 7 (J) is a low edge output, and FIG. 7 (K).
Indicates a delayed pulse 103, and FIG. 7L shows a delayed pulse 104. Further, description of signals having the same timing as in FIG. 5 will be omitted.

When the PLL circuit 105 is supplied with the actual input signal of FIG. 7C, it outputs the PLL output signal of FIG. 7B.

At time t1, a pulse is output from the high edge output circuit 99 as shown in FIG. 7H in response to the PLL output signal of FIG. 7B. In response to this pulse, the latch circuit 98 latches the count value of the counter circuit 97.

At time t2, the counter circuit 9 responds to the pulse output from the delay pulse 101 of FIG. 7 (I).
7 is reset. After that, the counter circuit 97 again counts the clock pulse from the AND gate 87 shown in FIG.

At time t3, when the PLL output signal of FIG. 7 (B) becomes low level, a pulse is output from the low edge output circuit 102 in response to the fall of the PLL output signal as shown in FIG. 7 (J). . In response to this pulse, the latch circuit 96 latches the count value of the counter circuit 95.

At time t4, the counter circuit 9 responds to the pulse output from the delay pulse 103 in FIG. 7 (K).
5 is reset. After that, the counter circuit 95 again counts the clock pulse from the AND gate 88 shown in FIG.

The same operation is repeated at times t5 to t8.

The counter circuit 97 has a period (for example, time t2) until it is reset by the pulse of the delay circuit 101.
At t6), clock pulses in the positive polarity period of the input signal in FIG. 7C are counted.

The counter circuit 95 has a period (for example, time t4) until it is reset by the pulse of the delay circuit 103.
From t8 to t8, clock pulses in the negative period of the input signal in FIG. 7C are counted.

The delay circuit 104 supplies the switching circuit 78 with a signal whose polarity is inverted at the timing of resetting each counter circuit. The switching circuit 78 is switched by the signal from the delay circuit 104 to output the side on which the count value is latched. In this embodiment, the count value of the latch circuit 98 is output when the output signal of the delay circuit 104 has a positive polarity, and the count value of the latch circuit 96 is output when the output signal has a negative polarity. That is, at the timing when the counter circuit 97 is reset at time t2, the switching circuit 78 controls so that the count value latched at time t1 is output from the latch circuit 98. At the timing when the counter circuit 95 is reset at time t4, the switching circuit is controlled so that the count value latched at time t3 is output from the latch circuit 96.

As described above, in the present modification, the timing of counting the high and low periods is measured by generating the pulse whose phase is different from the input signal by 90 ° by the PLL circuit. According to this modification, since the count timing can be generated only by the PLL circuit, the circuit can be simplified as compared with the signal processing circuit shown in FIG.

[0142]

According to the signal processing circuit of the present invention, the positive and negative clock pulses of the input pulse signal are counted by independent counters, respectively, and the signal values are accurately processed by using the counted values. You can Further, a more accurate count value can be obtained without being affected by noise superimposed on an actual input signal. Therefore, it is possible to generate an accurate digital signal.

Further, the counting means for counting the clock pulses generates a timing signal and controls the input pulse signal based on this timing signal to make the pulse period constant and stabilize the signal processing. it can.

[0144]

[Brief description of drawings]

FIG. 1 is a block diagram of an optical disk device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a signal processing circuit according to an embodiment of the present invention.

FIG. 3 shows a timing chart of the signal processing circuit of the present invention.

FIG. 4 shows a block diagram of a modification of the signal processing circuit shown in FIG.

5 shows a timing chart of the signal processing circuit shown in FIG.

6 shows a block diagram of a modification of the signal processing circuit shown in FIG.

7 is a timing chart of the signal processing circuit shown in FIG.

FIG. 8 shows an ideal timing chart in a conventional signal processing circuit.

FIG. 9 shows a timing chart in a conventional ideal signal processing circuit.

FIG. 10 shows an actual FM-modulated signal and an enlarged view around the zero level.

FIG. 11 shows a timing chart in an actual signal processing circuit.

FIG. 12 shows a timing chart for removing conventional chattering.

[Explanation of symbols]

10, 30, 31, 32 Signal processing circuit 11 Double-edge detection circuit 12 counter circuit 13, 75, 76, 96, 98 Latch circuit 14 Digital LPF 15 FM modulation signal terminal 16 clock pulse terminals 17 Digital FM signal terminal 40 discs 41 Optical system 42 spindle motor 43 thread motor 44 laser driver 45 front monitor 46 ALPC 47 Memory compensation circuit 48 Wobble signal processing unit 49 RF amplifier 50 Focus / Tracking servo circuit 51 Feed servo circuit 52 Spindle servo circuit 53 CD encode / decode circuit 54 D / A converter 55 audio amplifier 56, 58 RAM 57 CD-ROM encode / decode circuit 59 Interface / Buffer Controller 60 CPU 61 Host computer 71 Positive gate 72 Negative positive gate 73, 97 Counter circuit (positive polarity) 74, 95 Counter circuit (negative polarity) 77, 92 RS flip-flop 78 Switching circuit 79 Digital LPF 80, 81, 82, 101, 103, 104 Delay circuit 83 OR gate 87, 88 AND gate 89 inverter 90 high gate counter 93 low gate counter 91, 94 Gate circuit 99 high edge output circuit 102 Low edge output circuit 100 optical disk device 105 PLL circuit 106 90 ° phase comparison circuit 107 VCO 108 1 / N frequency divider

Continued front page    F-term (reference) 5D044 FG30 GL02 GL50                 5J039 BA04 BB07 KK05 KK10 KK13                       KK23 MM16 NN01

Claims (14)

[Claims] 1. A signal processing circuit for generating a digital signal according to an input pulse signal, which outputs a clock pulse with either polarity during a predetermined period including at least one pulse of the input pulse signal. Pulse output means, counting means for counting the clock pulse, setting means for setting the predetermined period based on a predetermined count value in either polarity, and output digital based on the count value of the counting means A signal processing circuit comprising: an output unit that outputs a signal. 2. The clock pulse output means outputs a clock pulse when the input pulse signal has a positive polarity, and a clock pulse when the input pulse signal has a negative polarity. And a second clock pulse output means, wherein the counting means counts the clock pulses from the first clock pulse output means, and the second clock pulse output means. The signal processing circuit according to claim 1, further comprising a second counting unit that counts clock pulses. 3. The third counting means for counting the clock pulses from the first clock pulse output means, and the fourth counting means for counting the clock pulses from the second clock pulse output means. 3. The counter according to claim 2, further comprising a counting means, wherein the setting means sets the predetermined period based on predetermined count values of the third counting means and the fourth counting means. Signal processing circuit. 4. The third counting means outputs a first timing signal with the predetermined count value, and the fourth counting means outputs a second timing signal with the predetermined count value. 4. The signal processing circuit according to claim 3, wherein the setting unit outputs a signal that determines the predetermined period according to the first timing signal and the second timing signal. 5. The signal processing circuit according to claim 4, wherein the setting unit includes a flip-flop that is set by the first timing signal and reset by the second timing signal. 6. The signal processing according to claim 5, wherein one of the third counting means and the fourth counting means resets a count value in response to resetting of the flip-flop. circuit. 7. The output means includes up-edge output means for outputting a third timing signal in response to an up edge of the Q output of the flip-flop, and a fourth edge in response to a down edge of the Q output of the flip-flop. Down edge output means for outputting the timing signal, first latch means for latching the count value of the first counting means according to the fourth timing signal, and the first timing means for responding to the third timing signal. 7. The signal processing circuit according to claim 5, further comprising a second latch unit that latches the count value of the second count unit. 8. The output means delays the third timing signal to output a fifth timing signal, and first delay means delays the fourth timing signal to provide a sixth timing signal. And a second delay means for outputting, the first counting means is reset in response to the sixth timing signal, the second counting means, in response to the fifth timing signal The signal processing circuit according to claim 7, wherein the signal processing circuit is reset. 9. The output means outputs the first count value latched by the first latch means and the second count value latched by the second latch means in accordance with the output of the flip-flop. 9. The signal processing circuit according to claim 7, further comprising switching means for switching the output. 10. The output unit generates a phase difference pulse signal having a predetermined phase difference from the input pulse signal, and outputs a third timing signal in response to an up edge of the phase difference pulse signal. Up edge output means, a down edge output means for outputting a fourth timing signal in response to a down edge of the phase difference pulse signal, and a count value of the first counting means in response to the third timing signal 3. The signal according to claim 2, further comprising: first latching means for latching the count value, and second latching means for latching the count value of the second counting means according to the fourth timing signal. Processing circuit. 11. The output means delays the third timing signal to output a fifth timing signal, and delays the fourth timing signal to produce a sixth timing signal. And a second delay means for outputting, the first counting means is reset according to the fifth timing signal, the second counting means, according to the sixth timing signal The signal processing circuit according to claim 10, wherein the signal processing circuit is reset. 12. The output means includes a third delay means for delaying the output of the phase difference pulse signal and outputting a delayed phase difference pulse signal, wherein the output means includes the third delay means for outputting the delayed phase difference pulse signal. 2. A switching means for switching between the output of the first count value latched by the first latch means and the output of the second count value latched by the second latch means.
The signal processing circuit according to 0 or 11. 13. The signal processing circuit according to claim 1, wherein the output unit includes a digital low pass filter. 14. A signal processing method for generating a digital signal according to an input pulse signal, comprising: a clock for outputting a clock pulse with either polarity during a predetermined period including at least one pulse of the input pulse signal. A pulse output procedure, a counting procedure for counting the clock pulse, a setting procedure for setting the predetermined period based on a predetermined count value in one of the polarities, and an output digital based on the count value in the counting procedure. A signal processing method comprising an output procedure for outputting a signal.