JP2003318322A - Interposer substrate, its manufacturing method, semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having high mounting reliability. <P>SOLUTION: The semiconductor device (100) comprises: two or more wiring substrates (1, 2) having thermal expansion coefficients and areas different from each other and laminated so that the areas are sequentially reduced toward a side near a semiconductor bare chip (5) via a stress relaxing layer (3) disposed between the substrate (1) and the substrate (2) to form a circuit on an interposer substrate (41); one or a plurality of semiconductor bare chips (5) face-down mounted on the substrate (41) to relax a stress concentration at each mounting part when mounted on a mother board. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interposer substrate suitable for mounting a semiconductor bare chip, a method for manufacturing the same, a semiconductor device having the semiconductor bare chip mounted thereon, and a method for manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor device on which a semiconductor bare chip is mounted is used as a so-called LSI in various devices such as a server device, a router device, a base station device such as a mobile phone, and a mobile communication terminal. In order to reduce the size, increase the functionality, and reduce the weight of these devices, the number of pins and the pitch of semiconductor devices are increasing. Accordingly, as a semiconductor package, a CSP in which a semiconductor bare chip is flip-mounted on a package substrate (that is, an interposer substrate) having external terminals of PGA or BGA.
(Chip size package) and BGA package are becoming popular.

In semiconductor device mounting technology, it is important to maintain stable electrical connection between parts, that is, to secure mounting reliability. The deterioration of mounting reliability occurs, for example, when one component expands more than the other due to the action of heat or the like. When such a difference in expansion occurs, a force that tends to generate "warpage" in the semiconductor device is generated between the semiconductor bare chip and the interposer substrate, and the mounting portion (that is, the connecting portion that electrically connects the two components to each other) is generated. ) Is subjected to tensile stress and shear stress. In the case of general flip-chip mounting, electrical connection is made in the mounting portion via protruding electrodes called bumps, but the magnitude of the stress depends on the bonding strength between the bump and bare chip or between the bump and interposer substrate. If the strength of the bump material is higher than the material strength of the bump material itself, there is a high possibility that the mounting portion is broken and a connection failure occurs. In order to avoid such an inconvenience, various mounting structures have been adopted so that connection failure does not occur even under conditions where stress is concentrated on the mounting portion.

In general flip chip mounting,
In order to disperse the stress concentrated in the mounting portion in the surface direction, an underfill is injected into the primary mounting portion between the semiconductor bare chip and the interposer substrate to improve the mounting reliability. Further, in the case of a multi-pin LSI, the input / output pad pitch on the LSI must be narrowed, so that the bump shape used for the mounting portion must be reduced, and as a result, the stress absorption margin of the mounting portion tends to be small. It is known that the mounting reliability decreases. Therefore, the input / output pads on the LSI are arranged in a grid pattern so as to widen the pad pitch.
Thereby, the bump shape of the primary mounting portion can be increased, and the mounting portion can sufficiently absorb the stress. Also, 2 between the interposer board and the motherboard
In the secondary mounting portion, the packaging substrate is made of an organic material to reduce the difference in coefficient of thermal expansion from the motherboard, and by injecting an underfill into the secondary mounting portion, the secondary mounting portion The stress concentration is alleviated. As described above, in the conventional semiconductor package, the mounting reliability is ensured by the mounting structure.

[0005]

However, depending on the mounting structure, there is a limit to relieving the stress in the mounting portion. In particular, with regard to LSIs, it is considered that the number of pins and the pitch will be further narrowed in the future in order to further improve the functions (for example, improve the processing speed) and downsize the network computing devices. In that case, it is expected that it is difficult to sufficiently relieve the stress in each mounting portion from the semiconductor bare chip to the substrate (for example, a mother board) and to secure high mounting reliability by the above mounting structure. The present invention has been made in consideration of the trend of such an LSI, and an object of the present invention is to provide a semiconductor device having higher mounting reliability.

[0006]

In order to solve the above problems, the present invention provides an interposer substrate for mounting one or a plurality of bare semiconductor chips on an upper surface thereof.
The above wiring boards are laminated so that the stress relaxation layer is located between the adjacent wiring boards, and the adjacent wiring boards are electrically connected to each other to form a circuit. Each wiring board is a double-sided board or a multi-layer board, and in at least one combination of adjacent wiring boards, the wiring boards have different areas and one wiring board has the other wiring. Provided is an interposer substrate arranged on a side closer to an upper surface without protruding from the substrate.

The wiring board is a sheet-like member having two broad surfaces (main surfaces), which is conventionally adopted in the field of semiconductor devices. In the present specification, the “area” of the wiring board refers to the area of the main surface of the wiring board unless otherwise specified. Further, when referring to “area” with respect to other members, when it is a sheet-like member, it means the area of the main surface unless otherwise specified.

In the above, the "combination of adjacent wiring boards" is a combination of two wiring boards that are adjacent in the thickness direction. The “upper surface” is a surface on which a semiconductor bare chip is mounted, and is a surface far from the substrate when the semiconductor device is mounted on the substrate (for example, a mother board).
In the present specification, the direction approaching the upper surface is also referred to as “up” for convenience. On the other hand, the direction away from the upper surface is called "down".

The interposer substrate of the present invention is composed of two or more wiring substrates, and in at least one combination of adjacent wiring substrates, the wiring substrates have different areas and one wiring substrate is used. Are arranged above without being protruded from the other wiring board. Due to this feature, even if stress occurs due to the difference in the coefficient of thermal expansion between the semiconductor bare chip and the interposer substrate, in a combination of the wiring boards having different areas, the wiring board having a larger area alleviates the stress. That is, the interposer substrate itself has a stress relaxation structure. Therefore, in the semiconductor device manufactured by mounting the semiconductor bare chip on the upper surface of the interposer substrate of the present invention, warpage due to heating is unlikely to occur, and the mounting reliability in the primary mounting portion and the secondary mounting portion is ensured. Become.

The interposer substrate is preferably a side close to the upper surface without having one wiring substrate protruding from the other wiring substrate in all combinations of adjacent wiring substrates, the wiring substrates having different areas. Has a structure arranged in. With this structure, the stress is more relaxed. It can be said that the interposer substrate having this structure is a wiring substrate in which each wiring substrate has a different area, and the areas are laminated so that the area becomes smaller in order toward the top.

In a combination of adjacent wiring boards having different areas, the wiring boards are preferably selected so as to have different coefficients of thermal expansion. In the combination of two wiring boards having different areas, when the wiring boards have different coefficients of thermal expansion, the above stress relaxation effect is more effectively exhibited. Preferably, the wiring board having a smaller area has a smaller coefficient of thermal expansion.

In a combination of adjacent wiring boards, when the wiring boards have different coefficients of thermal expansion, the dimensional change caused when heat is applied differs from wiring board to wiring board. This causes stress to concentrate on the part that electrically connects. Further, in a combination of adjacent wiring boards, even if the two wiring boards have the same coefficient of thermal expansion, different dimensional changes may occur in each wiring board depending on the use conditions, and similar stress concentration may occur. To alleviate this stress concentration, in the interposer substrate of the present invention, a stress relaxation layer is provided between the wiring boards. The stress relaxation layer absorbs the stress concentration as internal stress, thereby maintaining good electrical connection between the wiring boards.

In the interposer substrate, each wiring substrate preferably has a different coefficient of thermal expansion. In that case, in the interposer substrate, it is preferable that the wiring substrates are laminated so that the coefficient of thermal expansion thereof becomes smaller toward the side closer to the upper surface. In other words, in the interposer substrate of the present invention, it is preferable to design and configure each wiring board so that the wiring board having a larger area has a larger coefficient of thermal expansion. When the coefficient of thermal expansion of the wiring board is configured to gradually decrease toward the top, the stress caused by heat is gradually relaxed,
The mounting reliability of a semiconductor device manufactured using this interposer substrate is further improved.

In the interposer substrate of the present invention,
Among the wiring boards forming the interposer board, the wiring board having the largest coefficient of thermal expansion preferably has the same or smaller thermal expansion coefficient than the board (eg, motherboard) on which the semiconductor device is mounted. . Further, in the interposer substrate of the present invention, among the wiring substrates forming the interposer substrate, the coefficient of thermal expansion of the wiring substrate having the smallest coefficient of thermal expansion is the coefficient of thermal expansion of the semiconductor bare chip (generally the coefficient of thermal expansion of silicon). It is preferable that the coefficient of thermal expansion be equal to or larger than that. That is, each wiring board is preferably selected so that its coefficient of thermal expansion is within the range of not less than the coefficient of thermal expansion of the bare semiconductor chip and not more than that of the board (for example, motherboard) on which the semiconductor device is mounted. By doing so, even if there is a large difference between the coefficient of thermal expansion of the mother board and the coefficient of thermal expansion of the semiconductor bare chip, the stress is gradually relaxed, so that a semiconductor device manufactured using this interposer substrate Mounting reliability is improved.

Here, the coefficient of thermal expansion of the wiring board, the board on which the semiconductor device is mounted, and the semiconductor bare chip are all measured with the wiring and the like formed. Therefore, even if the wiring board is formed using the same base material,
Note that the coefficient of thermal expansion differs depending on the material of the wiring, the wiring pattern, and the like.

Therefore, the wiring boards constituting the interposer substrate are sequentially arranged from the upper side to the first wiring board, the second wiring board, ..., And the thermal expansion coefficients thereof are β ₁ , β ₂ ,. ． ． ,
and beta _n, the coefficient of thermal expansion of the substrate beta _m, the thermal expansion coefficient of the semiconductor bare chip is taken as beta _c, they are, β _c ≦ β ₁ ≦
It is preferable to satisfy the relationship of β ₂ ≤ ... ≤β _n ≤β _m (where β _c <β _m ). More preferably,
The relationship of β _c ≦ β ₁ <β ₂ <···· <β _n ≦ β _m is satisfied.

In the interposer substrate of the present invention,
Of the wiring boards that form the interposer board, the area of the wiring board having the largest area is preferably the same as or smaller than the area of the board (for example, a mother board) on which the semiconductor device is mounted. Therefore, the wiring boards that form the interposer board are arranged in order from the top to the bottom.
The wiring board, the second wiring board, ..., And the area thereof is S ₁ , S ₂ ,. ． ． , S _n and the area of the substrate is S _m , they are S ₁ ≦ S ₂ ≦ ... ≦ S _n ≦ S
It is preferable to satisfy the relationship of _m (however, S _k <S _{k + 1} is satisfied in at least one combination among the combinations of the adjacent wiring boards). More preferably, S ₁ <S ₂
<... · <S _n ≤S _m is satisfied. If wiring boards are laminated so as to satisfy this relationship, the difference in stress generated in each wiring board when heated is gradually reduced, and warpage occurs in a semiconductor device manufactured using this interposer substrate. Is more suppressed.

In the interposer substrate, the electrical connection between the wiring substrates is ensured by the conductor provided in the through hole penetrating in the thickness direction in the stress relaxation layer. That is, the conductor in the through hole of the stress relaxation layer serves as an electrical connection portion between the wiring boards. The conductor is, for example, a metal lump, metal powder, metal particles, a conductive paste, or a bump formed on the surface of the wiring board. By using the conductor in such a form, it is possible to obtain a connection structure in which disconnection is unlikely to occur even when stress is applied to the electrical connection portion.

In the interposer substrate of the present invention, the stress relaxation layer is preferably made of an elastic material. Here, the elastic body has a tensile elastic modulus smaller than that of the wiring boards located above and below the elastic body. By using the elastic body as the stress relaxation layer, the stress concentration on the electrical connection portion between the wiring boards in the interposer substrate is further relaxed.

The present invention is a method of manufacturing the interposer substrate according to the present invention, wherein at least one wiring board has two or more double-sided boards whose area is different from the area of at least one other wiring board. Preparing a multi-layered substrate, two adjacent wiring boards, steps 1) to 5) below: 1) a step of forming a stress relaxation layer on one exposed surface of one wiring board, 2) a stress relaxation layer , A step of forming a through hole penetrating in the thickness direction, 3) a step of disposing a conductor in the through hole, 4) a step of disposing the other wiring substrate on the surface of the stress relaxation layer, 5) a stress relaxation layer At least one combination of the wiring boards positioned on both sides of the wiring board is joined and the two wiring boards are laminated and integrated by a process of electrically connecting the two wiring boards through a conductor, and at least one of the adjacent wiring boards is combined. In the wiring board have different areas from each other, and one wiring board to provide a manufacturing method of the interposer substrate to be laminated so as not to protrude from the other wiring substrate.

It is necessary to prepare two or more wiring boards so that the area of at least one wiring board is different from the area of at least one other wiring board in at least one combination of adjacent wiring boards. This is because the wiring boards have different areas, and one wiring board is stacked so as not to protrude from the other wiring board. The exposed surface of the wiring board means a surface on which the stress relaxation layer is not yet laminated.

According to this manufacturing method, an interposer substrate having a stress relaxation structure composed of two or more wiring substrates can be obtained. By mounting the semiconductor bare chip face down on the interposer substrate, a semiconductor device with high mounting reliability can be obtained.

The present invention also provides, as another method of manufacturing the interposer substrate of the present invention, two or more double-sided boards as wiring boards in which the area of at least one wiring board is different from the area of at least one other wiring board. Alternatively, a multilayer board is prepared, and two adjacent wiring boards are connected to each other by the following I) to
Step IV): I) a step of forming bumps made of a conductor on one exposed surface of one wiring board, II) a surface of the wiring board on which the bumps are formed, or one exposed surface of the other wiring board A step of forming a stress relaxation layer, III) a step of arranging the two wiring boards so as to face each other via a stress relaxation layer and a bump, and IV) joining the stress relaxation layer and wiring boards located on both sides thereof At the same time, the wiring boards are laminated and integrated by a process of electrically connecting the two wiring boards via the bumps, and in at least one combination of adjacent wiring boards, the wiring boards have different areas from each other, and Provided is a method for manufacturing an interposer substrate, in which one wiring board is laminated so as not to protrude from the other wiring board. According to this manufacturing method, the bumps are penetrated through the stress relaxation layer, whereby the wiring boards located on both sides of the stress relaxation layer can be electrically connected. That is, this manufacturing method does not require a step of forming a through hole in the stress relaxation layer, and thus enables the interposer substrate to be easily manufactured.

The present invention also provides a semiconductor device in which one or more semiconductor bare chips are mounted face down on the interposer substrate of the present invention. Further, the present invention is a method for manufacturing the semiconductor device, wherein the interposer substrate is manufactured by the manufacturing method according to the present invention, and a semiconductor is formed on an upper surface of the interposer substrate, that is, a surface of a wiring board having a smaller area. Provided is a method for manufacturing a semiconductor device, which includes mounting a bare chip face down.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described. Each wiring board forming the interposer board is a double-sided board or a multilayer board. The double-sided board is a board having wiring layers on two main surfaces, and the multilayer board is a board having wiring layers on both main surfaces and having one or more wiring layers between them.

In the interposer substrate, in at least one of the combinations of adjacent wiring substrates, the area of one wiring substrate is smaller than that of the other wiring substrate. Therefore, in the interposer substrate of the present invention, for example, the lower two of the three wiring substrates have the same area, and the wiring substrate located on the uppermost side has a smaller area than the other wiring substrates, And the three wiring boards, the upper two have the same area, and the lowermost one has a larger area than the upper two. When the interposer board is composed of two wiring boards, there is only one combination of adjacent wiring boards, and therefore the area of one wiring board is always smaller than the area of the other wiring board. Preferably, in a combination of adjacent wiring boards, the area of the wiring board having a small area is 2.5 to 100% of the area of the wiring board having a large area, and more preferably 30 to 100% of the area of the wiring board having a large area. Is.

Preferably, in the interposer substrate, each wiring substrate has a different area and is laminated so that the area becomes smaller toward the side closer to the upper surface. Even in that case, in each combination of adjacent wiring boards, a wiring board having an area corresponding to preferably 2.5 to 100%, and more preferably 30 to 100% of the area is provided on the wiring board having a large area. It is preferably located.

In a combination of adjacent wiring boards having different areas, a wiring board having a smaller area is arranged without protruding from a wiring board having a larger area. By arranging so, 2
Even when the two wiring boards are deformed differently (for example, due to thermal expansion), the area of the large wiring board that does not overlap with the small wiring board serves as a release area to effectively relieve the stress.

Preferably, in a combination of adjacent wiring boards having different areas, the wiring boards are similar to each other, and the wiring boards have corresponding sides with the same orientation, and between the sides. It is arranged so that the distance is constant.
That is, it is preferable that the two wiring boards have the same shape, and that the wiring boards having a smaller area are stacked evenly on the wiring board having a larger area. The similar surface is the main surface of the wiring board.

Specifically, when the adjacent wiring boards are circular, the two wiring boards may be arranged so that their centers coincide with each other. When adjacent wiring boards are square or rectangular, it is preferable to arrange them so that the centers thereof coincide with each other and the directions of the respective sides coincide with each other. An example of such an interposer substrate is shown in FIG. 8 in a plan view seen from above. Figure 8
In the interposer substrate shown in, each wiring substrate (8
1, 82, 83) has a square main surface, and in each combination (81 and 82, 82 and 83) of adjacent wiring boards, the directions and centers (C) of the four sides of each wiring board are equal to each other. I am doing it.

As described above, in the combination of adjacent wiring boards having different areas, the wiring boards preferably have different coefficients of thermal expansion. In that case, it is preferable that the wiring board having a smaller area has a smaller coefficient of thermal expansion. The coefficient of thermal expansion is JIS C
Using the standard condition defined in 0010 as the measurement environment, JP
It is measured according to CA-BU01 (1998) and is generally expressed in ppm / ° C.

As described above, in the interposer substrate, the wiring substrates are preferably laminated so that the coefficient of thermal expansion thereof becomes smaller toward the side closer to the upper surface. The coefficient of thermal expansion of the wiring board differs depending on the material forming the wiring board and the like. Therefore, for the interposer substrate, the material of the wiring substrate is selected so that the adjacent wiring substrates have a desired difference in coefficient of thermal expansion, and the wiring substrate made of the selected material has a smaller area as it is stacked on the upper side. It is advisable to design and create the wiring board so that the wiring boards thus formed are laminated.

The wiring board can be arbitrarily selected from those conventionally used as semiconductor package boards. Specifically, it is composed of a composite resin substrate obtained by impregnating a core material formed of inorganic or organic fibers in a woven or non-woven fabric with a resin, a ceramic substrate, or a material in which a resin and an inorganic filler are mixed. Examples of the wiring board include a composite board and a flexible board using a film. Examples of the composite resin substrate include a glass epoxy substrate (for example, FR4 substrate obtained by impregnating glass woven fabric with FR4 epoxy resin), an aramid epoxy substrate, a glass polyphenylene ether substrate, and a glass-modified cyanate ester substrate. The structure of each wiring board is not particularly limited, and the wiring board may be, for example, an aramid epoxy substrate having an all-layer IVH structure (this wiring board is also referred to as “ALIVH (registered trademark) board”).

As described above, the coefficient of thermal expansion of each wiring board is preferably between the coefficient of thermal expansion of the semiconductor bare chip and the coefficient of thermal expansion of the substrate (for example, a mother board) on which the semiconductor device is mounted. The coefficient of thermal expansion of silicon, which is the main material of the semiconductor bare chip, is 2.5 ppm / ° C. Also, the board generally used as a mother board is FR
4 substrates, the coefficient of thermal expansion of which is 10 to 20 ppm / ° C. Therefore, when the semiconductor device is mounted on a motherboard, the coefficient of thermal expansion of each wiring board is 2.5.
It is preferably in the range of ppm / ° C to 20ppm / ° C.

In the interposer substrate, a stress relaxation layer is provided between the wiring boards. As described above, the stress relaxation layer is preferably made of an elastic body. The meaning of the elastic body is as described above, and preferably,
As for the tensile elastic modulus Es of the elastic body, the elastic modulus Eu and Eb (Eu <Eb) of the wiring boards located above and below the elastic elastic body
In the case of, the relationship of Es ≦ 0.5 × Eu is satisfied. More preferably, the tensile modulus of elasticity of the elastic body is smaller than the tensile modulus of elasticity of any of the wiring boards forming the interposer substrate. Since the tensile modulus of elasticity of the wiring board varies depending on the material of the wiring board and the like, the material preferably used as the elastic body also varies depending on the wiring board that constitutes the interposer substrate.

It is preferable that the elastic body does not deteriorate even when heat is applied when the semiconductor device is mounted on a mother board or the like, or when the mounted semiconductor device is used. Therefore, the elastic body preferably contains a cured product of a thermosetting resin and / or an ultraviolet curable resin. Alternatively, as long as the elastic body does not soften at the temperature when the semiconductor bare chip is mounted on the interposer substrate, the temperature when the semiconductor device is reflow-mounted on the motherboard (for example, 260 ° C.), and the temperature when the semiconductor device is used. It may contain a thermoplastic resin.

In consideration of the above matters, an appropriate elastic body is selected according to the combination of the wiring boards adjacent in the vertical direction to form the stress relaxation layer. For example, ALIVH substrates typically have a tensile modulus of about 7500 MPa, and FR4
The substrate generally has a tensile modulus of about 13000 MPa. Therefore, in the combination of the ALIVH board and the FR4 board, the elastic body positioned between them is 30 to 5
It preferably has a tensile elastic modulus of 000 MPa. Such an elastic body is, for example, a polyimide-modified epoxy resin (tensile elastic modulus after curing: about 30 to 60 MP).
a), epoxy-modified polyimide resin (tensile elastic modulus after curing: about 700 to 2500 MPa) and methallyl-maleimide resin (tensile elastic modulus after curing: about 500 MPa).

Each of the elastic bodies exemplified above is a thermosetting or ultraviolet curable resin having a considerably small tensile elastic modulus. Therefore, ALIVH board and FR
Not only the combination of the four substrates, but also any combination selected from the other wiring substrates exemplified above is preferably used as the constituent material of the stress relaxation layer located therebetween.

The elastic body may include a filler made of a non-conductive material. By mixing the filler made of a non-conductive material into the elastic body, the tensile elastic modulus and the thermal expansion coefficient of the elastic body can be adjusted. The filler made of a non-conductive material is, for example, silicon oxide (SiO 2).
₂ ) Powders, needles or granules made of an inorganic substance such as ₂ ), or powders, needles or granules made of an organic substance such as a cured epoxy resin. The mixing amount of the filler made of a non-conductive material is preferably 30 wt% or less. If the amount of the filler mixed is too large, the viscosity of the elastic body becomes high, molding becomes difficult, the adhesion to the wiring board deteriorates, and the tensile modulus of the elastic body becomes too large.

It is preferable that the area of the stress relaxation layer is an area necessary for bonding the wiring boards located above and below the wiring board to fix the wiring boards. Specifically, the wirings located above and below the stress relaxation layer. It suffices if the area of the board is the same as that of the wiring board having a small area. The area of the stress relaxation layer may be larger than that of a wiring board having a small area. In other words, the stress relaxation layer may protrude from the wiring board having a small area. However,
When the stress relaxation layer contains a thermosetting resin, when the stress relaxation layer is bonded to the wiring board by heating and pressing as described later, the thermosetting resin of the stress relaxation layer protruding from the wiring board having a small area is sufficient. Care must be taken to cure it.

The thickness of the stress relaxation layer is not particularly limited and is, for example, about 15 to 20 μm. However, if the thickness of the stress relaxation layer becomes large, the thickness of the entire semiconductor device becomes large, which may be disadvantageous in terms of downsizing. If the stress relaxation layer is too thin, the stress concentration on the electrical connection between the wiring boards may not be sufficiently relaxed.

In the interposer board, the wiring boards are electrically connected in a predetermined manner,
At least one circuit (or network) is formed on the interposer substrate as a whole. As described above, the wiring boards are electrically connected by the conductor arranged in the through hole of the stress relaxation layer.

Specifically, the conductor is Cu, Ag, A
Cu, Ag, Au, Cu-Ag, a lump of metal selected from u, Cu-Ag alloy, and Ag-plated Cu.
Powder or granular material consisting of an alloy and a metal selected from Ag-plated Cu, that is, metal powder or metal particles, a conductive paste containing the metal powder, and Cu, Ag formed on the surface of the wiring board. Au, Cu-A
It is preferably either a g-alloy or a bump made of a metal selected from Ag-plated Cu. The conductive paste may be one that is commonly used in the art, and for example, one in which Ag-plated Cu powder is pasted with an epoxy resin can be used. The conductive paste exists in the final product in a state where the resin in the paste is hardened. The bumps are formed on the surface of the wiring board by plating, printing or transfer of a conductive paste, or stud bump bonding applying a wire bonding technique.

Both conductors are preferably brought into pressure contact with the upper and lower wiring boards, and a part thereof may be brought into pressure contact with the wiring boards. This is to ensure an electrically good connection between the wiring boards. Therefore, the metal mass is
It is preferable that the original shape is flattened by being crushed by being pressed in the vertical direction between the wiring boards. Such a metal lump is, for example, an oblate sphere (or spheroid) formed by crushing a metal sphere.
As for the metal sphere, the ratio of the major axis to the minor axis becomes 2 or more,
It is preferably flattened. The metal powder, metal particles, or conductive paste is also preferably connected between the wiring boards while being compressed in the through holes. The state in which the metal powder is compressed can be generated, for example, by filling the through-hole with the metal powder so as to project from the end surface of the through-hole and pressurizing the through-hole in the vertical direction. The same applies to the metal particles and the conductive paste. Even when the wiring boards are electrically connected by the bumps formed on the surface of the wiring board, it is preferable that the tips of the bumps are pressed against the wiring board and are in contact with the opposing wiring board in a crushed state. .

The interposer substrate may be composed of two wiring boards or may be composed of three or more wiring boards. In any case, it is necessary to design the circuit by selecting the wiring pattern of each wiring board and the position and number of conductors between the wiring boards so that an interposer board having a desired circuit can be obtained. . The lower surface of the wiring board located at the lowermost side of the interposer board serves as a mounting surface on a motherboard or the like. This mounting surface is preferably formed so as to form a package in which electrodes are arranged in a grid pattern on the back surface of the package, for example, PGA or BGA.

The semiconductor device of the present invention comprises a bare semiconductor chip face down mounted on the upper surface of the interposer substrate described above. That is, in the semiconductor device of the present invention, the semiconductor bare chip is face-down mounted on the surface of the wiring board having the smallest area among the wiring boards constituting the interposer board. The number of mounted semiconductor bare chips may be one or plural. The semiconductor bare chip is SB
Face down mounting is performed by a conventional method selected from the B method, the C4 method using solder bumps, the ACF method using an anisotropic conductive adhesive, and the like. In addition, underfill may be injected between the semiconductor bare chip and the interposer substrate in order to reduce the concentration of stress on the face-down mounting portion, as is commonly done.

The present invention is applied to various semiconductor devices. The semiconductor device obtained by the present invention is particularly useful as an LSI used in a server device, a router device, a base station device such as a mobile phone, and a mobile communication terminal.

The interposer substrate of the present invention itself has a stress relaxation structure. Therefore, according to the semiconductor device of the present invention obtained by using this, the stress concentration on the primary mounting portion and the secondary mounting portion is higher than in the conventional case where the stress is relaxed only by underfill. Will be alleviated. Therefore, the semiconductor device of the present invention exhibits higher mounting reliability.

Here, a more specific form of the interposer substrate of the present invention will be described with reference to the drawings in the form of a semiconductor device having a semiconductor bare chip mounted on its upper surface.

FIG. 1 is a schematic sectional view showing a first embodiment of a semiconductor device of the present invention. In the semiconductor device (100) shown in FIG. 1, a semiconductor bare chip (5) is face-down mounted on an interposer substrate (41) composed of a first wiring substrate (1) and a second wiring substrate (2). It is a thing. A stress relaxation layer (3) is interposed between the first wiring board (1) and the second wiring board (2).
The first wiring board (1) and the second wiring board (2) are electrically connected by a conductor (6a) arranged in a hole (9) penetrating the stress relaxation layer (3). . In the illustrated embodiment, the conductor (6a) is a metal oblate sphere.

The thermal expansion coefficients β ₁ and β _{2 of} the first wiring board (1) and the second wiring board (2) are β ₁ ≠ β _2.
And the areas S ₁ and S ₂ are S ₁ <
The relationship of S ₂ is satisfied. The coefficient of thermal expansion of the two wiring boards is β
It is preferable to satisfy the relationship of ₁ <β ₂ and β _c ≦ β ₁ <
It is more preferable to satisfy the relationship of β ₂ ≦ β _m (β _c is the coefficient of thermal expansion of the bare semiconductor chip, and β _m is the coefficient of thermal expansion of the substrate on which the semiconductor device is mounted).

An appropriate combination of the first wiring board / second wiring board is selected from the above-exemplified wiring boards so as to satisfy these relationships. When the illustrated semiconductor device is mounted on a mother board (FR4 board), the combination of the first wiring board / second wiring board is AL.
Aramid epoxy substrate / glass epoxy substrate such as IVH substrate (coefficient of thermal expansion: 6 to 11 ppm) / FR4 substrate (coefficient of thermal expansion: 10 to 20 ppm), ceramic substrate (coefficient of thermal expansion: 4 to 8 ppm) / ALIVH substrate, ceramic A board / FR4 board etc. are illustrated. The first wiring board / second wiring board combination may be a combination of homogeneous composite substrates having different thermal expansion coefficients. As illustrated, when only one semiconductor bare chip is mounted, S ₁ is preferably larger than the area of the semiconductor bare chip (for example, 64 mm ² ). Further, it is preferable that S ₂ is smaller than the area of the motherboard (for example, 2500 mm ² ).

In the illustrated embodiment, the stress relaxation layer (3) located between the first wiring board (1) and the second wiring board (2) is made of an elastic body. As described above, a polyimide-modified epoxy resin is used as the elastic body.
In the illustrated embodiment, the stress relaxation layer (3) has a thickness of 15
It is about 20 μm.

In the illustrated embodiment, between the first wiring board (1) and the second wiring board (2) is made of copper arranged in the through hole (9) of the stress relaxation layer (3). It is electrically connected by a flat ball (6a). Oblate (6a) is
A sphere having a diameter of 45 to 50 μm is flattened by being pressed in the vertical direction to have a short diameter of 30 μm and a long diameter of 60 μm, and the upper and lower portions are embedded in the wiring board. The shape of the through hole (9) has a diameter of 70 μm when formed.
However, in the final semiconductor device, as shown in the figure, the shape of the through-hole (9) is oblate (6).
It has the same contour as in a). As will be described later, when the sphere is flattened (6a) and the stress relaxation layer (3) and the first and second wiring boards (1, 2) are bonded together, when heat and pressure are applied. This is because the resin forming the stress relaxation layer once melted and adhered to the oblate sphere.

The semiconductor bare chip (5) is attached to the interposer substrate (41) by face-down mounting. In the illustrated embodiment, only one semiconductor bare chip (5) is mounted, but two or more semiconductor bare chips (5) may be mounted.

FIG. 2 is a schematic sectional view showing a second embodiment of the semiconductor device of the present invention. In FIG. 2, FIG.
The reference numerals used in Table 1 represent the same elements as they represent in FIG. In the semiconductor device (200) shown in FIG. 2, in the interposer substrate (42), the conductor (6b) electrically connecting the first wiring board (1) and the second wiring board (2) is conductive. It is the same as the semiconductor device shown in FIG. 1 except that it is a paste. Conductive paste (6
In b), Ag-plated Cu powder is pasted with an epoxy resin. Conductive paste (6b)
Are filled in the through hole (9) in a compressed state. Further, the epoxy resin in the conductive paste is hardened in the final product.

FIG. 3 is a schematic cross-sectional view showing a third embodiment of the semiconductor device of the present invention. In FIG. 3, FIG.
The reference numerals used in Table 1 represent the same elements as they represent in FIG. In the semiconductor device (300) shown in FIG. 3, in the interposer substrate (43), the conductor (6c) electrically connecting the first wiring board (1) and the second wiring board (2) is A bump formed on the surface of one wiring board (1), and a stress relaxation layer (3),
Except that the elastic body potted (that is, dropped) on the surface of the second wiring board (2) is formed by being spread by being pressed by the first wiring board (1). It is the same as the semiconductor device shown by 1.

The bump (6c) is made of Au and is formed by plating. The dimensions when formed are
The diameter was 50 μm and the height was 40 μm. In the illustrated final product, the bumps (6c) are crushed in the thickness direction by pressurization to have a height of about 20 to 30 μm.
The stress relaxation layer (3) has a portion exposed from the first wiring board (1) due to its formation method.

FIG. 4 is a schematic sectional view showing the fourth embodiment of the semiconductor device of the present invention. In FIG. 4, FIG.
And the reference numbers used in FIG. 2 represent the same elements as they represent in FIGS. In the semiconductor device (400) shown in FIG. 4, the interposer substrate (44)
Are three wiring boards, namely the first wiring board (11),
Second wiring board (12) and third wiring board (13)
The wiring boards are electrically connected by a conductive paste (6b).

First, second, and third wiring boards (1
1, 12, 13) is the coefficient of thermal expansion β ₁, Β_TwoAnd β
_ThreeAre different from each other and their area S₁, S_TwoOh
And S _ThreeIs S₁<S_Two<S_ThreeMeet the relationship. β₁, Β
_TwoAnd β_ThreeBut preferably β ₁<Β_Two<Β_ThreeRelationship
Satisfy, more preferably β₁, Β_TwoAnd β_ThreeWill be
Also β_cAbove β_mWhat follows is that the first embodiment is
As described in relation to.

An appropriate combination of three wiring boards is selected from the wiring boards exemplified above so as to satisfy these relationships. When the illustrated semiconductor device is mounted on a mother board (FR4 board), a ceramic board (coefficient of thermal expansion:
4 to 8 ppm) / ALIVH substrate / FR4 substrate can be exemplified. As shown in the figure, when only one semiconductor bare chip is mounted, S ₁ is equal to or larger than the area of the semiconductor bare chip. Further, S ₃ is preferably smaller than the area of the motherboard.

The configuration between the first wiring board (11) and the second wiring board (12) and the configuration between the second wiring board (12) and the third wiring board (13) are both shown in FIG. It is the same as the configuration between the first wiring board (1) and the second wiring board (2) shown in FIG. Therefore, its explanation is omitted.

Needless to say, the semiconductor device shown in FIGS. 1 to 4 is merely an example of a preferred embodiment of the present invention, and various other embodiments can be applied. For example, the wiring boards illustrated in FIGS. 1 to 4 are both double-sided boards, but each wiring board may be a multilayer board. Further, the interposer substrate may be formed by stacking four or more wiring substrates.

Next, a method of manufacturing the interposer substrate of the present invention and a method of manufacturing the semiconductor device of the present invention using the manufacturing method will be described. In the first method of manufacturing the interposer substrate of the present invention, stacking and integration of two adjacent wiring substrates are performed by the steps 1) to 5). When the semiconductor bare chip is mounted on the surface of the interposer substrate (the surface of the wiring substrate having the smallest area) thus formed, the semiconductor device of the present invention is manufactured. A method for manufacturing a semiconductor device of the present invention, including the first method for manufacturing an interposer substrate of the present invention, will be described below with reference to the drawings.

6A to 6F, the interposer substrate (41) is formed by using the first wiring board (1) and the second wiring board (2) as two adjacent wiring boards, respectively. Furthermore, each step of the method of manufacturing the semiconductor device of the form shown in FIG. 1 by mounting a semiconductor bare chip is shown. In FIG. 6, (a) corresponds to step 1) of forming a stress relaxation layer on one exposed surface of one wiring board,
(B) corresponds to step 2) of forming a through hole penetrating in the thickness direction in the stress relaxation layer, (c) corresponds to step 3) of disposing a conductor in the through hole, and (d) shows stress. Corresponding to the step of exposing the surface of the relaxation layer (that is, part of step 1),
(E) corresponds to step 4) of arranging the other wiring board on the surface of the stress relaxation layer, and (f) joins the stress relaxation layer and the wiring boards located on both surfaces thereof, and through a conductor. This corresponds to step 5) of electrically connecting the two wiring boards. FIG. 6G corresponds to the step of face-down mounting the semiconductor bare chip on the surface of the interposer substrate.

FIG. 6A schematically shows the step of forming the stress relaxation layer (3) on one exposed surface of the second wiring board (2) having a larger area. In the step of forming the stress relaxation layer (3), a composite sheet (2) obtained by forming a layer of an elastic body (3) having a constant film thickness on a carrier film (7).
It is a step of heating and laminating 1) on the surface of the second wiring board (2). In the embodiment shown, the carrier film (7) is a 9 μm thick film made of PEN (polyethylene naphthalate). The carrier film may be made of PET (polyethylene terephthalate). The thickness of the carrier film is 9 μm
It is not limited to this, and is appropriately selected depending on the size of the through hole formed in the through hole forming step described later.

The layer of the elastic body (3) is formed by coating the surface of the carrier film (7) with the elastic body dispersed or dissolved in a solvent and evaporating the solvent. When the elastic body is a resin that is cured by heat, etc., the elastic body is
It is uncured when applied to a carrier film. Evaporation of the solvent may be carried out using a drying oven or may be carried out by natural drying. The layer thickness of the uncured elastic body (3) is determined according to the thickness of the stress relaxation layer to be finally obtained. Therefore, in the semiconductor device shown in FIG. 1, the thickness of the stress relaxation layer is set to 15 to 20 μm as described above.
In the case of m, the thickness of the uncured elastic body layer is preferably about 20 μm in consideration of compression of the elastic body layer in the step described later.

In the heat lamination, when the elastic body is a thermosetting resin, the thermosetting resin is not cured.
It is preferable to carry out at a temperature at which tackiness occurs.
When the elastic body is a polyimide-modified epoxy resin, the heat lamination is preferably performed at 80 to 120 ° C. The uncured elastic body (3) is temporarily bonded onto the second wiring board (2) by heat lamination. The use of the composite sheet has advantages that a stress relaxation layer is easily formed, a stress relaxation layer having a uniform thickness is formed, and a through hole is easily formed later.

In the illustrated embodiment, the composite sheet (21) has the first wiring board (1) laminated thereon.
(See (e) of FIG. 6).

FIG. 6B schematically shows a step of forming a through hole (9) penetrating in the thickness direction in the stress relaxation layer (3). By forming the through hole (9), the surface wiring (8) of the second wiring board (2) is exposed. The through hole is formed at an appropriate position of the stress relaxation layer according to the wiring patterns of the first and second wiring boards so that a desired circuit is formed on the interposer substrate. Further, the through hole is formed so as to have a size such that a conductor is placed therein to ensure electrical connection. Through hole is 500μ
cylindrical with a diameter of up to m, preferably 20-100
It is formed in a cylindrical shape having a diameter of μm. As shown in the figure, when a metal sphere is arranged as a conductor, the through hole (9)
Is larger than the diameter of the metal sphere (eg 45-50 μm), preferably slightly larger (eg 70 μm).
m) is formed into a cylindrical shape.

In the illustrated embodiment, the through hole (9) is
Formed on the stress relief layer (3) in the form of a composite sheet (21). That is, the through hole (9) is formed so as to penetrate the carrier film (7) as well. Through hole (9)
Are formed by a processing method that is conventionally adopted as a hole forming process, such as an ultraviolet laser process.

FIG. 6C schematically shows the step of disposing the conductor (6a) in the through hole (9). In the illustrated embodiment, the conductor (6a) arranged in the through hole (9).
Is a metal ball (copper ball). One metal sphere is arranged for each through hole.

Subsequently, the carrier film (7) of the composite sheet (21) is peeled off to obtain the state shown in FIG. 6 (d). 6D corresponds to the step of exposing the surface of the uncured elastic body (3), and it can be said that the formation of the stress relaxation layer (3) is part of the step. In the illustrated embodiment, by peeling off the carrier film (7), the metal spheres (6a) are projected from the surface of the layer of the elastic body (3) (that is, the end surface of the through hole (9)). Metal ball (6
The protruding part of a) is the "pushing margin". The portion corresponding to the "pushing margin" is the first wiring board (1) described later.
Are crushed in the step of stacking and pressing, whereby the metal spheres (6a) are compressed in the through holes (9), and a state of being pressed against both wiring boards is formed.

When wiring boards are connected using metal powder, metal particles or conductive paste instead of metal balls, the whole of the through-holes formed in the composite sheet are filled with metal powder, metal particles or conductive paste. Then, when the carrier sheet is peeled off, a state in which the metal powder, the metal particles or the conductive paste is swollen from the end surface of the through hole is obtained. In that state, when the first wiring substrate is laminated and pressed as described later, a state in which the metal powder, the metal particles or the conductive paste is compressed can be created. As a method of filling the through holes with metal powder, metal particles or conductive paste, there is a squeezing method.

FIG. 6E shows a step of disposing the first wiring board (1) on the surface of the stress relaxation layer (3). The first wiring board (1) is aligned so as to obtain a desired connection. As the alignment method, for example, the first wiring board (1) and the second wiring board (2) should be aligned by horizontally offsetting each other by an offset distance (direction parallel to the main surface). A method of exposing a surface and using a pair of cameras to recognize and align a part of a wiring pattern of each board facing each other, and an electromagnetic wave (X
There is a method of recognizing the wiring pattern of each wiring board by lines or infrared rays and the like and performing alignment.

FIG. 6 (f) shows that the stress relaxation layer (3) is bonded to the first wiring board (1) and the second wiring board (2) and that the conductor (6a) is interposed therebetween. A step of electrically connecting the first wiring board (1) and the second wiring board (2) will be described. In the step shown in FIG. 6F, after the aligned first wiring board (1) is placed on the elastic body which is the stress relaxation layer (3) and temporarily fixed using the adhesiveness of the elastic body. It is carried out by heating and pressurizing in vacuum. In the case of heating, when the elastic body is a thermosetting resin, the elastic body is cured so as to be between the first wiring board (1) and the stress relaxation layer (3) and the second wiring board (2). And the stress relaxation layer (3). Pressurization is performed by pressing a conductor (here, a metal ball) (6a) against the wiring board,
It is carried out to obtain a stable electrical connection between wiring boards. At this time, since the elastic body is melted by heat, the original shape of the through hole (9) disappears, and the elastic body near the through hole (9) adheres to the conductor (6a). As a result, the shape of the through hole (9) becomes the same as the contour of the conductor (6a).

The heating temperature is set to a temperature required for hardening the elastic body. Further, the heating and pressurization may be performed using a hot platen. When the elastic body contains an ultraviolet curable resin component in addition to the thermosetting resin component, it is irradiated with ultraviolet rays while applying pressure to electrically connect the wiring boards, and at the same time, the ultraviolet curable resin component is used. It is possible to employ a method in which the stress relaxation layer and each wiring board are bonded to a certain extent, and then, in order to complete the bonding between the stress relaxation layer and each wiring board, heating is performed to cure the thermosetting resin component. According to this method, it is not necessary to use a heating plate, and the pressurizing step and the heating step can be performed separately. As a method of irradiating ultraviolet rays while applying pressure, for example, a method of irradiating ultraviolet rays through a pressure jig using a pressure jig made of an ultraviolet-transparent material,
Alternatively, a method of irradiating ultraviolet rays from the side of the wiring board may be used. The heating is performed using a suitable heat treatment device (for example, a heating furnace).

The pressure at the time of pressurization is set to the pressure necessary to bring the conductor (6a) into pressure contact with the wiring board. For example, to make a metal sphere having a diameter of 45 to 50 μm as shown in the drawing into a flattened sphere having a short diameter of 30 μm and a long diameter of 60 μm,
A pressure of ~ 20 MPa is required. When using metal powder or conductive paste as a conductor instead of metal balls,
A pressure of 5-20 MPa is required to compress them. This pressure range is smaller than the pressure required to make the metal sphere into an oblate sphere. Therefore, if the interposer substrate is manufactured using the metal powder or the conductive paste, the residual strain in the interposer substrate can be further reduced.

The steps shown in FIGS. 6A to 6F correspond to the steps of the method for manufacturing the interposer substrate 41. The semiconductor device of the present invention can be obtained by mounting a semiconductor bare chip face down on the interposer substrate obtained through these steps. FIG. 6G shows a mounting process of the semiconductor bare chip (5). In the illustrated embodiment, the semiconductor bare chip (5) is mounted by SBB via the bumps (10). An underfill (22) is injected between the semiconductor bare chip (5) and the interposer substrate (41). The method for mounting the semiconductor bare chip (5) is not limited to SBB, and may be the other conventional mounting method described above, such as C4 or ACF.

The interposer substrate manufacturing method described above is a manufacturing method including a step of forming a through hole in the stress relaxation layer and a step of disposing a conductor in the formed through hole. Next, a manufacturing method that does not require those steps will be described as a second method of manufacturing the interposer substrate of the present invention. In the second method of manufacturing the interposer substrate of the present invention, stacking and integration of two adjacent wiring substrates are carried out by the above steps I) to IV).
A method of manufacturing a semiconductor manufacturing apparatus of the present invention including a second method of manufacturing an interposer substrate of the present invention will be described below with reference to the drawings.

7 (a) to 7 (e), an interposer substrate (43) is formed by using the first wiring board (1) and the second wiring board (2) as two adjacent wiring boards, respectively. Furthermore, each step of the method of manufacturing a semiconductor device of the form shown in FIG. 3 by mounting a semiconductor bare chip is shown. In FIG. 7, (a) corresponds to step I) of forming bumps made of a conductor on one exposed surface of one wiring board, and (b) shows a stress relaxation layer on one exposed surface of the other wiring board. (C) corresponds to step III) in which the two wiring boards are arranged so as to face each other via the stress relaxation layer and the bump, and (d) corresponds to the stress relaxation layer and its While joining the wiring boards located on both sides,
Process of electrically connecting two wiring boards via bumps
Equivalent to IV). FIG. 7E corresponds to the step of face-down mounting the semiconductor bare chip on the surface of the interposer substrate.

FIG. 7A schematically shows a step of forming bumps (6c) on the surface of the first wiring board (1).
In the illustrated embodiment, the bump (6c) is made of Au and is formed by a plating method. The diameter of the protrusion (6c) is about 50 μm, and the height is about 40 μm. The material, forming method and size of the bump (6c) are not limited to these, and the bump may be formed by appropriately combining the metal (Cu etc.) and the method (printing method etc.) exemplified above.

FIG. 7B schematically shows the step of forming the stress relaxation layer (3) on the surface of the second wiring board (2). In the illustrated embodiment, the stress relaxation layer (3) is a liquid thermosetting resin (eg, polyimide-modified epoxy resin).
The uncured elastic body is formed by potting. Therefore, as shown in the figure, in this state, the thickness of the stress relaxation layer (that is, the elastic body) (3) is not constant. The stress relaxation layer (3) becomes a layer having a substantially constant thickness by the pressing step described later. The amount of the elastic body to be potted is determined according to the thickness of the stress relaxation layer to be finally obtained. Alternatively, the stress relief layer may be formed on the surface of the second wiring substrate in the form of a composite sheet, as described above with reference to FIG. Alternatively, the stress relaxation layer may be formed on the bump forming surface of the wiring board on which the bumps are formed, that is, on the bump forming surface of the first wiring board (1).

In FIG. 7C, the second wiring board (2) and the first wiring board (1) are arranged so as to face each other via the stress relaxation layer (3) and the bump (6c). It is a process to do. The first wiring board (1) is aligned so as to obtain a desired connection on the interposer board. The alignment method is as described above with reference to FIG.

FIG. 7 (d) shows that the stress relaxation layer (3) is bonded to the first wiring board (1) and the second wiring board (2) and the bumps (6c) are used. The process of electrically connecting the first wiring board (1) and the second wiring board (2) is shown. The step shown in FIG. 7D is performed by bringing the first wiring board (1) into contact with the elastic body which is the stress relaxation layer (3) and then heating and pressing the same. The heating cures the elastic body, which is a thermosetting resin, between the first wiring board (1) and the stress relaxation layer (3) and between the second wiring board (2) and the stress relaxation layer (3). ) Is carried out to join between. Pressurized by potted elastic body (3)
As a layer having a substantially constant thickness, and bumps (6
c) is penetrated into the elastic body (3), and the bump (6
It is carried out so that the tip of c) is brought into pressure contact with the second wiring board (2). That is, in this process, the stress relaxation layer (3) is bonded to the wiring boards (1, 2) and the through hole (9) is formed.
And the wiring boards (1, 2) are electrically connected to each other.

The heating temperature is set to a temperature required for hardening the elastic body. The heating and pressing may be performed using a hot platen. When the elastic body contains an ultraviolet curable resin in addition to the thermosetting resin, ultraviolet irradiation, pressurization, and heating can be performed in the same manner as the method described with reference to FIG.

The pressure at the time of pressurization is such that the bumps (6c) penetrate the elastic body (3) and surely the first wiring board (1).
And the second wiring board (2) are electrically connected to each other. Therefore, the pressure is appropriately set according to the material and size of the bump (6c). As shown in the figure, on the surface of the first wiring board (1), a diameter of about 50 μm,
When the Au bumps (6c) having a height of about 40 μm are formed, the bumps (6c) are crushed to have a height of about 20 to 30 μm by applying pressure in the vertical direction at 5 to 20 kPa. Further, due to the pressure, the elastic body (3) is layered between the first wiring board (1) and the second wiring board (2), and its thickness is almost the same as the height of the bump (6c). Become.

The steps shown in FIGS. 7A to 7D are steps for manufacturing the interposer substrate 43, and semiconductor bare chips are mounted face down on the interposer substrate obtained through these steps. The process of mounting the semiconductor bare chip (5) on the interposer substrate (43)
It shows in (e) of FIG. This step is the same as that described with reference to FIG. 6G, and thus the description thereof is omitted here.

This manufacturing method is advantageous in terms of manufacturing cost because it does not require a step of forming a through hole in the stress relaxation layer. Further, as shown in the figure, when the stress relaxation layer is formed by potting a liquid elastic body, the step of processing the elastic body into a sheet-like material such as a composite sheet can be omitted, so that the cost is reduced, and A semiconductor device can be manufactured with higher manufacturing efficiency. Further, according to this manufacturing method, since a material that is not in the form of a sheet (for example, a liquid material) can be used, the range of selection of materials can be widened, and therefore the structure of the interposer substrate can be diversified.

The manufacturing method described above with reference to FIGS. 6 and 7 relates to a manufacturing method of forming the interposer substrate with two wiring substrates. The interposer substrate composed of three or more wiring substrates is shown in FIGS.
7 or the steps shown in FIGS. 7A to 7D are repeated.

For example, in the first manufacturing method described with reference to FIG. 6, when another wiring board is laminated, the first wiring board (1) and another wiring formed thereon are stacked. A board is defined as two adjacent wiring boards, and
The step (f) is repeated. In the step 1), the upper surface of the first wiring board (1) shown in FIG. 6 (f) or one surface of another wiring board to be laminated thereon is used as an exposed surface,
It is performed by forming a stress relaxation layer on the exposed surface.

Similarly, in the second manufacturing method described with reference to FIG. 7, when another wiring board is laminated, the first wiring board (1) and another wiring board formed on the first wiring board (1) are stacked. As the two wiring boards adjacent to the wiring board, (a) to
The step (d) is repeated. In step I), the upper surface of the first wiring board (1) shown in FIG. 7D or one surface of another wiring board to be laminated thereon is used as an exposed surface,
This is performed by forming bumps on the exposed surface.
In the step II), when bumps are formed on the upper surface of the first wiring board (1), a stress relaxation layer is formed on the upper surface of the first wiring board or one exposed surface of another wiring board. When bumps are formed on the surface of another wiring board, the stress relaxation layer is formed on the upper surface of the first wiring board or the bumped surface of another wiring board. To do.

FIGS. 6 and 7 exemplarily show the form of the preferred manufacturing method. Various other forms may be adopted in each step. For example, although double-sided boards are shown as the first and second wiring boards in FIGS. 6 and 7, one or both wiring boards may be multilayer boards. The stress relaxation layer may be formed on the surface of the first wiring board (that is, the wiring board having a small area).

FIG. 5 shows the semiconductor device (100) shown in FIG.
A mode in which is mounted on a mother board (110) is schematically shown in a sectional view. The semiconductor device (100) is a semiconductor bare chip (5) electrically connected to an interposer substrate (41) through a primary mounting portion (10). The semiconductor device (100) includes a mother board (110). ) To 2
It is electrically connected through the next mounting part (120).
In the illustrated embodiment, the underfill (13) is also provided between the semiconductor device (100) and the mother board (110).
0) is injected to alleviate the stress concentration on the secondary mounting portion.

[0095]

The interposer substrate of the present invention comprises a plurality of wiring substrates, and among the combinations of adjacent wiring substrates,
In at least one combination, the wiring boards have different areas, and one wiring board is arranged on the side close to the upper surface without protruding from the other wiring board. When a semiconductor device in which a semiconductor bare chip is mounted on the upper surface of an interposer substrate having this characteristic is mounted on a motherboard, stress concentration on each mounting part from the semiconductor bare chip to the motherboard is sufficiently relaxed, resulting in excellent mounting reliability. It is possible to obtain a mounting body having properties. Therefore, the present invention is particularly preferably applied to the manufacture of a multi-pin narrow pitch LSI.

[Brief description of drawings]

FIG. 1 is a cross-sectional view schematically showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a sectional view schematically showing a second embodiment of the semiconductor device of the present invention.

FIG. 3 is a cross-sectional view schematically showing a third embodiment of the semiconductor device of the present invention.

FIG. 4 is a sectional view schematically showing a fourth embodiment of the semiconductor device of the present invention.

5 is a cross-sectional view schematically showing a state in which the semiconductor device shown in FIG. 1 is mounted on a mother board.

FIG. 6A to FIG. 6G schematically show respective steps of manufacturing the semiconductor device of the first embodiment.

7A to 7E schematically show respective steps of manufacturing the semiconductor device of the third embodiment.

FIG. 8 is a top view schematically showing an example of the interposer substrate of the present invention.

[Explanation of symbols]

1, 11 ... First wiring board, 2, 12 ... Second wiring board, 13 ... Third wiring board, 3 ... Stress relaxation layer (elastic body), 41, 42, 43, 44 ... Interposer substrate, 5 ... Semiconductor bare chip, 6a, 6b, 6c ... Conductor, 7 ... Carrier film, 8 ... Surface wiring, 9 ... Through hole, 10. .. Bump (primary mounting part), 21 ... Composite sheet, 22 ... Underfill, 100, 200, 30
0,400 ... Semiconductor device, 110 ... Motherboard, 1
20 ... Secondary mounting part, 130 ... Underfill, 81,
82, 83 ... Wiring board.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hideki Azumaya             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd.

Claims (25)

[Claims] 1. An interposer substrate for mounting one or a plurality of semiconductor bare chips on an upper surface thereof, wherein two or more wiring substrates have a stress relaxation layer positioned between adjacent wiring substrates. To form a circuit by electrically connecting adjacent wiring boards to each other, and each wiring board is a double-sided board or a multi-layer board. In at least one combination, the wiring boards have different areas, and one wiring board is arranged on the side closer to the upper surface without protruding from the other wiring board. 2. In all combinations of adjacent wiring boards, the wiring boards have different areas, and one wiring board is arranged on the side closer to the upper surface without protruding from the other wiring board. The interposer substrate according to claim 1. 3. In the combination of adjacent wiring boards having different areas, the wiring boards are similar to each other, and the wiring boards have the corresponding directions of the corresponding sides, and the respective sides are the same. The interposer substrate according to claim 1 or 2, wherein the interposer substrate is arranged so that a distance therebetween is constant. 4. The interposer substrate according to claim 1, wherein in the combination of the adjacent wiring boards having different areas, the wiring boards have different coefficients of thermal expansion. 5. The interposer substrate according to claim 1, wherein each wiring substrate has a different coefficient of thermal expansion. 6. The wiring board is laminated such that the coefficient of thermal expansion thereof decreases in order toward the upper surface.
The interposer substrate described in. 7. The coefficient of thermal expansion of the wiring board having the smallest coefficient of thermal expansion is equal to or larger than the coefficient of thermal expansion of the semiconductor bare chip, and the coefficient of thermal expansion of the wiring board having the largest coefficient of thermal expansion is: The interposer substrate according to any one of claims 1 to 6, which has a coefficient of thermal expansion equal to or smaller than a coefficient of thermal expansion of a substrate on which a semiconductor device is mounted. 8. The interposer substrate according to claim 1, wherein the area of the wiring board having the largest area is equal to or smaller than the area of the board on which the semiconductor device is mounted. 9. The stress relieving layer has a through-hole penetrating in the thickness direction, and a conductor arranged in the through-hole electrically connects the wiring boards. The interposer substrate according to claim 1. 10. The conductor is a lump of metal, metal powder, metal particles,
The interposer substrate according to claim 9, which is a conductive paste or a bump formed on a surface of a wiring substrate. 11. The interposer substrate according to claim 9, wherein the conductor is made of metal and is a flattened sphere having a ratio of the major axis to the minor axis of 2 or more. 12. The interposer substrate according to claim 9, wherein the conductor is a bump formed on the surface of the wiring substrate by plating, printing or transfer of a conductive paste, or stud bump bonding. 13. The stress relaxation layer is made of an elastic material.
The interposer substrate according to any one of 1 to 12. 14. The elastic body has a tensile elastic modulus of 50% or less of a tensile elastic modulus of a wiring substrate having a larger tensile elastic modulus among wiring substrates located on both sides of the elastic body. Interposer board. 15. The interposer substrate according to claim 13, wherein the elastic body has a tensile elastic modulus smaller than that of all wiring substrates. 16. The interposer substrate according to claim 13, wherein the elastic body contains a cured product of a thermosetting resin and / or an ultraviolet curable resin. 17. The interposer substrate according to claim 13, wherein the elastic body contains a filler made of a non-conductive material. 18. A method of manufacturing an interposer substrate, wherein the area of at least one wiring board is different from the area of at least one other wiring board as the wiring board.
The above double-sided board or multilayer board is prepared, and two adjacent wiring boards are subjected to the following steps 1) to 5): 1) A step of forming a stress relaxation layer on one exposed surface of one wiring board, 2) a step of forming a through hole penetrating the stress relaxation layer in the thickness direction, 3) a step of disposing a conductor in the through hole, 4) a step of disposing the other wiring substrate on the surface of the stress relaxation layer, 5 ) Bonding the stress relieving layer and the wiring boards located on both sides thereof, and laminating and integrating the two wiring boards by a process of electrically connecting the two wiring boards via a conductor, and among the combinations of the adjacent wiring boards, In at least one combination, a method for manufacturing an interposer substrate, wherein wiring boards have different areas, and one wiring board is stacked so as not to protrude from the other wiring board. 19. The method 3) is carried out by disposing a metal ball having a diameter smaller than the diameter of the through hole in the through hole, and the method 5) is performed by applying pressure in the thickness direction of the stress relaxation layer. The method of manufacturing an interposer substrate according to claim 18, wherein the interposer substrate is manufactured by forming a metal sphere into a flattened sphere and contacting the two wiring substrates with pressure. 20. The above 1) is performed using an elastic body containing a thermosetting resin and / or an ultraviolet curable resin, and the above 5) is performed by curing the resin.
A method of manufacturing an interposer substrate according to claim 18 or 19. 21. A method of manufacturing an interposer substrate, wherein the area of at least one wiring board is different from the area of at least one other wiring board as the wiring board.
The above double-sided board or multi-layered board is prepared, and two adjacent wiring boards are subjected to the following steps I) to IV): I) A step of forming a bump made of a conductor on one exposed surface of one wiring board. , II) A step of forming a stress relaxation layer on the bump-formed surface of the wiring board or on one exposed surface of the other wiring board, III) The two wiring boards are opposed to each other via the stress relaxation layer and the bump. IV) The stress relieving layer and the wiring boards located on both sides thereof are joined together, and the two wiring boards are electrically connected through the bumps so that they are laminated and integrated, and are adjacent to each other. In at least one combination of wiring boards, the wiring boards have different areas, and one wiring board is stacked so that it does not protrude from the other wiring board. Method of manufacturing a plate. 22. The step IV) is performed by applying pressure in the thickness direction of the stress relaxation layer so that the bump penetrates into the stress relaxation layer and the tip of the bump is pressed against the wiring board. 21. A method for manufacturing an interposer substrate according to item 21. 23. The step I) is performed using an elastic body containing a thermosetting resin and / or an ultraviolet curable resin, and the step IV) is performed by curing the resin.
A method for manufacturing an interposer substrate according to claim 21 or 22. 24. A semiconductor device in which one or a plurality of semiconductor bare chips are face-down mounted on an interposer substrate, wherein the interposer substrate is the interposer substrate.
7. The interposer substrate according to any one of 7 above,
A semiconductor device in which a semiconductor bare chip is mounted on the upper surface. 25. A method of manufacturing a semiconductor device, comprising forming an interposer substrate by the method according to claim 18, and forming one or a plurality of bare semiconductor chips on an upper surface of the interposer substrate. A method of manufacturing a semiconductor device including face-down mounting.