JP2003318296A - Semiconductor device and its fabricating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, and its fabricating method, in which floating effect of a substrate is controlled. <P>SOLUTION: The semiconductor device 1000 comprises an isolation region 14, an n-type field effect transistor 100, and an npn-type bipolar transistor 200 fabricated on an SOI substrate 10. A p-type body region 50a and an n-type source region 120 are connected electrically. The p-type body region 50a and a p-type base region 220 are connected electrically. An n-type drain region 130 and an n-type collector region 230 are connected electrically. The n-type source region 120 and an n-type emitter region 210 are isolated structurally. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a field effect transistor and a bipolar transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art A MOS field effect transistor having an SOI structure is driven at lower power consumption and a higher speed than an ordinary MOS field effect transistor. FIG. . A buried oxide film 1100 made of a silicon oxide film is formed on the silicon substrate 2000. A source region 1200 and a drain region 1300 are formed on the buried oxide film 1100. Buried oxide film 1100
Above the source region 1200 and the drain region 1
A body region 1400 is formed between the two and 300. A gate electrode 1500 is formed on the body region 1400 via a gate insulating film.

The body region 1400 of this MOS field effect transistor is in a floating state. Therefore, the carriers generated by the impact ionization phenomenon are accumulated in the body region 1400. When carriers are accumulated in body region 1400, the potential of body region 1400 changes. A phenomenon called the so-called substrate floating effect occurs. The substrate floating effect causes a kink phenomenon and a history effect in the MOS field effect transistor.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which the floating body effect is suppressed and a method for manufacturing the same.

[0005]

(Semiconductor Device) (a) A first semiconductor device of the present invention comprises an insulating layer, a semiconductor layer formed on the insulating layer, and a semiconductor layer formed in the semiconductor layer. An element isolation region and an element formation region defined by the element isolation region are included, and at least one of the element formation regions includes both a bipolar transistor and a field effect transistor, and at least a source region and a drain. A body region formed between the drain region and the source region, the body region and the source region are electrically connected, the body region and the base region are electrically connected, and the drain The region and the collector region are electrically connected to each other, and the source region and the emitter region are structurally separated from each other.

(B) A second semiconductor device of the present invention comprises an insulating layer, a semiconductor layer formed on the insulating layer, an element isolation region formed in the semiconductor layer, and the element isolation region. A defined element formation region, and at least one of the element formation regions includes both a bipolar transistor and a field effect transistor, wherein the bipolar transistor includes a first conductivity type emitter region and a second conductivity type emitter region. Type base region and a first conductivity type collector region, the field effect transistor includes a gate electrode layer, a first conductivity type source region, and a first conductivity type drain region, and A first second formed at least between the source region and the drain region
A first conductivity type body region and the source region are electrically connected, and the first second conductivity type body region and the base region are electrically connected to each other. Electrically connected, the drain region and the collector region are electrically connected, and the source region,
It is structurally separated from the emitter region.

According to the semiconductor device of the semiconductor device of the present invention, the occurrence of the substrate floating effect can be suppressed.
That is, it is possible to prevent the threshold voltage from changing and the occurrence of kinks and history effects.

The first semiconductor device of the present invention can take any one of the following aspects (1) and (2).

(1) Further, there is a first electrode layer continuous to a side portion of the gate electrode layer and reaching the element isolation region, and the gate electrode layer is formed so as to straddle the element formation region. The source region is formed in a first region surrounded by the gate electrode layer, the first electrode layer, and the element isolation region in the field effect transistor formation region, and the gate electrode layer is formed. The drain region and the collector region are formed in a second region surrounded by the element isolation region, the gate electrode layer in the bipolar transistor formation region, the first electrode layer, and the device In a third region surrounded by the isolation region, the emitter region is formed,
A mode in which the first second conductivity type body region is formed at least below the gate electrode layer in the field effect transistor formation region and below a part of the first electrode layer.

(2) Further, it has a first layer and a second layer, and one end of the first layer is continuous with the gate electrode layer or the second layer and the other end The end reaches the element isolation region, the second layer has one end continuous with the gate electrode layer or the first layer, and the other end reaches the element isolation region, the gate In a first region surrounded by the electrode layer, the first layer, and the element isolation region,
The source region is formed, the drain region and the collector region are formed in a second region surrounded by the gate electrode layer, the second layer, and the element isolation region, and the first layer and the collector region are formed. In a third region surrounded by a second layer and the element isolation region, the emitter region is formed, under a part of the first layer, and the second region.
The base region is formed in the semiconductor layer below a part of the first layer, and the first second conductivity type body region is at least below the gate electrode layer and below a part of the first layer. The aspect formed in.

Further, the semiconductor device of the present invention can take at least one of the following modes (3) to (8).

(3) A mode having a first conductivity type body region, wherein the first conductivity type body region is formed in a semiconductor layer between the base region and the collector region.

(4) Further, a second conductivity type impurity diffusion layer is formed, and the second conductivity type impurity diffusion layer is a semiconductor layer in the first region, and the source region and the first region. Of the second conductive type body region, the source region and the first second conductive type body region are electrically connected to each other via the second conductive type impurity diffusion layer. Connected to.

(5) A contact layer for electrically connecting the second conductivity type impurity diffusion layer and the source region is formed, and the contact layer is the second conductivity type impurity diffusion layer and the contact layer. A mode in which it is formed so as to straddle the source region.

(6) A mode in which a second second conductivity type body region is formed in the semiconductor layer between the collector region and the emitter region, in the semiconductor layer in the vicinity of the element isolation region.

(7) A mode in which the first conductivity type is n-type and the second conductivity type is p-type, or the first conductivity type is p-type and the second conductivity type is Is an n-type.

(8) The semiconductor layer is a silicon layer.

(C) A third semiconductor device of the present invention comprises an insulating layer, a semiconductor layer formed on the insulating layer, an element isolation region formed in the semiconductor layer, and the element isolation region. A defined element formation region, at least one of the element formation regions includes both a bipolar transistor and a field effect transistor, and a gate electrode layer is formed on the semiconductor layer. A layer is formed so as to extend over the element formation region, a first electrode layer is formed on the semiconductor layer, and one end of the first electrode layer is closer to the gate electrode layer side. A first end which is continuous with the gate electrode layer, the first electrode layer, and the element isolation region in the field effect transistor formation region. Small area A first first-conductivity-type impurity diffusion layer is formed at least in part, and a second first-conductivity-type impurity diffusion layer is formed in a second region surrounded by the gate electrode layer and the element isolation region. A layer is formed, and a third first-conductivity-type impurity diffusion layer is formed in a third region defined by the gate electrode layer, the first electrode layer, and the element isolation region in the formation region of the bipolar transistor. A layer is formed, and a first second conductivity type body region is formed below the gate electrode layer and the first electrode layer in a formation region of the field effect transistor,
A first electrode is provided below the gate electrode layer and the first electrode layer in the formation region of the bipolar transistor and along the periphery of the third first-conductivity-type impurity diffusion layer.
Second conductivity type impurity diffusion layer is provided, and the first second type impurity diffusion layer is provided.
The conductivity type body region and the first first conductivity type impurity diffusion layer are electrically connected to each other, and the first second conductivity type body region and the first second conductivity type impurity diffusion layer are connected to each other. Are electrically connected.

(Method for Manufacturing Semiconductor Device) (a) A first method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including an insulating layer and a semiconductor layer formed on the insulating layer. And a step (A) of forming an element isolation region in the semiconductor layer to define the element formation region, and a step (B) of forming a field effect transistor and a bipolar transistor in the same element formation region.
In the semiconductor layer in at least a part of the gate electrode layer to be formed region and the first electrode layer to be formed region, the step (B) includes (B-1) at least the first second conductivity type body. A step of forming a region, and (B-2) a step of forming the gate electrode layer and the first electrode layer on the semiconductor layer, wherein the first electrode layer is the gate electrode layer. Continuing on the side, reaching the element isolation region,
(B-3) In the semiconductor layer in the third region surrounded by the gate electrode layer in the formation region of the bipolar transistor, the first electrode layer, and the element isolation region, an impurity diffusion layer of the second conductivity type is formed. The step of forming, (B-4) heat treatment is performed to thermally diffuse the impurity diffusion layer of the second conductivity type to form a semiconductor layer below the first gate electrode layer and below the first electrode layer. And forming a base region of the bipolar transistor, the base region and the first region
Electrically connecting the second conductivity type body region of
(B-5) At least a part of the first region surrounded by the gate electrode layer, the first electrode layer, and the element isolation region in the field effect transistor, the field effect transistor having: Forming a source region of the first conductivity type, (B-6) first conductivity of the field effect transistor in a part of a second region surrounded by the gate electrode layer and the element isolation region. Type drain region, (B-7) forming a first conductivity type collector region of the bipolar transistor in a part of the second region, and (B-8) the third region. Forming a first conductivity type emitter region of the bipolar transistor, and (B-9) electrically connecting the first second conductivity type body region and the source region. Including.

(B) A second method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including an insulating layer and a semiconductor layer formed on the insulating layer. The method includes a step (C) of forming an element isolation region and defining the element formation region, and a step (D) of forming a field effect transistor and a bipolar transistor in the same element formation region. , (D-1) a step of forming a first second conductivity type body region in at least the semiconductor layer in the region where the gate electrode layer is to be formed and the region where the first layer is to be formed, (D-2) the semiconductor A step of forming a gate electrode layer on the layer, (D-3) a step of forming a first layer on the semiconductor layer, wherein one end of the first layer is the Continue to the gate electrode layer or the second layer, etc. End of the reaches the isolation region,
(D-4) a step of forming a second layer on the semiconductor layer, wherein one end of the second layer is continuous with the gate electrode layer or the first layer, and the other Reach an element isolation region, and (D-5) in the semiconductor layer of the third region surrounded by the first layer, the second layer, and the element isolation region, the second conductivity Forming an impurity diffusion layer of the second type, and performing heat treatment (D-6) to thermally diffuse the impurity diffusion layer of the second conductivity type so as to be under the first layer and the second layer. Forming a base region of the bipolar transistor in the lower semiconductor layer and short-circuiting the base region and the first second conductivity type body region; (D-7) the gate electrode layer and the first region. Of the field effect type transistor in at least a part of the first region surrounded by the first layer and the element isolation region. Forming a source region of the first conductivity type in the transistor, (D-8) forming a part of a second region surrounded by the gate electrode layer, the second layer and the element isolation region, A step of forming a first conductivity type drain region of the field effect transistor, (D-9) a part of a second region surrounded by the gate electrode layer, the second layer and the element isolation region Forming a collector region of the first conductivity type in the bipolar transistor, and (D-10) a third region surrounded by the first layer, the second layer and the element isolation region. In the step of forming a first conductivity type emitter region of the bipolar transistor, and (D-11) electrically connecting the first second conductivity type body region and the source region.

A second semiconductor device manufacturing method of the present invention is
Further, the method may include a step of forming a second second conductivity type body region in a semiconductor layer below the second layer in the element formation region, the semiconductor layer being in the vicinity of the element isolation region. .

The first and second semiconductor device manufacturing methods of the present invention can have the following aspects.

(1) A mode in which the first conductivity type is n-type and the second conductivity type is p-type, or the first conductivity type is p-type and the second conductivity type is Is an n-type.

(2) A mode in which the semiconductor layer is a silicon layer.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings.

[Semiconductor Device] (Structure of Device) The semiconductor device according to the embodiment will be described below. FIG. 1 is a plan view schematically showing the semiconductor device of this embodiment. FIG. 2 is a plan view schematically showing a layer in which the gate electrode layer is formed and a plane of the semiconductor device below the layer. FIG. 3 is a plan view schematically showing the plane of the semiconductor device in the layer in which the semiconductor layer is formed. Specifically, the configurations of the impurity diffusion layer and the body region are shown. In FIG. 3, the downward slanting slanted line region indicates an n-type region, and the downward slanting slanted line region indicates a p-type region. FIG. 4 is a cross-sectional view schematically showing a cross section taken along the line AA in FIG. FIG. 4 is a cross-sectional view schematically showing a cross section of a field effect transistor. FIG. 5 is a cross-sectional view schematically showing a cross section taken along the line BB in FIG. FIG. 6 shows C in FIG.
It is sectional drawing which shows the cross section along the -C line typically. Figure 6
FIG. 4 is a cross-sectional view schematically showing specifically the cross section of a bipolar transistor. FIG. 7 shows an equivalent circuit of this embodiment. 1 to 3, the thick diagonally shaded area indicates the element isolation area.

The semiconductor device 1000 is shown in FIGS.
As shown in FIG. 6, it has an SOI substrate 10. The SOI substrate 10 has a semiconductor layer 10a formed on an insulating layer 10b. A field effect transistor (MOS transistor) 100 and a bipolar transistor 200 are formed in the semiconductor layer 10a.

Element isolation regions 14 are formed in predetermined regions of the semiconductor layer 10a. The element formation region 16 is defined by the element isolation region 14. Field-effect transistor 100 and bipolar transistor 2
00 are formed in the same element formation region 16. The field effect transistor 100 is n-type and the bipolar transistor 200 is npn-type.

The field effect transistor 100 has a gate electrode layer 110 and an n-type source region 1 as shown in FIG.
20 and an n-type drain region 130. As shown in FIG. 6, the bipolar transistor 200 has an n-type emitter region 210, a p-type base region 220, an n-type body region 52a, and an n-type collector region 230.
Hereinafter, the configurations of the field effect transistor 100 and the bipolar transistor 200 will be specifically described.

First, referring to FIG. 2, gate electrode layer 11
The layer in which 0 is formed will be described. The gate electrode layer 110 is
It is formed so as to straddle the element formation region 16 with a gate insulating layer (not shown in FIG. 2) 140 interposed therebetween. Specifically, the gate electrode layer 110 extends from the element isolation region 14 through the element formation region 16 to the element isolation region 14 again. A first electrode layer 60 is formed on a side portion of the gate electrode layer 110. First electrode layer 60
Are connected to the gate electrode layer 110. The first electrode layer 60 is formed on a predetermined region of the element formation region 16 and extends to the element isolation region 14. The first electrode layer 60 and the gate electrode layer 110 are integrally formed.

Next, the layer in which the semiconductor layer 10a is formed will be described with reference to FIGS. Of the region surrounded by the gate electrode layer 110, the first electrode layer 60, and the element isolation region 14, the region on the side where the field effect transistor 100 is formed is the first region A10, and the bipolar transistor 200 is used. The region on the side where is formed is referred to as a third region A30. Part of the semiconductor layer 1 in the first region A10
An n-type source region 120 is formed at 0a. n
The type source region 120 is composed of an n-type impurity diffusion layer.

A region surrounded by the gate electrode layer 110 and the element isolation region 14 is referred to as a second region A20. An n-type drain region 130 is formed in a part of the semiconductor layer 10a of the second region A20. In addition, the second area A2
In a part of 0, the n-type collector region 230 is formed. n-type drain region 130 and n-type collector region 2
30 is configured to be electrically connected to each other.
Specifically, each of the n-type drain region 130 and the n-type collector region 230 is composed of an n-type impurity diffusion layer, and these n-type impurity diffusion layers are continuously formed integrally with each other.

An n-type emitter region 210 is formed in the third region A30. n-type emitter region 210
Is composed of an n-type impurity diffusion layer. The n-type emitter region 210 is formed apart from the n-type source region 120. That is, the n-type emitter region 210 is n
It is structurally separated from the mold source region 120.

In the element forming region 16, the third region A
A base region 220 is formed below the gate electrode layer 110 and the first electrode layer 60 adjacent to 30. The base region 220 is composed of a p-type impurity diffusion layer. The base region 220 is the n-type emitter region 2
It is formed along the circumference of 10.

In the element formation region 16, the semiconductor layer 10a below the gate electrode layer 110 and the first electrode layer 6 are formed.
A first p-type body region 50a is formed in the semiconductor layer 10a below a part of 0. The first p-type body region 50a is joined to the p-type base region 220 below the first electrode layer 60.

In the element formation region 16, the gate electrode layer 11 in the formation region of the bipolar transistor 200.
The second p-type body region 50b is formed in the semiconductor layer 10a under 0 and in the semiconductor layer 10a in the vicinity of the element isolation region 14.

In the first region A10 except the n-type source region 120, the p-type impurity diffusion layer 40 is formed. Specifically, the p-type impurity diffusion layer 40
Is between the first p-type body region 50 a below the first electrode layer 60 and the n-type source region 120,
Has been formed.

The gate electrode layer 11 in the formation region of the bipolar transistor 200 in the element formation region 16
An n-type body region 52a is formed in the semiconductor layer 10a below a part of 0. The n-type body region 52a is
It is formed between the p-type base region 220 and the n-type collector region 230.

Next, the semiconductor layer 10a will be described with reference to FIGS. 1 and 4 to 6. An interlayer insulating layer 80 is formed on the semiconductor layer 10a. The first to fourth through holes 8 are formed in predetermined regions of the interlayer insulating layer 80.
2, 84, 86 and 88 are formed. The first through hole 82 is formed in the first region A10 and is formed so as to straddle the n-type source region 120 and the p-type impurity diffusion layer 40. Second through hole 8
4 is formed in the second area A20. Third
Through hole 86 is formed in the third region A30. The fourth through hole 88 is formed to take out the gate electrode layer 110.

A first contact layer 82a is formed in the first through hole 82. The first contact layer 82a has a function of short-circuiting the n-type source region 120 and the p-type impurity diffusion layer 40. As a result, the first p-type body region 50a and the n-type source region 120 are p-type.
It is electrically connected via the type impurity diffusion layer 40. Second
~ Second to fourth contact layers 84a, 86a, 88a are formed in the fourth through holes 84, 86, 88, respectively.

On the inter-layer insulating layer 80, the first wiring layer 90 electrically connected to the second contact layer 84a.
Are formed. A second wiring layer 92 electrically connected to the third contact layer 86a is formed on the interlayer insulating layer 80. Second wiring layer 92
Is connected to ground, for example. Further, on the interlayer insulating layer 80, the third wiring layer 94 electrically connected to the fourth contact layer 86a is formed.

[Manufacturing Method of Semiconductor Device] (Process) Hereinafter, a manufacturing method of the semiconductor device according to the embodiment will be described. 8 to 13 are plan views schematically showing the manufacturing process of the semiconductor device according to the embodiment. Figure 9
13A to 13C, the thin sloping area on the lower left indicates the p-type area, and the thin sloping area on the lower right indicates the n-type area.

First, as shown in FIG. 8, the SOI substrate 10
The element isolation region 14 is formed in the semiconductor layer 10a in FIG. By forming the element isolation region 14,
The element formation region 16 is defined. Examples of the method for forming the element isolation region 14 include a LOCOS method and a trench isolation method.

Next, as shown in FIG. 9, the element forming region 1
In the semiconductor layer 10a in 6, the first p-type body region 50a and the n-type body region 52a are formed. The first p-type body region 50a is at least the region where the gate electrode layer 110 is to be formed and the region 60 where the first electrode layer 60 is to be formed in the field effect transistor formation region.
Formed at A. Element isolation region 14 is LOCOS
When it is formed by the method, it is the semiconductor layer 10a in the formation planned region of the gate electrode layer 110 in the bipolar transistor formation planned region and the element isolation region 14
A second p-type body region 50b is preferably formed in the semiconductor layer 10a in the vicinity of.

The first and second p-type body regions 50a,
50b and n type body region 52a can be formed as follows, for example. The first and second p-type body regions 50a and 50b are formed by ion-implanting p-type impurities into a predetermined region using a lithography technique.
Then, the n-type body region 52a is formed by ion-implanting an n-type impurity into a predetermined region using the lithography technique. In addition to this method, after p-type impurities are ion-implanted in the entire element formation region 16, n-type impurities may be ion-implanted in a predetermined region using a lithography technique.

Next, a polysilicon layer (not shown) is deposited on the entire surface by the CVD method or the like. Then, the polysilicon layer is patterned by lithography and etching techniques, and the gate electrode layer 110 is formed as shown in FIG.
And the first electrode layer 60 is formed.

Next, as shown in FIG. 11, a p-type impurity is selectively ion-implanted into the third region A30 by using the lithography technique to form a p-type impurity diffusion layer 222.

Next, as shown in FIG. 12, the substrate 10 is heat-treated to thermally diffuse the p-type impurity diffusion layer 222. Thus, the p-type base region 220 is formed under a part of the first electrode layer 60 and a part of the gate electrode layer 110 in the bipolar transistor formation planned region. Specifically, when the heat treatment temperature is 1100 ° C., the heat treatment time is, for example, 10 minutes, and when the heat treatment temperature is 1050 ° C., the heat treatment time is, for example, 30 minutes.

Next, as shown in FIG. 13, an n-type impurity is selectively ion-implanted into a predetermined region of the element formation region 16 by utilizing the lithography technique. Thus, the first
Region A10, an n-type source region 120 is formed, and in the second region A20, an n-type drain region 130 is formed.
And an n-type collector region 230 are formed, and an n-type emitter region 210 is formed in the third region A30.

Next, in a predetermined area in the first area A10,
P-type impurities are ion-implanted to form the p-type impurity diffusion layer 40.
To form. When the semiconductor device 1000 has a p-type field effect transistor, this p-type impurity ion implantation step can be performed in the same step as the step of forming the p-type source / drain regions.

Next, as shown in FIGS. 1 and 4 to 6, an interlayer insulating layer 80 made of silicon oxide is formed on the substrate 10 by a known method. Next, first to fourth through holes 82, 84, 86, 88 are formed in predetermined regions in the interlayer insulating layer 80. Next, first to fourth
Through holes 82, 84, 86, 88 are filled with a conductive layer, and the first to fourth contact layers 82a, 84a,
86a and 88a are formed. Then, the first to third wiring layers 9 having a predetermined pattern are formed on the interlayer insulating layer 80.
0, 92, 94 are formed. Thus, the semiconductor device 1000 according to this embodiment is formed.

(Operation and Effect) The operation and effect of the method for manufacturing a semiconductor device according to the embodiment will be described below.

(1) In the present embodiment, the p-type impurity diffusion layer 222 is formed in the third region A30, and the p-type impurity diffusion layer 222 is heat-treated to form p-type impurity diffusion layer 222.
The p-type base region 220 is formed by thermally diffusing the type impurities. As a result, under the first electrode layer 60, p
The mold base region 220 and the first p-type body region 50a are electrically connected. Therefore, according to the manufacturing method of the present embodiment, the p-type base region 2 can be formed without forming a contact layer for drawing out the p-type base region 220.
20 and the first p-type body region 50a can be electrically connected.

Further, in the present embodiment, n-type impurities are ion-implanted into the third region A30 by using the first electrode layer 60 and the gate electrode layer 110 as a mask, and n
A mold emitter region 210 can be formed. Therefore, according to the present embodiment, n-type emitter region 210 can be formed in self-alignment with p-type base region 220.

(2) When the element isolation region 14 is formed by the LOCOS method, the bipolar transistor 20
It is preferable to form the second p-type body region 50b in the semiconductor layer 10a under the gate electrode layer 110 at 0 and in the semiconductor layer 10a near the element isolation region 14. The reason for this will be described below.

When an n-type body region is formed in the semiconductor layer 10a under the gate electrode layer 110 in the bipolar transistor 200 and in the semiconductor layer 10a in the vicinity of the element isolation region 14, the following problem occurs. Occurs. The p-type base region 220 is formed by thermally diffusing the p-type impurity diffusion layer 222 in the third region A30. However, as shown in FIG. 15, p-type impurities are difficult to thermally diffuse to the corner formed by the element isolation region 14 and the insulating layer 10b, so that the n-type body region 300 remains at the corner. It may end up. When the n-type body region 300 remains, the n-type body region 30
The n-type emitter region 210 and the n-type collector region 230 are short-circuited via 0.

Therefore, by forming the second p-type body region 50a in the semiconductor layer 10a under the gate electrode layer 110 in the bipolar transistor 100 and in the semiconductor layer 10a in the vicinity of the element isolation region 14, it is possible to ensure the reliability. In addition, it is possible to prevent the n-type emitter region 210 and the n-type collector region 230 from being short-circuited.

Experimental Example An experimental example will be described below.

(Regarding Kink) It was examined what kind of difference occurs in kink between the semiconductor device according to the example and the semiconductor device according to the comparative example. FIG. 16 shows a voltage (VD) applied to the drain region with respect to the source region according to the embodiment.
It is a graph which shows the relationship between S) and drain current (ID). FIG. 17 is a graph showing the relationship between the voltage (VDS) applied to the drain region with respect to the source region and the drain current (ID) according to the comparative example. In addition, VG is
It means the gate voltage.

The example has the configuration shown in the embodiment. Specifically, the embodiment is composed of an n-type MOS transistor and an npn-type bipolar transistor, and the width of the gate electrode layer in the element formation region is 0.8 μm.
m, the length of the gate electrode layer in the MOS transistor formation region was 4 μm, the width of the gate electrode layer in the bipolar transistor formation region was 0.8 μm, and the length of the gate electrode layer in the bipolar transistor formation region was 4 μm. The structure of the comparative example is a simple n-type MO.
It was an S transistor. In the comparative example, the gate width was 0.8 μm and the gate length was 8 μm. The switching element according to the example and the field effect transistor according to the comparative example were formed on the same wafer and formed under the same process conditions.

In the comparative example, as shown in FIG.
It can be seen that a kink has occurred. But,
In the example, as shown in FIG. 16, it can be seen that no kink has occurred. From the above, according to the embodiment,
It can be seen that the occurrence of kinks can be prevented.

(Regarding History Effect) It was examined what kind of difference occurs in the history effect between the semiconductor device according to the example and the semiconductor device according to the comparative example. 18 and 19 show the gate voltage (VG) and the drain current (I
It is a graph which shows the relationship with D). FIG. 18 shows data when the voltage applied to the drain region with respect to the source region is 1V. FIG. 19 shows data when the voltage applied to the drain region with respect to the source region is 0.1V. 18 and 19, the thin line indicates the example, and the thick line indicates the comparative example.

18 and 19, the graph A1 is the data of the example, and the graph B1 is the data of the comparative example. The conditions of the semiconductor device according to the example and the semiconductor device according to the comparative example are the same as those described in the item of kink.

First, the experimental data shown in FIG. 18 will be examined. In the comparative example, the history effect remarkably appears. On the other hand, in the embodiment, the gate voltage is about 0.25.
It can be seen that the history effect is slightly suppressed below V, but the history effect is significantly suppressed as compared with the comparative example.

Next, the experimental data of FIG. 19 will be examined. In the comparative example, the history effect is observed when the gate voltage is about 0.8 V or less. On the other hand, in the embodiment, the history effect is observed when the gate voltage is 0.15 V or less.
That is, according to the example, the range of the gate voltage at which the history effect does not occur is wider than that of the comparative example.

[Modification] The above embodiment can be variously modified within the scope of the present invention. For example, the following changes are possible.

(1) In the above embodiments, the field effect transistor is n-type and the bipolar transistor is npn-type. However, the field effect transistor may be p-type and the bipolar transistor may be pnp-type.

(2) In the above embodiment, the gate electrode layer 110 is provided so as to straddle the element forming region 16. Then, the first electrode layer 60 reaching the element isolation region 16 from the side portion of the gate electrode layer 110 is formed. However, the present invention is not limited to this, and as shown in FIG. 21, the gate electrode layer 110, the first layer 70, and the second layer 7 are formed.
The first area A10, the second area A20, and the third area A30 may be configured with 2. The material of the first layer 70 and the second layer 72 is not particularly limited, and examples thereof include insulating materials (silicon oxide, silicon nitride).

In this modification, the gate electrode layer 11
The connection relationship between 0, the first layer 70, and the second layer 72 has the following relationship, for example. a) A mode in which the end of the first layer 70 is continuous with the gate electrode layer 110 and the end of the second layer 72 is also continuous with the gate electrode layer 110. b) A mode in which the end of the first layer 70 is continuous with the gate electrode layer 110 and the end of the second layer 72 is continuous with the end of the first layer 70. c) Second
The layer 72 has an end portion continuous with the gate electrode layer 110, and the first layer 70 has an end portion continuous with the second layer 72.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present invention.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a semiconductor device.

FIG. 2 is a plan view schematically showing a layer in which a gate electrode is formed and a plane of the semiconductor device below the layer.

FIG. 3 is a plan view schematically showing a plane of a semiconductor device in a layer in which a semiconductor layer is formed.

4 is a cross-sectional view schematically showing a cross section taken along line AA in FIG.

5 is a cross-sectional view schematically showing a cross section taken along the line BB in FIG.

6 is a cross-sectional view schematically showing a cross section taken along the line CC of FIG.

FIG. 7 shows an equivalent circuit of a switching element.

FIG. 8 is a cross-sectional view schematically showing the manufacturing process of the semiconductor device according to the embodiment.

FIG. 9 is a cross-sectional view schematically showing the manufacturing process of the semiconductor device according to the embodiment.

FIG. 10 is a cross-sectional view schematically showing the manufacturing process of the semiconductor device according to the embodiment.

FIG. 11 is a cross-sectional view schematically showing the manufacturing process of the semiconductor device according to the embodiment.

FIG. 12 is a cross-sectional view schematically showing the manufacturing process of the semiconductor device according to the embodiment.

FIG. 13 is a cross-sectional view schematically showing the manufacturing process of the semiconductor device according to the embodiment.

FIG. 14 shows an equivalent circuit of a BICMOS inverter circuit.

FIG. 15 is a schematic cross-sectional view for explaining a function and effect.

FIG. 16 is a diagram showing the voltage (VDS) applied to the drain region with respect to the source region and the drain current (I
It is a graph which shows the relationship with D).

FIG. 17 shows a voltage (VDS) applied to the drain region with respect to the source region and a drain current (I
It is a graph which shows the relationship with D).

FIG. 18 shows a gate voltage (VG) and a drain current (I
It is a graph which shows the relationship with D). The data is obtained when the voltage applied to the drain region with respect to the source region is 1V.

FIG. 19 shows a gate voltage (VG) and a drain current (I
It is a graph which shows the relationship with D). The data is obtained when the voltage applied to the drain region with respect to the source region is 0.1V.

FIG. 20 is a cross-sectional view schematically showing a MOS transistor formed on an SOI substrate according to a conventional example.

FIG. 21 is a plan view schematically showing a modified example of the semiconductor device in the layer in which the gate electrode layer is formed.

[Explanation of symbols]

10 SOI substrate, 10a SOI layer, 14 element isolation region, 16 element formation region, 40 p-type impurity diffusion layer, 50a first p-type body region, 50b second
P-type body region, 52a n-type body region, 60
First electrode layer, 60a first electrode layer formation planned region,
80 interlayer insulating layer, 82 first through hole, 8
2a 1st contact layer, 84 2nd through hole, 84a 2nd contact layer, 86 3rd through hole, 86a 3rd contact layer, 88 4th
Through-hole, 88a Fourth contact layer, 90
First wiring layer, 92 second wiring layer, 94 third
Wiring layer, 100 n-type field effect transistor,
110 gate electrode layer, 110a gate electrode layer formation planned region, 120 n-type source region, 130 n-type drain region, 140 gate insulating layer, 200 npn
-Type bipolar transistor, 210 n-type emitter region, 220 p-type base region, 222 p-type impurity diffusion layer, 230 n-type collector region, A10 first region, A20 second region, A30 third region, 1
000 Semiconductor device

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/73 F term (reference) 5F003 BB90 BC90 BJ08 BJ15 BN01 BP21 5F048 AA01 AA04 AA07 AA10 AB04 AC05 AC07 BA16 BB01 BB05 BC01 BC03 BE09 BF11 BF16 BF17 BG12 BG13 CA03 CA04 5F082 AA08 AA40 BA04 BA05 BA21 BA26 BA47 BA48 BC01 BC09 DA02 DA10 EA09 FA05 FA12 GA02 GA04

Claims (18)

[Claims] 1. An insulating layer, a semiconductor layer formed on the insulating layer, an element isolation region formed in the semiconductor layer, an element formation region defined by the element isolation region,
At least one of the element formation regions includes both a bipolar transistor and a field effect transistor, and further has at least a body region formed between a source region and a drain region, the body region And the source region are electrically connected, the body region and the base region are electrically connected, the drain region and the collector region are electrically connected, and the source region and , A semiconductor device formed so as to be structurally separated from the emitter region. 2. An insulating layer, a semiconductor layer formed on the insulating layer, an element isolation region formed in the semiconductor layer, an element formation region defined by the element isolation region,
At least one of the element formation regions includes both a bipolar transistor and a field effect transistor, and the bipolar transistor includes a first conductivity type emitter region, a second conductivity type base region, and a first conductivity type base region. A field-effect transistor including a gate electrode layer;
A source region of a conductivity type and a drain region of a first conductivity type; and a first second conductivity type body region formed at least between the source region and the drain region, The first second conductivity type body region and the source region are electrically connected, the first second conductivity type body region and the base region are electrically connected, and the drain A semiconductor device, wherein the region and the collector region are electrically connected to each other, and the source region and the emitter region are structurally separated from each other. 3. The device according to claim 2, further comprising a first electrode layer continuous to a side portion of the gate electrode layer and reaching the element isolation region, the gate electrode layer straddling the element formation region. Formed in this manner, the source region is formed in a first region surrounded by the gate electrode layer in the field effect transistor formation region, the first electrode layer, and the element isolation region, The drain region and the collector region are formed in a second region surrounded by the gate electrode layer and the element isolation region, the gate electrode layer in the bipolar transistor formation region, and the first electrode layer And the emitter region is formed in a third region surrounded by the element isolation region, and the first second conductivity type body region is at least the electric field. A semiconductor device, which is formed below the gate electrode layer and below a part of the first electrode layer in an effect transistor formation region. 4. The method according to claim 2, further comprising a first layer and a second layer, wherein one end of the first layer is continuous with the gate electrode layer or the second layer. The other end reaches the element isolation region, the second layer has one end continuous with the gate electrode layer or the first layer, and the other end has the element isolation region. The source region is formed in a first region surrounded by the gate electrode layer, the first layer, and the element isolation region, and the gate electrode layer, the second layer, and the element isolation region are formed. The drain region and the collector region are formed in a second region surrounded by, and the emitter region is formed in a third region surrounded by the first layer, the second layer, and the element isolation region. Formed under a portion of the first layer and the first layer The base region is formed in a semiconductor layer below a part of the first layer, and the first second conductivity type body region is at least below the gate electrode layer and below a part of the first layer. Forming a semiconductor device. 5. The semiconductor device according to claim 2, further comprising a body region of the first conductivity type, wherein the body region of the first conductivity type is a semiconductor layer between the base region and the collector region. Is formed,
Semiconductor device. 6. The impurity diffusion layer of the second conductivity type is further formed, and the impurity diffusion layer of the second conductivity type is a semiconductor layer in the first region. Is formed in the semiconductor layer between the source region and the first second conductivity type body region, and the source region and the first second conductivity type body region are of the second conductivity type. A semiconductor device electrically connected via an impurity diffusion layer. 7. The contact layer according to claim 2, wherein a contact layer for electrically connecting the impurity diffusion layer of the second conductivity type and the source region is formed, and the contact layer is the first layer. A semiconductor device formed so as to straddle a two-conductivity-type impurity diffusion layer and the source region. 8. The semiconductor layer according to claim 2, wherein a semiconductor layer between the collector region and the emitter region, the semiconductor layer near the element isolation region, is provided with a second layer.
Of the second conductivity type body region is formed. 9. The method according to claim 2, wherein The first conductivity type is n-type, A semiconductor device in which the second conductivity type is p-type. 10. The method according to claim 2, wherein The first conductivity type is p-type, The semiconductor device, wherein the second conductivity type is n-type. 11. The method according to claim 2, wherein A semiconductor device, wherein the semiconductor layer is a silicon layer. 12. An insulating layer, a semiconductor layer formed on the insulating layer, an element isolation region formed in the semiconductor layer, an element formation region defined by the element isolation region,
Including at least one of the element formation region includes a bipolar transistor and a field effect transistor, a gate electrode layer is formed on the semiconductor layer, the gate electrode layer, the element formation region A first electrode layer is formed so as to straddle the semiconductor layer, and one end of the first electrode layer is continuous with a side part of the gate electrode layer and the other end of the first electrode layer is continuous. Part reaches the element isolation region, at least a part of the first region surrounded by the gate electrode layer in the field effect transistor formation region, the first electrode layer, and the element isolation region, A first first-conductivity-type impurity diffusion layer is formed, and a second first-conductivity-type impurity diffusion layer is formed in a second region surrounded by the gate electrode layer and the element isolation region, by A third first-conductivity-type impurity diffusion layer is formed in a third region defined by the gate electrode layer, the first electrode layer, and the element isolation region in a polar transistor formation region, A first second conductivity type body region is formed below the gate electrode layer and the first electrode layer in the field effect transistor formation region, and the gate electrode layer and the first region in the bipolar transistor formation region are formed. A first electrode layer below the first electrode layer and along the periphery of the third first-conductivity-type impurity diffusion layer;
Second conductivity type impurity diffusion layer is provided, and the first second conductivity type body region and the first first conductivity type impurity diffusion layer are electrically connected, and the first second A semiconductor device, wherein the conductive type body region and the first second conductive type impurity diffusion layer are electrically connected. 13. A method of manufacturing a semiconductor device, comprising: an insulating layer; and a semiconductor layer formed on the insulating layer, wherein an element isolation region is formed in the semiconductor layer, and an element forming region is defined. (A) includes a step (B) of forming a field effect transistor and a bipolar transistor in the same element formation region, and the step (B) includes (B-1) at least a part of the gate electrode layer. Forming a first second-conductivity-type body region in the semiconductor layer in the formation planned region and the first electrode layer formation planned region, (B-2) forming the gate electrode layer and the gate electrode layer on the semiconductor layer. Forming the first electrode layer, wherein the first electrode layer is continuous with a side portion of the gate electrode layer and reaches the element isolation region, (B-3) formation of the bipolar transistor In the area Forming a second conductivity type impurity diffusion layer in the semiconductor layer in the third region surrounded by the gate electrode layer, the first electrode layer, and the element isolation region, and (B-4) heat treatment. By doing so, the impurity diffusion layer of the second conductivity type is thermally diffused to form the base region of the bipolar transistor in the semiconductor layer below the first gate electrode layer and below the first electrode layer. Electrically connecting the base region and the first second conductivity type body region, (B-5) the gate electrode layer in the field effect transistor, the first electrode layer and the element. At least a part of the first region surrounded by the isolation region and the first region of the field effect transistor
A step of forming a conductive type source region, (B-6) a part of the second region surrounded by the gate electrode layer and the element isolation region, of the first conductive type of the field effect transistor. Forming a drain region, (B-7) forming a collector region of the first conductivity type of the bipolar transistor in a part of the second region, and (B-8)
Forming a first conductivity type emitter region of the bipolar transistor in the third region; and (B-9) electrically connecting the first second conductivity type body region and the source region. A method of manufacturing a semiconductor device, the method including: 14. A method of manufacturing a semiconductor device, comprising: an insulating layer; and a semiconductor layer formed on the insulating layer, wherein an element isolation region is formed in the semiconductor layer, and an element forming region is defined. (C) includes a step (D) of forming a field effect transistor and a bipolar transistor in the same element formation region, and the step (D) includes (D-1) at least a gate electrode layer formation schedule Forming a first second conductivity type body region in the semiconductor layer in the region and the region where the first layer is to be formed; (D-2) forming a gate electrode layer on the semiconductor layer; D-3) On the semiconductor layer,
In the step of forming a first layer, one end of the first layer is continuous with the gate electrode layer or the second layer, and the other end reaches the element isolation region,
(D-4) a step of forming a second layer on the semiconductor layer, wherein one end of the second layer is continuous with the gate electrode layer or the first layer, and the other The end of the element reaches the element isolation region,
(D-5) In a semiconductor layer in a third region surrounded by the first layer, the second layer, and the element isolation region,
A step of forming a second conductivity type impurity diffusion layer, (D-6)
By performing heat treatment, the impurity diffusion layer of the second conductivity type is thermally diffused to form a base region of the bipolar transistor in the semiconductor layer below the first layer and below the second layer. A step of short-circuiting the base region and the first second conductivity type body region, (D-7) a first region surrounded by the gate electrode layer, the first layer and the element isolation region. Forming a first conductivity type source region of the field effect transistor in at least a part of the region, (D-8) surrounded by the gate electrode layer, the second layer, and the element isolation region. Forming a drain region of the first conductivity type of the field effect transistor in a part of the second region, (D-9) the gate electrode layer, the second layer, and the element isolation region. In the part of the second area surrounded by Forming a collector region of the first conductivity type of the transistor, and (D-10) in a third region surrounded by the first layer, the second layer and the element isolation region, Of bipolar transistor,
Forming a first conductivity type emitter region, and (D
-11) A method of manufacturing a semiconductor device, including a step of electrically connecting the first body region of the second conductivity type and the source region. 15. The second conductivity type body according to claim 14, further comprising: a semiconductor layer below the second layer in the element formation region, the semiconductor layer near the element isolation region. A method of manufacturing a semiconductor device, comprising the step of forming a region. 16. The method of manufacturing a semiconductor device according to claim 13, wherein the first conductivity type is n-type and the second conductivity type is p-type. 17. The method of manufacturing a semiconductor device according to claim 13, wherein the first conductivity type is p-type and the second conductivity type is n-type. 18. The method of manufacturing a semiconductor device according to claim 13, wherein the semiconductor layer is a silicon layer.