JP2004063600A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device such as an SOI device capable controlling the potential of a channel region by using even one electrode, and completely suppressing the destruction of a gate oxide film induced from the destruction of a BOX (buried oxidation) film by preventing destruction of the BOX film due to a surge. <P>SOLUTION: Contact holes 215, 217 penetrating through the buried oxidation film 202 and reaching a silicon substrate 401 are provided in N-channel transistor active region extension parts 101A, 102A. Metallic films 216, 218 are filled in the contact holes, and electrodes 212, 214 are formed. Only by impressing potential to the electrodes 212, 214 all of potential levels of the adjacent channel regions of the same conduction type transistors are fixed. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, in the field of semiconductor devices, high-speed operation and low power consumption due to rapid miniaturization have been advanced. However, the process using a conventional bulk silicon wafer has reached its limit, and a next-generation device using an SOI (Silicon on Insulator) wafer is expected.
[0003]
This is an LSI in which an ultra-thin single-crystal silicon layer is formed on an insulating layer and a CMOS is formed thereon. Compared with an LSI on a conventional silicon substrate, the operation speed is easily increased and power consumption is reduced. It is easy to perform, and latch-up can be prevented.
[0004]
10 (a) and 10 (b) show a conventional SOI transistor, FIG. 10 (b) is a cross-sectional view, and FIG. 10 (a) is a plan view of a region near a surface indicated by an arrow XX ', which is a silicon substrate. 7, an SOI layer 9 is provided, and a transistor is formed in the SOI layer 9.
[0005]
1 is an active region extension, 2 is a gate electrode extension, 3 is a body contact region, 4A is a drain region, 4 is a drain contact region, 5A is a source region, 5 is a source contact region, 6 is a gate contact region, 8 is A buried oxide film (BOX film), 10 is a shallow trench isolation (STI), 11 is a channel region, 12 is a gate oxide film, 13 is a gate electrode, 14 is a body contact electrode, and 15 is a gate contact electrode.
[0006]
As described above, when the shallow trench isolation 10 (hereinafter, referred to as STI) is formed due to the presence of the buried oxide film 8 (hereinafter, referred to as BOX film), the channel region 11 is in a floating state. Therefore, by providing the active region extension 1, the body contact region 3 is designated in layout, and the potential of the channel region 11 is fixed via the body contact electrode 14. At the same time, a gate electrode extension 2 is provided to secure a path for the body contact immediately below.
[0007]
[Problems to be solved by the invention]
However, in the above configuration, the channel region 11 is independent for each transistor, and the voltage cannot be controlled unless a potential is applied to each body contact electrode 14.
[0008]
In addition, the SOI layer 9 and the silicon substrate 7 are insulated and separated by the BOX film 8. If the SOI layer 9 and the silicon substrate 7 are damaged during the process, the gate oxide film 12 and the BOX film 8 exist as a series capacitor, and the BOX film 8 becomes excessive. More susceptible to damage. The damaged BOX film 8 has a problem in that a surge breakdown occurs locally in a weak portion, and a surge breakdown of the gate oxide film 12 occurs due to the surge breakdown.
[0009]
In view of the above problems, an object of the present invention is to provide a SOI device that can control the potential of a channel region with only one electrode, completely prevent a gate oxide film breakdown induced by a BOX film breakdown without causing a surge breakdown of a BOX film. An object of the present invention is to provide a semiconductor device that can be suppressed and a method for manufacturing the same.
[0010]
[Means for Solving the Problems]
To achieve this object, a semiconductor device according to claim 1 of the present invention has an SOI structure including a silicon substrate, an insulating layer formed on the silicon substrate, and a semiconductor layer formed on the insulating layer. A semiconductor device having an MIS transistor formed on the semiconductor layer, the semiconductor device comprising: an active region including the semiconductor layer; an active region extension including the semiconductor layer extending from the active region; A contact hole reaching the silicon substrate provided through the semiconductor layer and the insulating layer located in the body contact region of the region extension, and a body contact electrode made of a metal film filled in the contact hole; And applying a potential to the body contact electrode so that the potentials of the channel regions of adjacent transistors of the same conductivity type are all increased. It can be constant.
[0011]
According to a second aspect of the present invention, in the first aspect, by applying a potential to the body contact electrode, the potential of the channel region in the active region of the adjacent MIS transistor of the same conductivity type can be simultaneously fixed.
[0012]
According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the n-type MIS transistor includes an n-type MIS transistor, and an n-type transistor formation region in which a plurality of the n-type MIS transistors are formed. A P-type impurity layer is provided on the silicon substrate located immediately below the contact hole of the n-type MIS transistor, and body contact electrodes of the plurality of n-type MIS transistors are provided via the P-type impurity layer. It is characterized by being electrically connected.
[0013]
According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, a p-type MIS transistor is provided as the MIS transistor, and a plurality of the p-type MIS transistors are formed. In the P-type transistor forming region, an N-type impurity layer is provided on the silicon substrate located immediately below the contact hole of the p-type MIS transistor, and a plurality of the p-type MIS transistors are provided via the N-type impurity layer. Are electrically connected to each other.
[0014]
According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, the n-type MIS transistor includes an n-type MIS transistor and a p-type MIS transistor as the MIS transistor. A high-concentration P-type impurity layer having the same implantation dose as the high-concentration source / drain region of the p-type MIS transistor is formed in the active-region extension of the p-type MIS transistor. Is characterized in that a high-concentration N-type impurity layer having the same implantation dose as the high-concentration source / drain region of the n-type MIS transistor is formed.
[0015]
The method of manufacturing a semiconductor device according to claim 6 of the present invention uses a substrate having an SOI structure including a silicon substrate, an insulating layer formed on the silicon substrate, and a semiconductor layer formed on the insulating layer. A method of manufacturing a semiconductor device having a MIS transistor, wherein the step (a) of patterning the semiconductor layer to form an active region of the MIS transistor and an active region extension extending the active region; (B) forming a trench isolation region surrounding the active region extension and having the insulating layer as the bottom, and penetrating the semiconductor layer and the insulating layer located in the body contact region of the active region extension; (C) forming a contact hole reaching the silicon substrate, and a body contact made of a metal film in the contact hole Characterized in that it comprises a step (d) of forming the electrode.
[0016]
According to a seventh aspect of the present invention, in the method for manufacturing a semiconductor device according to the sixth aspect, the MIS transistor includes an n-type MIS transistor, and after the step (b) and before the step (c), Forming a p-type impurity layer on the silicon substrate immediately below the insulating layer in an n-type transistor formation region where the n-type MIS transistor is formed; The contact hole is formed so as to reach the P-type impurity layer, and in the step (d), the body contact electrode of the n-type MIS transistor is formed so as to be connected to the P-type impurity layer. And
[0017]
According to a eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth or seventh aspect, a p-type MIS transistor is provided as the MIS transistor, and the step (c) is performed after the step (b). Forming an N-type impurity layer on the silicon substrate immediately below the insulating layer in a P-type transistor formation region where the p-type MIS transistor is formed, and in the step (c), Forming the contact hole of the p-type MIS transistor so as to reach the n-type impurity layer; and forming the body contact electrode of the p-type MIS transistor so as to connect to the n-type impurity layer in the step (d). It is characterized by doing.
[0018]
According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the sixth to eighth aspects, the method further comprises: as the MIS transistor, an n-type MIS transistor and a p-type MIS transistor; ), Before the step (c), simultaneously ion-implanting P-type impurities into the active region extension of the n-type MIS transistor and the source / drain region of the p-type MIS transistor; A step of simultaneously ion-implanting N-type impurities into the active region extension of the transistor and the source / drain regions of the n-type MIS transistor.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the drawings.
[0020]
FIG. 1 shows a substrate having an SOI structure including a silicon substrate, an insulating layer formed on the silicon substrate, and a semiconductor layer formed on the insulating layer, and an MIS transistor formed on the semiconductor layer. FIGS. 3A to 9 show a region plan view (a) and a cross-sectional view (b) of the semiconductor device in the manufacturing process.
[0021]
First, a semiconductor device according to an embodiment of the present invention will be described.
As shown in FIG. 1, in an SOI structure substrate, an Nch transistor active region extension 101A obtained by extending the Nch transistor active region 101 is provided in an Nch transistor formation region 1N, and a wiring interlayer film 211 of the Nch transistor active region extension 101A and an SOI layer are provided. A structure having a contact hole 215 that penetrates through the 203 and the BOX film 202 and reaches the silicon substrate 201 is adopted.
[0022]
The contact hole 215 is filled with a metal film 216, and a metal electrode 212 for Nch transistor body contact exists so as to be in contact with the silicon substrate 201, and a high level exists in the SOI layer 203 of the active region extension 101A of the Nch transistor formation region 1N. The P-type diffusion layer 205B having a concentration has a structure in which the P-type impurity layer 205A exists in the silicon substrate 201 immediately below the BOX film 202 in the Nch transistor formation region 1N.
[0023]
Similarly, a Pch transistor active region extension portion 102A obtained by extending the Pch transistor active region 102 is provided in the Pch transistor formation region 1P, and penetrates the wiring interlayer film 211, the SOI layer 203, and the BOX film 202 of the Pch transistor active region extension portion 102A. Then, a structure having a contact hole 217 reaching the silicon substrate 201 is formed.
[0024]
A metal film 218 is filled in the contact hole 217, and a metal electrode 214 for Pch transistor body contact is present so as to be in contact with the silicon substrate 201, and a high level exists in the SOI layer 203 of the active region extension 102A of the Pch transistor formation region 1P. The N-type diffusion layer 206B having a concentration is configured such that the N-type impurity layer 206A exists on the silicon substrate 201 immediately below the BOX film 202 in the Pch transistor formation region 1P.
[0025]
Further, the gate electrode region 103 is extended at the edges of the Nch transistor active region extension 101A and the Pch transistor active region extension 102A, and has a structure having a home base shape. The gate electrode 208 has a structure connected to the gate electrode metal electrode 213.
[0026]
Note that 104 is an Nch transistor body contact region, 105A is an Nch transistor drain region, 105 is an Nch transistor drain contact region, 106A is an Nch transistor source region, 106 is an Nch transistor source contact region, 107A is a Pch transistor drain region, and 107 is Pch Transistor drain contact region, 108A is a Pch transistor source region, 108 is a Pch transistor source contact region, 109 is a Pch transistor body contact region, 110 is a gate electrode contact region, 204 is an STI, 205 is an Nch transistor channel region, 206 is a Pch transistor A channel region, 207 is a gate oxide film, 209 is a gate electrode silicide, and 210 is an LDD sidewall. Is Lumpur.
[0027]
This semiconductor device can be manufactured by the following process.
First, as shown in FIG. 3, the body contact portions of the Nch transistor active region 301 and the Pch transistor active region 302 in the Nch transistor formation region 2N and the Pch transistor formation region 2P in the SOI layer 403 on the silicon substrate 401, respectively. The Nch transistor active region extension 301A and the Pch transistor active region extension 302A are also expanded and patterned to form an STI 402A having the BOX film 402 as a bottom by a normal separation forming process. 404 is a pad oxide film.
[0028]
Next, as shown in FIG. 4, Nch transistor threshold value control implantation is performed in the SOI layer 403 of the Nch transistor formation region 2N, for example, boron ions are implanted at an acceleration energy of 30 KeV and a dose of 5.5 × 10 4. ¹² Pieces / cm ² To form an Nch transistor threshold voltage control layer 405. At the same time, for example, boron ions are accelerated at an energy of 150 KeV and a dose of 9.0 × 10 ¹³ Pieces / cm ² To form a P-type impurity layer 405A immediately below the BOX film 402 in the Nch transistor formation region 2N. Reference numeral 303 denotes an Nch transistor threshold control layer region.
[0029]
Next, similarly, Pch transistor threshold value control implantation is performed in the SOI layer 403 in the Pch transistor formation region 2P, for example, phosphorus ions are accelerated at an energy of 50 KeV and a dose of 1.2 × 10 ¹² Pieces / cm ² To form a Pch transistor threshold voltage control layer 406. At the same time, for example, phosphorus ions are accelerated at an energy of 330 KeV and a dose of 9.0 × 10 ¹³ Pieces / cm ² To form an N-type impurity layer 406A immediately below the BOX film 402 in the Pch transistor formation region 2P. Reference numeral 304 denotes a Pch transistor threshold control layer region.
[0030]
Next, as shown in FIG. 5, after removing the pad oxide film 404, the gate electrode formation region 305 is patterned by a normal gate electrode formation process to form a gate oxide film 407 and a gate electrode 408.
[0031]
Next, as shown in FIG. 6, after an oxide film sidewall 409 is formed on the side surface of the gate electrode 408, the source / drain region of the Nch transistor formation region 2N and the Pch transistor active region extension 302A are formed by lithography. After forming the first resist film 410 having an opening, using the first resist film 410 as a mask, high-concentration source / drain implantation of an Nch transistor is performed, for example, by arsenic ion acceleration energy of 70 KeV and a dose of 3.0 × 10 3. ^Fifteen Pieces / cm ² Inject under the conditions of At this time, a high-concentration N-type body contact diffusion layer 406B is formed in the SOI layer 403 serving as a body contact part of the Pch transistor active region extension 302A. Reference numeral 306 denotes a high-concentration N-type impurity-implanted region serving as an n-type source / drain region;
[0032]
Next, as shown in FIG. 7, after removing the first resist film 410, a second opening having an opening above the source / drain region of the Pch transistor forming region 2P and the Nch transistor active region extension 301A by lithography. After forming the resist film 411, using the second resist film 411 as a mask, high-concentration source / drain implantation of the Pch transistor is performed, for example, by implanting boron ions at an acceleration energy of 10 KeV and a dose of 2.0 × 10 4. ^Fifteen Pieces / cm ² Inject under the conditions. At this time, a high-concentration P-type body contact diffusion layer 405B is formed in the SOI layer 403 serving as a body contact part of the Nch transistor active region extension 301A. Reference numeral 308 denotes a second resist film forming region, and 309 denotes a high-concentration P-type impurity-implanted region serving as a p-type source / drain region.
[0033]
Next, as shown in FIG. 8, after removing the second resist film 411 and forming a cobalt silicide layer 412 on the gate electrode 408, a wiring interlayer oxide film 413, for example, a BPSG film is formed on the entire surface of the substrate. It is formed by depositing 1300 nm and polishing it to 800 nm by a CMP method.
[0034]
Next, the Nch transistor body contact region 310, the Nch transistor drain contact region 311, the Nch transistor source contact region 312, the Pch transistor body contact region 313, the Pch transistor drain contact region 314, the Pch transistor source contact region 315, and the gate electrode contact region 316 Form a contact hole.
[0035]
For example, in the gate electrode contact region 316, the wiring interlayer oxide film 413 is etched until the silicide layer 412 is exposed to form a gate electrode contact hole 415. In the Nch transistor body contact region 310 and the Pch transistor body contact region 313, after the wiring interlayer oxide film 413 is etched until the SOI layer 403 is exposed, the high-concentration P-type body contact diffusion layer 405B of the SOI layer 403 and the high-concentration N-type Etching is performed through the body contact diffusion layers 406B, and the BOX film 402 is continuously etched until it reaches the silicon substrate 401 to form an Nch transistor body contact hole 414 and a Pch transistor body contact hole 416.
[0036]
Next, as shown in FIG. 9, for example, titanium and titanium nitride are buried in the gate electrode contact hole 415, the Nch transistor body contact hole 414, and the Pch transistor body contact hole 416 by sputtering, and then, for example, tungsten is continuously buried. Then, the Nch transistor body contact 417A, the gate electrode contact 418A, and the Pch transistor body contact 419A to be the first metal film are formed by polishing and filling by the CMP method.
[0037]
Next, for example, titanium nitride and aluminum as a second metal film are deposited by sputtering, patterned by lithography, and etched by dry etching to form an Nch transistor body contact electrode 417, a gate electrode contact electrode 418, and a Pch transistor. A body contact electrode 419 is formed.
[0038]
Conventionally, the channel region is independent for each transistor, and voltage control cannot be performed unless a potential is applied to the Nch transistor body contact electrode 417 and the Pch transistor body contact electrode 419, respectively. Further, the SOI layer 403 and the silicon substrate 401 are separated from each other, and if the semiconductor substrate is damaged during the process, the gate oxide film 410 and the BOX film 402 exist as a series capacitor, and the BOX film 402 is easily damaged. . The damaged BOX film 402 has a problem in that a surge breakdown occurs locally in a weak portion, which causes a surge breakdown of the gate oxide film 410. However, in the semiconductor device of this embodiment, FIG. As shown in FIG. 9, by applying a potential to the Nch transistor body contact electrode 417 in the SOI device, the Nch transistor threshold control layer 405 becomes the same potential via the P-type impurity layer 405A, and the P-type impurity layer 405A The threshold control layers of adjacent Nch transistors can have the same potential.
[0039]
Specifically, the P-type impurity layer 405A is the P-type impurity layer 205A shown in FIGS. 1 and 2, and the P-type impurity layer 205A is also formed below the adjacent Nch transistor as shown in FIG. Thus, the Nch transistor threshold value control layer 405 has the same potential via the P-type impurity layer 405A as described above.
[0040]
Similarly, by applying a potential to the Pch transistor body contact electrode 419, the Pch transistor threshold control layer 406 has the same potential via the N-type impurity layer 406A, and the adjacent Pch transistor via the N-type impurity layer 406A. The threshold control layers can be at the same potential.
[0041]
Specifically, the N-type impurity layer 406A is the N-type impurity layer 206A shown in FIGS. 1 and 2, and the N-type impurity layer 206A is also formed below the adjacent Pch transistor as shown in FIG. As a result, the Pch transistor threshold voltage control layer 406 has the same potential via the N-type impurity layer 406A as described above.
[0042]
Therefore, it is possible to control the potentials of the channel portions of all the transistors only by controlling the voltage of one body contact electrode.
Further, the Nch transistor body contact electrode 417 and the high-concentration P-type body contact diffusion layer 405B make the SOI layer 403 and the silicon substrate 401 of the Nch transistor have the same potential during the manufacturing process. Due to the high-concentration N-type body contact diffusion layer 406B, the SOI layer 403 of the Pch transistor and the silicon substrate 401 have the same potential during the manufacturing process. Therefore, damage during the process is not directly applied to the BOX film 402, a locally weak portion of the BOX film 402 does not cause surge breakdown, and no induced breakdown of the gate oxide film 409 occurs.
[0043]
Note that, in the above-described embodiment, the case where both the P-type impurity layer 205A and the N-type impurity layer 206A are provided has been described as an example, but operation is possible without providing the P-type impurity layer 205A. .
[0044]
【The invention's effect】
As described above, the present invention includes a substrate having an SOI structure including a silicon substrate, an insulating layer formed on the silicon substrate, and a semiconductor layer formed on the insulating layer, and formed on the semiconductor layer. By applying a potential to the Nch transistor body contact electrode in the semiconductor device having the MIS transistor described above, all the potentials of the channel region of the Nch transistor adjacent to the high-concentration P-type body contact diffusion layer via the silicon substrate can be fixed.
[0045]
Similarly, by applying a potential to the body contact electrode of the Pch transistor, it is possible to fix all the potentials of the channel region of the Pch transistor adjacent to the high concentration N-type body contact diffusion layer via the silicon substrate.
[0046]
Also, the Nch transistor body contact electrode makes the SOI layer of the Nch transistor and the silicon substrate have the same potential during the wiring process. Similarly, the Pch transistor body contact electrode connects the SOI layer of the Pch transistor and the silicon substrate during the wiring process. It becomes the same potential. Therefore, damage during the process is not directly added to the BOX film, and a locally weak portion of the BOX film does not cause a surge breakdown and does not cause a gate oxide film induced breakdown.
[Brief description of the drawings]
FIG. 1 is a plan view and a sectional view of a region in a semiconductor device according to an embodiment of the present invention;
FIG. 2 shows a positional relationship between an identical (N-type) conductive transistor formed in the same embodiment and an impurity layer 205A formed in a silicon substrate, and an identical (P-type) formed adjacently. FIG. 4 is a plan view showing a positional relationship between a conductivity type transistor and an impurity layer 206A formed on a silicon substrate.
FIG. 3 shows an STI 402A having an Nch transistor active region extension 301A and a Pch transistor active region extension 302A extended and patterned on a silicon substrate 401 in a manufacturing process of the manufacturing method according to the embodiment. Plan and cross-sectional view
FIG. 4 is a cross-sectional view of the manufacturing method of the embodiment after the step of FIG. 3 after the step of FIG. 3; Plan view and cross-sectional view of region where impurity layer 406A is formed
FIG. 5 is a plan view and a cross-sectional view of a region in which a gate electrode 408 is formed by patterning a gate electrode formation region 305 after the step of FIG. 4 in the manufacturing process of the manufacturing method according to the embodiment.
FIG. 6 shows that, in the manufacturing process of the manufacturing method according to the embodiment, after the step of FIG. Plan view and sectional view of formed area
FIG. 7 shows that in the manufacturing process of the manufacturing method of the embodiment, after the step of FIG. Plan view and sectional view of formed area
8 is a plan view and a cross-sectional view of a region where an Nch transistor body contact hole 414 and a Pch transistor body contact hole 416 are formed after the step of FIG. 7 in a manufacturing process of the manufacturing method according to the embodiment.
FIG. 9 is a view showing a step of FIG. 8 in which a metal film is filled in each contact hole to form an Nch transistor body contact electrode 417, a gate electrode contact electrode 418, and a Pch transistor body contact. Plan view and sectional view of a region where an electrode 419 is formed
FIG. 10 is a plan view and a sectional view of a region of a conventional semiconductor device having an SOI structure.
[Explanation of symbols]
1N Nch transistor formation region
1P Pch transistor formation region
101 Nch transistor active region
101A Nch transistor active area extension
102 Pch transistor active area
102A Pch transistor active area extension
103 Gate electrode area
104 Nch transistor body contact region
105 Nch transistor drain contact region
105A Nch transistor drain region
106 Nch transistor source contact area
106A Nch transistor source region
107 Pch transistor drain contact region
107A Pch transistor drain region
108 Pch transistor source contact area
108A Pch transistor source region
109 Pch transistor body contact region
110 Gate electrode contact area
201 Silicon substrate
202 Box film
203 SOI layer
204 STI
205 Nch transistor channel region
206 Pch transistor channel region
205A P-type impurity layer
205B High concentration P-type diffusion layer
206A N-type impurity layer
206B High concentration N-type diffusion layer
207 Gate oxide film
208 Gate electrode
209 Gate electrode silicide
210 LDD sidewall
211 Wiring interlayer film
212 Metal electrode for Nch transistor body contact
213 Metal electrode for gate electrode
214 metal electrode for Pch transistor body contact
215 Contact hole
216 Metal film
217 Contact hole
218 metal film
2N Nch transistor formation region
2P Pch transistor formation region
301 Nch transistor active area
301A Nch transistor active area extension
302 Pch transistor active area
302A Pch transistor active area extension
303 Nch transistor threshold control layer region
304 Pch transistor threshold control layer region
305 Gate electrode formation area
306 High concentration N-type impurity implantation region
307 First resist film formation area
308 Second resist film formation area
309 High-concentration P-type impurity implantation region
310 Nch transistor body contact region
311 Nch transistor drain contact region
312 Nch transistor source contact area
313 Pch transistor body contact region
314 Pch transistor drain contact region
315 Pch transistor source contact area
316 gate electrode contact area
401 silicon substrate
402 BOX film
402A STI
403 SOI layer
404 pad oxide film
405 Nch transistor threshold control layer
405A P-type impurity layer
405B High concentration P type body contact diffusion layer (High concentration P type impurity layer)
406 Pch transistor threshold control layer
406A N-type impurity layer
406B High concentration N-type body contact diffusion layer (High concentration N-type impurity layer)
407 Gate oxide film
408 gate electrode
409 Oxide sidewall
410 First resist film
411 Second resist film
412 Cobalt silicide layer
413 Oxide film between wiring layers
414 Nch transistor body contact hole
415 Gate electrode contact hole
416 Pch transistor body contact hole
417 Nch transistor body contact electrode
417A Nch transistor body contact
418 gate electrode contact electrode
418A Gate electrode contact
419 Pch transistor body contact electrode
419A Pch transistor body contact

Claims (9)

A semiconductor device having an SOI structure substrate including a silicon substrate, an insulating layer formed on the silicon substrate, and a semiconductor layer formed on the insulating layer, and having an MIS transistor formed on the semiconductor layer At
An active region comprising the semiconductor layer;
An active region extension portion made of the semiconductor layer in which the active region is extended;
A contact hole reaching the silicon substrate provided through the semiconductor layer and the insulating layer located in the body contact region of the active region extension;
And a body contact electrode made of a metal film filled in the contact hole. 2. The semiconductor device according to claim 1, wherein by applying a potential to said body contact electrode, a potential of a channel region in an active region of an adjacent MIS transistor of the same conductivity type can be simultaneously fixed. An n-type MIS transistor as the MIS transistor;
In an N-type transistor formation region in which the plurality of n-type MIS transistors are formed, a P-type impurity layer is provided on the silicon substrate located immediately below the contact hole of the n-type MIS transistor, and the P-type impurity layer is provided. 3. The semiconductor device according to claim 1, wherein the body contact electrodes of the plurality of n-type MIS transistors are electrically connected via a layer. A p-type MIS transistor as the MIS transistor;
In a P-type transistor formation region in which the plurality of p-type MIS transistors are formed, an N-type impurity layer is provided on the silicon substrate located immediately below the contact hole of the p-type MIS transistor, and the N-type impurity 4. The semiconductor device according to claim 1, wherein the body contact electrodes of the plurality of p-type MIS transistors are electrically connected via a layer. The MIS transistor includes an n-type MIS transistor and a p-type MIS transistor,
A high-concentration P-type impurity layer having the same implantation dose as the high-concentration source / drain region of the p-type MIS transistor is formed in the active region extension of the n-type MIS transistor,
The high-concentration N-type impurity layer having the same implantation dose as the high-concentration source / drain region of the n-type MIS transistor is formed in the active region extension of the p-type MIS transistor. The semiconductor device according to claim 1. In a method for manufacturing a semiconductor device having a MIS transistor using a substrate having an SOI structure including a silicon substrate, an insulating layer formed on the silicon substrate, and a semiconductor layer formed on the insulating layer,
Patterning the semiconductor layer to form an active region of the MIS transistor and an active region extension extending the active region (a);
(B) forming a trench isolation region surrounding the active region and the active region extension and having the insulating layer as a bottom;
Forming a contact hole penetrating through the semiconductor layer and the insulating layer located in the body contact region of the active region extension and reaching the silicon substrate;
Forming a body contact electrode made of a metal film in the contact hole (d). An n-type MIS transistor as the MIS transistor;
Forming a P-type impurity layer on the silicon substrate immediately below the insulating layer in an N-type transistor formation region where the n-type MIS transistor is formed after the step (b) and before the step (c); Has,
In the step (c), the contact hole of the n-type MIS transistor is formed so as to reach the P-type impurity layer,
7. The method according to claim 6, wherein in the step (d), the body contact electrode of the n-type MIS transistor is formed so as to be connected to the P-type impurity layer. A p-type MIS transistor as the MIS transistor;
Forming an N-type impurity layer on the silicon substrate immediately below the insulating layer in a P-type transistor formation region where the p-type MIS transistor is formed after the step (b) and before the step (c); Has,
In the step (c), the contact hole of the p-type MIS transistor is formed so as to reach the N-type impurity layer,
8. The method according to claim 6, wherein in the step (d), the body contact electrode of the p-type MIS transistor is formed so as to be connected to the N-type impurity layer. 9. . The MIS transistor includes an n-type MIS transistor and a p-type MIS transistor,
After the step (b) and before the step (c), simultaneously ion-implanting a P-type impurity into the active region extension of the n-type MIS transistor and the source / drain region of the p-type MIS transistor; 9. The method according to claim 6, further comprising the step of simultaneously ion-implanting an N-type impurity into the active region extension of the p-type MIS transistor and the source / drain region of the n-type MIS transistor. The manufacturing method of the semiconductor device described in the above.

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