JP2003318251A - Electrostatic chuck - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that temperature distribution of a wafer becomes worse because, to make dimensional change of the wafer small, a leakage current between an electrostatic electrode and the wafer is made small, so that a part of the wafer generates heat by heating due to the leakage current. <P>SOLUTION: This electrostatic chuck comprises a base substrate, an electrostatic electrode consisting of a conductor provided on the surface of the base substrate, and a dielectric layer covering the electrostatic electrode. Related to the base substrate, thermal expansion coefficient at 10-40°C is 1.0×10<SP>-6</SP>/°C or less, and a thickness is 3-50 mm. The dielectric layer consists of an amorphous thin film with Si as a main component, and has a thickness of 0.001-0.3 mm. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an etching process for finely processing a semiconductor wafer (hereinafter referred to as a wafer) in a semiconductor manufacturing process, a film forming process for forming a thin film, and mainly for exposing a photoresist film. The present invention relates to an electrostatic chuck that holds a wafer in an exposure processing step or the like.

[0002]

2. Description of the Related Art An electrostatic chuck attracts a wafer by placing a wafer on an attracting surface and applying a voltage between the electrostatic electrode and the wafer to generate electrostatic force such as Coulomb force or Johnson-Rahbek force. To hold. As this type of electrostatic chuck, there has been proposed one in which a dielectric made of alumina, sapphire, aluminum nitride or the like is formed on an electrostatic electrode for adsorption. For example, Japanese Patent Laid-Open No. 11-5460
Japanese Patent No. 3 discloses an electrostatic chuck made of aluminum nitride.

In recent years, the wiring of semiconductor integrated circuits has been miniaturized to improve the degree of integration. It has been desired that an electrostatic chuck for adsorbing and fixing a wafer for manufacturing such a semiconductor integrated circuit should have a small dimensional variation with respect to a temperature change during the process.

Particularly, in the exposure step, a slight dimensional change of the electrostatic chuck caused by a temperature change of 1 ° C. lowers the manufacturing yield of the semiconductor integrated circuit. Therefore, it is desired that the electrostatic chuck provided with the attracting surface is a low thermal expansion material.

Further, since the wiring pattern is exposed in a plurality of times in the exposure process, it has been necessary to control the position accuracy of the wafer at the nanomicron level. Therefore, although the wafer temperature is kept as constant as possible, it has become necessary to reduce the dimensional change due to the thermal expansion of the wafer. Above all, the temperature of the wafer changes due to Joule heat generated by a minute leakage current generated between the wafer and the electrostatic electrode, and if this leakage current is non-uniform within the wafer surface, a temperature difference occurs within the wafer surface, It is important that the leakage current from the electrostatic electrode to the wafer is uniform in the plane of the wafer, because the accuracy of the integrated circuit on the wafer cannot be improved because a partial dimensional change occurs in the plane of the wafer. It has been.

Cordierite is a typical low thermal expansion material, and Japanese Patent Publication No. 6-97675 discloses that cordierite is used as the base of an electrostatic chuck. That is, as shown in FIG. 3, an electrode 22 is formed on a substrate 21 made of a ceramic such as cordierite, a dielectric layer 23 mainly made of alumina is provided thereon, and an electrostatic chuck made of a laminated body 24 is formed. Is formed.

Further, Japanese Unexamined Patent Publication No. 2001-313332 discloses an electrostatic chuck in which an electrostatic electrode 22 is formed on the back surface of a dielectric layer 23 and is fixedly bonded to a substrate 21, as shown in FIG. 4 (a). ing. The base 21 is made of cordierite having a small thermal expansion coefficient of 10 × 10 ⁻⁶ / ° C. or less at 10 to 40 ° C.

FIG. 4B shows an electrostatic chuck composed of a dielectric layer 23 made of cordierite and a base 21 made of aluminum nitride, silicon carbide or mullite, or a dielectric layer 23 made of the same material as the base 21. As the above, an electrostatic chuck in which the electrostatic electrode 22 is embedded is disclosed.

Further, in Japanese Laid-7-135246, JP-4 thermal expansion coefficient at room temperature to 800 ° C. As shown in (c) is 4.0 × 10 ^-6 /℃~6.0×10 ^-6 / An electrostatic chuck has been proposed in which a thin film dielectric layer 23 made of aluminum nitride is formed on the surface of a conductive substrate 21 at a temperature of ° C.

[0010]

In the electrostatic chucks up to now, since the leak current between the electrostatic electrode and the wafer is non-uniform in the wafer surface, the partial heating in the wafer surface due to the leak current occurs. As a result, a part of the wafer may generate heat and the temperature distribution of the wafer may deteriorate.

Further, when the electrostatic expansion coefficient of the electrostatic chuck is large, there is a problem that the position of the wafer is displaced due to a slight temperature change.

Further, the dielectric layer may be peeled off from the substrate due to the temperature cycle.

That is, in the electrostatic chuck shown in FIG. 3, the dielectric 23 is made of ceramics mainly composed of alumina, and the coefficient of thermal expansion of the electrostatic chuck reaches several tens of times or more of the coefficient of thermal expansion of cordierite, which constitutes the substrate. Therefore, when the laminated body 24 is sintered at a high temperature and then cooled, there is a problem that the dielectric body 23 is peeled off. Further, when cooled to room temperature after co-sintering, the wafer suction surface is distorted and the flatness is lowered, or a large stress is generated between the dielectric layer 23 and the base body 21 or between the electrode 22 and the dielectric layer 23. However, there is a problem that the dimensional change occurs due to the temperature change in the room.

Further, in the electrostatic chuck of FIG. 4A, the thermal expansion of the adhesive is significantly different from that of the dielectric layer 23 and the substrate 21, so that a dimensional change of the order of 1 μm occurs due to a temperature change applied after the bonding and processing. was there.

Further, in the electrostatic chuck of FIG.
Since it is necessary to fire at a high temperature of 300 to 1500 ° C., it is thermally deformed during firing, resulting in a sintered body of 0.05 to 1 mm.
However, there is a problem that the temperature distribution is bad due to the warp.

[0016]

In view of the above-mentioned problems, the present invention comprises a substrate, an electrostatic electrode made of a conductor provided on the surface of the substrate, and a dielectric layer covering the electrostatic electrode. An electrostatic chuck, wherein the substrate has a coefficient of thermal expansion at 10 to 40 ° C. of 1.0 × 10 ⁻⁶ / ° C. or less and a thickness of 3 to
50 mm, the dielectric layer is made of an amorphous thin film containing Si as a main component, and the thickness thereof is 0.001 to 0.
It is characterized by being 3 mm.

Further, the internal stress of the dielectric layer is 10 ⁸ P.
It is characterized by being a or less.

Further, the substrate is made of rare earth oxide of 1 to 20.
It is characterized by being composed of cordierite containing mass%.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

FIG. 1 is a perspective view showing an example of the electrostatic chuck of the present invention, and FIG. 2 is a sectional view of FIG. The electrostatic chuck 4 is provided with an electrostatic electrode 2 made of a conductor on the upper surface of a substrate 1, and has a dielectric layer 3 covering the electrostatic electrode 2. The upper surface of the dielectric layer 3 is used for mounting a wafer. It is set as the surface 5.
Then, the wafer W placed on the placing surface 5 and the electrostatic electrode 2
A voltage of approximately 100 to 1000 V is applied between the wafer W and the wafer W to cause an electrostatic force between the wafer W and the electrostatic electrode 2 to attract the wafer W to the mounting surface 5.

The substrate 1 of the present invention has a coefficient of thermal expansion at 10 to 40 ° C. of 1.0 × 10 ^-6 / ° C. or less. If the substrate 1 has a coefficient of thermal expansion of 1.0 × 10 ⁻⁶ / ° C. or less, the positional deviation of the wafer W can be suppressed to nanomicrons or less even if the substrate 1 expands or contracts due to a temperature change of 1 ° C. .

For example, as the substrate 1, quartz, Mg-Al
-Si containing cordierite system, containing Li-Al-Si
LAS-based material, KZP-based material containing K-Zr-P-O,
Al ₂TiO_FiveAluminum titanate represented by and the like are preferable.
In particular, the substrate 1 made of a material containing cordierite as a main component
Has a small coefficient of thermal expansion and a large Young's modulus
Is preferred. That is, the electrostatic chuck is not used as a film forming device.
When fixing with a screw etc.
The base 1 expands and contracts little with respect to temperature changes, and the mounting surface
5 can constitute an electrostatic chuck with highly accurate flatness.
And are possible.

The substrate 1 has a thickness of 3 to 50 mm. In particular, the thickness of 3 mm or more requires rigidity that does not deform when the flatness of the mounting surface of the electrostatic chuck is processed. Although the dielectric layer 3 is thin and has a small internal stress, when the thickness of the substrate 1 is less than 3 mm, warpage of the substrate 1 after film formation may become large. The reason is that the flatness of the mounting surface 4 cannot be kept below 0.001 mm due to the deformation due to the difference in thermal expansion due to the temperature difference during use.

The thickness of the substrate 1 is preferably 50 mm or less, more preferably 30 mm or less for a stage of an exposure apparatus that requires lightweight and compactness.

The dielectric layer 3 is an amorphous thin film containing Si as a main component. This is because, in the manufacturing process of a semiconductor device, the dielectric layer 3 becomes particles and is less likely to scatter during exposure or film formation on minute wiring of the device. That is, if the dielectric layer 3 is a film containing Si as a main component, the falling powder of the dielectric layer 3 can be easily gasified by the fluorine or chlorine-based gas used when cleaning the mounting surface 5. Therefore, the particles are not scattered and remain on the wafer W.

Further, the reason why the amorphous thin film containing Si as a main component is used is that the crystalline film is tightly bound between the crystal lattices and the interstitial distance is hard to change due to external stress, so that the stress applied to the crystal film is relaxed. The amorphous thin film containing Si as a main component, unlike the crystalline film, has a function of varying the interstitial distance with respect to external stress, unlike the crystalline film. It can be made smaller than a crystalline film. Therefore, the thermal expansion coefficient of the substrate 1 is set to 1.0.
Even if the temperature is not more than × 10 ^-6 / ° C, the dielectric layer 3 is less likely to be peeled off from the substrate 1 or the electrostatic electrode 2.

Further, the thickness of the dielectric layer 3 is 0.001 to
The thickness is 0.3 mm. If the thickness is smaller than 0.001 mm, the dielectric layer 5 may be dielectrically broken down when a voltage is applied to the wafer W and the electrostatic electrode 2. Moreover, when the dielectric layer 3 is washed, the dielectric layer 3 is easily dropped and consumed, which is not preferable.

On the other hand, if the thickness of the dielectric layer 3 is thicker than 0.3 mm, a large warp as shown in FIG. 6 (a) occurs after the film formation due to the difference in thermal expansion between the substrate 1 and the dielectric layer 3, and thereafter. When the mounting surface 5 of the electrostatic chuck is processed to be flat, as shown in FIG. 6B, the variation in the thickness of the dielectric layer 3 due to the warp increases. Then, the resistance value of the thin portion of the dielectric layer 3 becomes small, and the leakage current flowing between the electrostatic electrode 2 and the wafer W locally becomes large. Therefore, the wafer W
The variation of the leak current in the plane is large, the temperature of the wafer W is uneven due to the heat generated by the leak current, and the in-plane position of the wafer W is deviated due to the difference in the thermal expansion due to the temperature difference in the plane of the wafer W. This is because exposure may not be possible.

Further, the internal stress of the dielectric layer 3 is 10 ⁸ Pa.
The following is preferable. In the case of a thin film having an internal stress of more than 10 ⁸ Pa, as shown in FIG. 6A, the warp after the film formation on the substrate 1 or the electrostatic electrode 2 is large, and the dielectric layer 3
Stress increases, and the dielectric layer 3 may be cracked or peeled off after the film formation. Particularly, in the electrostatic chuck for an exposure apparatus, it is necessary to perform a process of flattening the dielectric layer 3 after forming the dielectric layer 3 in order to set the flatness of the mounting surface 5 to 1 μm or less. Dielectric layer 3 due to processing stress
Is easily peeled off.

Similarly to the above, as shown in FIG. 6B, in a thin film in which the internal stress of the dielectric layer 3 exceeds 10 ⁸ Pa, the warp after the dielectric layer 3 is formed is large, and If the layer 3 is processed flat, the thickness of the dielectric layer 3 becomes uneven. When the thickness of the dielectric layer 3 becomes non-uniform, the resistance between the electrostatic electrode 2 and the wafer W becomes non-uniform in the plane of the wafer W, and the resistance of the dielectric layer 3 becomes large when used as an electrostatic chuck. A large leakage current flows in a small area, and the leakage current causes heat generation, resulting in non-uniform temperature of the wafer.

The stress inside the dielectric layer film can be measured by the method shown in FIG. That is, an AF measuring 40 mm long, 10 mm wide, and 0.1 mm thick is used as a measurement sample.
A film to be the dielectric layer 3 is formed on the glass substrate made of 45 with a thickness of 10 μm.
The internal stress σ can be obtained from the warp amount δ of the AF45 glass by the equation 1 after forming a film of about m. σ = (E × δ ×
Ts ² ) / (3 × (1-ν) × L ² × Tf) (Equation 1) E is the Young's modulus of the substrate 1, Ts is the thickness of the substrate, ν is the Poisson's ratio of the substrate, and Tf is the dielectric. The thickness of the layer.

The material forming the substrate 1 preferably contains cordierite in a proportion of 1 to 20% by weight in terms of oxide of a rare earth element. By containing the rare earth element, densification during sintering is promoted, and it becomes possible to easily obtain a densified body having a relative density of 95% or more. As a result, the porosity becomes 2% or less, the outgas generated from the substrate 1 is small, and the EU
It is suitable for use in processes performed in a high vacuum such as V exposure, EB exposure, and sputtering.

Next, the manufacturing method and structure of the electrostatic chuck 4 will be described.

In order to manufacture an amorphous thin film having a small internal stress as the dielectric layer 3, there is a catalytic CVD method or the like. For example, an amorphous film containing Si as a main component (hereinafter abbreviated as a) is used as a dielectric layer by reducing the ratio of source gas H ₂ / SiH ₄ or B ₂ H ₆ / SiH _4. 3 can be formed into a film. As the film forming the dielectric layer 3, an a-Si-based or a-Si alloy-based material or a-S
i ・ a-SiC ・ a-SiN ・ a-SiO ・ a-SiG
e-a-SiCN-a-SiNO-a-SiCO-a-
SiCNO.a-AlO etc. can be used. Dielectric layer 3
Is an element of Group 3a of the periodic table (hereinafter abbreviated as Group 3a element)
The electric characteristics can be adjusted by containing a Group 5a element (hereinafter abbreviated as Group 5a element) or an element such as carbon (C), nitrogen (N), oxygen (O). Boron (B) is used as the group 3a element and the group 5a element, respectively.
Phosphorus (P) has an excellent covalent bond property and can sensitively change semiconductor characteristics. In order to contain B and P together with C, N, O and the like elements, the dielectric layer 3 contains 0.1 to 3 a group 3a element.
It is preferable to contain 20,000 mass ppm, and if it is a group 5a element, it is preferable to contain 0.1 to 10,000 mass ppm. Further, the content of elements such as C, N, and O may be changed in the thickness direction of the dielectric layer 3 to provide a gradient. In that case, if the average content of the entire dielectric layer 3 is within the above range. Good.

A method for reducing the internal stress of the film is as follows.
Change the component ratio of the source gas when forming a-Si film
It is possible by That is, H of the source gas₂/ S
iH _Four, B₂H₆/ SiH_FourBy reducing the ratio, the internal response
Power is 10⁸Amorph mainly composed of silicon of Pa or less
A thin film can be made.

On the other hand, in the thin film manufacturing method, the film forming speed is about 10 μm / hour, and it is not economical to form a film of 0.3 mm or more.

Next, a method of manufacturing the base 1 made of cordierite-based ceramics will be described. 1 to 20% by mass, preferably 5 to 1% by weight of rare earth element oxide powder having an average particle size of 10 μm or less in 10 μm or less cordierite powder.
It is preferable to add 5% by mass, and more preferably 8 to 12% by mass. Cordierite 100 without additives
Even if the content is% by mass, densification is possible, but the firing temperature is high,
Since the calcinable temperature range is very narrow at ± 5 ° C, it is difficult to stably manufacture a densified material. On the contrary,
If the content of the rare earth element is 1% by weight or more, it reacts with the cordierite component during firing to form a liquid layer, which has the effect of increasing the sinterability, and enables firing at low temperature and firing. Since the temperature range can be expanded to about ± 25 ° C, mass productivity can be improved.
Rare earth elements contained in cordierite include Y,
Examples thereof include Yb, Lu, Er, Ce, Nd, Sm and the like.
Among these, Y and Yb are preferable because they can be obtained at low cost.

Although this rare earth element exists at the grain boundary of the cordierite crystal, this rare earth element is RE ₂ O ₃ .Si.
It is desirable to exist as a crystal phase of a silicate compound such as O ₂ or RE ₂ O ₃ .2SiO _2. This is to reduce the thermal expansion coefficient of the substrate 1 by crystallization of the grain boundary phase.

The conductive electrostatic electrode 2 forming the electrode 2 may be made of a conductive material such as metal, and the manufacturing method is not particularly limited. For example, glow discharge decomposition method, various sputtering methods, various vapor depositions. The film can be formed by a method, an ECR method, a photo CVD method, a catalytic CVD method, a reactive vapor deposition method, or the like. The thickness of the electrostatic electrode 2 is 0.0001 to 0.1 m.
m is sufficient. Electrostatic electrode 2 if 0.0001 mm or less
Can not be obtained in the plane. When the thickness is 0.1 mm or more, peeling easily occurs at the interface with the substrate 1 due to the difference in thermal expansion from the substrate 1. In particular, the interface that is the surface of the substrate 1 has Ra 0.3.
As described above, by setting it to preferably 0.7 or more, the electrostatic electrode 2 in which peeling hardly occurs can be formed.

When the dielectric layer 3 is formed of the amorphous thin film of the present invention, the internal stress of the dielectric layer 3 is small. After the dielectric layer 3 is formed, the substrate 1 has a warp of 50 μm or less, and the thickness of the dielectric layer 3 becomes uniform.
It is possible to reduce the variation in resistance within the plane. As a result, the in-plane temperature of the wafer W can be made uniform. That is, it is possible to manufacture an electrostatic chuck having a high degree of positional accuracy in which warpage of the substrate 1 when forming the dielectric layer 3 is small and peeling or cracking of the dielectric layer 3 does not occur.

[0041]

Example 1 A cordierite powder having an average particle size of 3 μm was added to Y ₂ O ₃ , Yb ₂ O ₃ and Er ₂ as sintering aids.
O ₃ and CeO ₂ powders were prepared as shown in Table 1, a binder and a solvent were added, and the mixture was mixed for 24 hours and dried to obtain granulated powder. Then, the granulated powder was filled in a mold and pressure-molded at a pressure of 98 MPa to produce a molded body. Then, the molded body was put in a silicon carbide sagger under a reducing atmosphere and fired in an electric furnace at the firing temperature shown in Table 1.

The obtained sintered body was polished to 3 × 4 × 15 m
10 ~ 4 of this ceramic is polished to a size of m
The average coefficient of thermal expansion up to 0 ° C is JIS R3251-19
The relative density measured by the method specified in
The porosity and bulk density were measured and determined using the method specified in S C2141-1992. Furthermore, JIS R162
The powder density of the pulverized sample measured by the method specified in 0 was measured, and the above-mentioned bulk density was divided by the powder density to calculate the relative density.

Further, a sintered body produced by the same method was polished into a disk shape having an outer diameter of 320 mm and a thickness of 10 mm, and the flatness of the upper and lower surfaces was set to 1 μm or less, and the thickness of 1 μm was formed on almost the entire upper surface. An aluminum film was formed by sputtering to form the electrostatic electrode 2.

Next, the base 1 was set in a catalytic CVD apparatus, and an a-Si film was formed on the upper surface of the electrostatic electrode 3 under the conditions of the base temperature of 260 ° C. and the internal pressure of the apparatus of 13.3 Pa. A H ₂ / SiH ₄ mixed gas was used as the Si source, the flow rates of the H ₂ and SiH ₄ gases were 100 sccm, and H ₂ containing 0.5% of B ₂ H ₆ was added as necessary to control the characteristics of the film. Gas was supplied. The film forming rate was 11.5 μm / hour.

At the same time, the internal stress of the dielectric layer formed on the substrate made of AF45 was measured by the above-mentioned method.
It was 2 × 10 ⁷ Pa. Further, the step between the film-formed portion and the portion masked with the stainless steel mask was measured with a dial gauge and used as the thickness of the formed film.

Then, the flatness of the surface on which the electrostatic electrode was formed was measured. Further, the dielectric layer is placed on a tin lapping machine 10
Using a diamond slurry of μm, lapping was performed as a mounting surface. The mounting surface has a flatness of approximately 1μ due to lapping.
m, surface roughness Ra 0.1.

For the adsorption force, a 25 mm square Si plate was used in vacuum, a DC voltage of 500 V was applied between the Si plate and the electrostatic electrode to adsorb the Si plate, and then the Si plate was peeled off via a load cell. The force (F) applied at that time was measured using a load cell, F was divided by the area of the Si plate, and the adsorption force per unit area was calculated.

Further, a 25 mm square Si plate is moved over the entire mounting surface, and the current between the Si plate and the electrostatic electrode is measured as a leakage current. The difference between the maximum and minimum values of the leakage current is measured. Was calculated as the leakage current difference.

As an evaluation method of the positional accuracy of the electrostatic chuck, the electrostatic chuck was placed in an ambient temperature of 20 ° C. and 30 ° C., and the amount of wafer deformation due to this temperature difference was measured as a positional deviation.

First, 200 is applied to the surface of a 300 mm wafer.
Laser marking was performed at a temperature of 20 ° C. at two points separated by mm, and the distance between the two points was measured at 20 ° C. Next, a 300 mm wafer is mounted on the electrostatic chuck and attracted,
Laser macking at 30 ° C at two points 2 mm apart
The distance between two points was measured at 0 ° C., and the positional deviation was taken as the amount of deformation. In addition, a silicon wafer with a diameter of 300 mm is at 30 ° C.
The temperature distribution in the silicon wafer surface after adsorption for 30 minutes was measured by an infrared thermometer to measure the temperature difference in the silicon wafer. The results are shown in Table 1.

[0051]

[Table 1]

Sample No. of the present invention. The coefficient of thermal expansion of 3 to 5 and 7 is less than 1.0 × 10 ⁻⁶ / ° C., and the thickness of the substrate is 3 to
50 mm, the dielectric layer is composed of an amorphous thin film containing Si as a main component, the film thickness is 0.001 to 0.3 mm, the positional deviation of marking is 1.0 μm or less, and the temperature difference is 5 ° C. or less. It was the preferred electrostatic chuck.
Further, the adsorption force showed a large adsorption force of 1 × 10 ⁴ Pa or more, which was a good result.

On the other hand, the sample No. having a coefficient of thermal expansion larger than 1.0 × 10 ⁻⁶ / ° C. No. 6 has a marking displacement of 2.
It was 5 μm, which was not very good.

Sample No. 1 was not preferable because the thickness of the substrate was as small as 1 mm and the positional deviation was as large as 1.1 μm. Further, in the sample No. 9, since the thickness of the substrate was as large as 60 mm, the temperature difference of the wafer was as large as 1.2 ° C. and the positional deviation was also as large as 1.2 μm. Therefore, the thickness of the substrate is 3
It has been found that -50 mm is preferable.

Sample No. 2 had a dielectric layer thickness of 0.00
It was as small as 05 mm, and dielectric breakdown occurred during the evaluation.
In addition, the sample No. In No. 8, the thickness of the dielectric layer was as large as 0.4 mm, and the thickness variation of the dielectric layer was generated, and the temperature variation of the wafer was 1.1 ° C. and the positional deviation was also as large as 1.1 μm.

Therefore, the thickness of the dielectric layer is 0.001 to
It has been found that 0.3 mm is preferred. (Example 2) Next, using a substrate having the same composition as that of sample No. 4 of Example 1 and a thickness of 10 mm, the flow rate of the raw material gas was changed to form a dielectric layer having different physical properties, and the temperature was -10 to 100 ° C.
Was subjected to a thermal cycle, and peeling of the film for each cycle was observed.

For heating and cooling, the sample was heated with a hot / cold air tester to 3
The temperature was raised and lowered at a rate of 0 ° C./hour, and the maximum and minimum temperatures were maintained for 30 minutes. The results are shown in Table 2.

[0058]

[Table 2]

Sample No. having an internal stress of 10 ⁸ Pa or less. Three
Nos. 1 to 33, 35, 37, and 38 had good results without peeling even after 100 thermal cycles.

However, sample No. 1 having an internal stress of 10 ⁸ Pa or more. In Nos. 34 and 36, peeling occurred after 100 cycles, which was not good.

[0061]

According to the present invention, there is provided an electrostatic chuck provided with a substrate, an electrostatic electrode made of a conductor provided on the surface of the substrate, and a dielectric layer covering the electrostatic electrode. The substrate has a coefficient of thermal expansion of 1.0 × 10 ^{−6 at} 10 to 40 ° C.
/ C or less, the substrate has a thickness of 3 to 50 mm, the dielectric layer is an amorphous thin film containing Si as a main component, and the thickness is 0.001 to 0.3 mm. The leakage current between the wafer and the wafer,
The temperature distribution of the wafer becomes smaller.

Further, the coefficient of thermal expansion of the electrostatic chuck is small, and the position of the wafer can be prevented from shifting.

Further, it is possible to provide a highly reliable electrostatic chuck in which the dielectric layer does not peel off from the substrate due to the temperature cycle.

[Brief description of drawings]

FIG. 1 is a perspective view showing an electrostatic chuck of the present invention.

FIG. 2 is a sectional view showing an electrostatic chuck of the present invention.

FIG. 3 is a cross-sectional view showing a conventional electrostatic chuck.

4A to 4C are cross-sectional views showing another conventional electrostatic chuck.

FIG. 5 is a diagram showing a method for measuring internal stress.

6A and 6B are cross-sectional views showing a conventional electrostatic chuck.

[Explanation of symbols]

1: substrate 2: electrode 3: dielectric layer W: Wafer 4: Electrostatic chuck 5: Mounting surface 21: substrate 22: electrode 23: dielectric layer 24: Laminated body 25: Mounting surface 26: Adhesive

Claims (3)

[Claims] 1. An electrostatic chuck comprising a base, an electrostatic electrode made of a conductor provided on the surface of the base, and a dielectric layer covering the electrostatic electrode, wherein the base is 10 to 10. The thermal expansion coefficient at 40 ° C. is 1.0 × 10 ⁻⁶ / ° C. or less, the thickness is 3 to 50 mm, the dielectric layer is an amorphous thin film containing Si as a main component, and the thickness is 0.00.
An electrostatic chuck having a size of 1 to 0.3 mm. 2. The electrostatic chuck according to claim 1, wherein the internal stress of the dielectric layer is 10 ⁸ Pa or less. 3. The base contains 1 to 20% by mass of a rare earth oxide.
An electrostatic chuck according to claim 1 or 2, wherein the electrostatic chuck comprises cordierite.