JP2003317484A - Device and method for reducing noise of mixed mode integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device and a method for an integrated circuit in which switching noise is reduced. <P>SOLUTION: This circuit comprises an inverter circuit network having at least two transistors, a micro-battery such as a thin film or the like connected to the inverter circuit network, and a resistor of which one end is connected to the micro-battery and the other end is connected to a power source. In a fixed period when the transistor is transitted from a logic state to the other logic state, transistors more than one are turned on. When control is not performed, this state causes high current and voltage spike of the result. Peak voltage disturbing an analog element is prevented by extracting current request of this transition period from the micro-battery. As the battery is charged again gradually, voltage spike is not caused. Further, an integrated circuit component is separated from a power source line by the resistor limiting a current for the line. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to semiconductor integrated circuits, and more particularly to apparatus and methods for reducing noise in mixed mode semiconductor integrated circuits.

[0002]

BACKGROUND OF THE INVENTION In today's environment, semiconductors are those that have both analog and digital components, commonly referred to as mixed signal or mixed mode integrated circuits (ICs). obtain. Integrating analog and digital devices on the same chip can reduce cost, area and power requirements,
This is an important consideration in the manufacture of ICs. However, combining analog and digital devices on the same substrate poses a design risk. First, switch noise from high speed digital circuits is likely to interfere with and damage high frequency analog circuits. Digital circuits usually switch rapidly between predetermined voltage levels and are therefore transient (temporary) in the wire.
Induces noise. Analog circuits, which are analog operated at a large number of voltage levels and frequencies, are susceptible to induced noise, while digital circuits are well able to withstand the interference of induced noise.

Integrated circuits include some devices that are high performance devices that are sensitive to noise. Rapid changes in charging or discharging current can cause brownouts. This transitional voltage change can be so great as to interfere with the performance of these sensitive devices.

Substrate noise is a factor in many applications. For example, substrate noise is a problem in phase locked loop systems (phase locked loop systems (PLL)) and inverters (phase anti-reciprocal circuits). PLLs are used in numerous applications, including disk drive data recovery, wired and wireless communications, high speed microprocessors and memory.

Inverters (also called flip-flops) are also widely used. Flip-flops play an important role in reading and writing bits of words in memory devices. Flip-flops typically include fast switching circuits that can be addressed for writing to or reading from the flip-flop. (Need for definition of flip-flop).

When there is no switching between the steady state or the static state, that is, the output state, no current flows from the power supply into the flip-flop. Flip-flops typically include a network of transistors connected to a power supply and ground. In the steady state, one transistor (or group of transistors) is turned on and another transistor (or group of transistors) is turned off. To switch from one transistor to another, the power supply is switched from one state to another, for example from low to high, which draws current.
When one transistor is turned off and another is turned on, both transistors are turned on for a period of time. During this period high currents are present in the network. This high current causes a voltage spike, which causes noise during the switching process. As current is drawn through the wires in the network, resistance develops and the voltage begins to drop, resulting in a transitional voltage across the IC. These transition states can propagate along the electrical wires that provide power to the integrated circuit from the printed circuit board to which the integrated circuit board is attached. This transition state produces radio frequency (RF) radiation that can interfere with the proper operation of other circuits on the printed circuit board as well as other circuits within the integrated circuit itself.

Several attempts have previously been proposed to solve the switching noise problem. One proposed solution focuses on controlling sudden surges in current. U.S. Pat. No. 5,905,399, entitled "CMOS Integrated Circuit Conditioner for Reducing Power Supply Noise," issued May 18, 1999, discloses a set of logic gates during a switching transition state. It includes a complementary metal oxide semiconductor (CMOS) regulator that provides a constant current to it. This arrangement disconnects the external electrical supply shared by the analog circuitry and supplies current to the power rails. This current is kept almost constant by the clamping action of the clamping transistor. The excess charge of the transient current is supplied by the capacitor and the capacitor is replenished during non-switching times.

Another attempt to solve the noise problem involves the addition of decoupling capacitors placed close to the active device. Decoupling capacitors stabilize the current flow to these devices. However, although the capacitor absorbs some of the voltage, it still produces a spike.

Yet another attempt to solve the substrate noise problem is:
It contains an active method that uses a linear feedback loop. This method involves sampling the noise in the analog receiver portion of the noise and directing the noise to the input stage of a negative feedback loop. After being amplified in the opposite phase,
The noise is reinjected into the substrate again. The reinjected noise, which has the opposite phase of that of the original noise traveling in the substrate, can be used to cancel up to 83% of the original noise. This solution operates on a mixed mode integrated circuit operating in lower frequency, lower power portable electronics having a slower digital clock speed.

Yet another attempt to handle switching noise involves partitioning analog and digital functions. This method requires unique manufacturing processes and custom designs. For example, U.S. Pat. No. 6,020,614, entitled "A Method for Reducing Substrate Noise Coupling in Mixed Signal Integrated Circuits," issued February 1, 2000, discloses that analog circuits are separate from digital circuits. It is suggested that the noise can be reduced by forming the boundary band between the analog circuit and the digital circuit of the semiconductor substrate having the power supply bus.
In addition, this patent provides interconnect signal lines such that isolated wiring between circuits can be functionally interacted with other circuits while the interconnect substrate noise from other circuits remains low. Is disclosed. However, separating analog devices from digital devices can waste valuable semiconductor space, which is an important consideration in integrated circuit design.

Yet another attempt to solve the switching noise problem is US Pat. No. 5,649,160 entitled "Reduction of Noise in Integrated Circuits and Circuit Devices," issued July 15, 1997. Is described in. This patent suggests that noise can be reduced by shaping it from a digital circuit and concentrating it into a single or small number of frequency spectrum portions. This solution is less important at frequencies where there is noise in analog circuits and therefore relies on the concept of carefully placing spectral peaks or groups of peaks from digital circuits to reduce or eliminate interference.

Each of the various prior art attempts to solve the switching noise problem has its limitations. Therefore, there is a need for an apparatus and method that substantially reduces switching noise in mixed mode integrated circuits.

[0013]

SUMMARY OF THE INVENTION The present invention is directed to overcoming the problems associated with switching noise that occur in integrated circuits having analog and digital components by including a microbattery on the integrated circuit. There is. Noise occurs in integrated circuits through several environments. Noise typically occurs when some integrated circuit, such as an inverter, transitions from one logic state to another. For example, suppose inverter A must be turned on and inverter B must be turned off. During this transition state, both inverters are turned on for a certain period of time, during which the transition state is completed. In this case, high currents are present resulting in voltage spikes and noise generation.

An integrated circuit according to the invention for reducing switching noise is provided with an inverter network having at least two transistors, a gate network connected to the inverter network, and connected to the inverter. It includes a microbattery and a resistor having one end connected to the microbattery and the other end connected to a power source. In steady state, the microbattery is not charged. When charged, a nominal current will flow through the microbattery. When the inverter goes into a transition state and a current surge results in a voltage spike, the current demand to reduce that voltage is drawn from the microbattery. The integrated circuit therefore avoids flowing into the analog element and creating peak voltages that disturb the analog element. Furthermore, the battery is gradually recharged so that no voltage spikes occur. Furthermore, the elements of the integrated circuit are isolated from the power supply line, V _DD , by resistors that limit the current drawn from that line.
Alternatively, the inverter can include a bipolar RAM storage cell containing two cross-coupled three-emitter transistors.

In another embodiment of the invention, switching noise is reduced in non-switched integrated circuits.
This aspect includes a plurality of transistors in which one group of transistors is on-logic and another group of transistors is off-logic. A microbattery is connected to each group of transistors. Knowing the state of a transistor is determined by whether the associated microbattery is charged. To write to a cell, charge the associated microbattery and turn on the associated transistor.

Another embodiment of the present invention for reducing switching noise involves a random access memory network having a microbattery and a resistor for reducing switching noise. Random access memory circuitry includes a plurality of cells. These cells contain an inverter circuit. Adding a microbattery provides a capacitor 130 that receives charge from the microbattery. Therefore, this capacitor can handle current surges that cause voltage spikes on the power line. The resistor further limits the current drawn from the voltage line.

Yet another embodiment of the present invention includes a random access memory network, the network including a microbattery and a resistor circuit, each microbattery and resistor circuit comprising: , A microbattery and a resistor circuit are associated with each cell of the network that operates independently. A localized microbattery source for each cell increases the speed of the network while reducing switching noise and resistor size.

Accordingly, the present invention is directed to achieving at least one or more of the following objects, or achieving a combination of the following objects.

It is an object of the present invention to provide an apparatus and method for reducing switching noise in a mixed mode integrated circuit so that the elements of the integrated circuit are not damaged by transitional noise.

An apparatus for reducing switching noise in an integrated circuit that utilizes a microbattery to supply current to the integrated circuit when there is an increase in power demand during the transition from one logic state to another. And providing a method.

An apparatus and method for using a microbattery in an integrated circuit to indicate whether the associated transistor is off or on.

An apparatus and method for reducing switching noise in an integrated circuit using a microbattery that efficiently uses semiconductor space.

An apparatus and method for isolating power supply lines from voltage spikes.

Other objects, advantages and features of the apparatus and method of the present invention are set forth in part in the description which follows and in part are obvious from the description of the invention or can be learned by practice of the invention. It can be done. The objects, advantages and features of the present invention will be realized and attained by the components and combinations particularly pointed out in the appended claims.

[0025]

BRIEF DESCRIPTION OF THE DRAWINGS Reference will now be made in detail to the preferred embodiments of the examples of the invention illustrated in the accompanying drawings. 1-5 depict various surfaces for protecting integrated circuit devices from noise.

FIG. 1 shows a transistor 2 connected to an inverter circuit 12 including cross-coupled transistors 14, 16, 18 connected at nodes 22, 24.
Single MOS-for use in a mixed mode integrated circuit having 6, 28, 30 and 32 gate networks
3 is a circuit diagram of the RAM cell 10. FIG. At node 36, microbattery 34 is connected to inverter circuit 12. At one end 42 a resistor 38 is connected to the microbattery 34, and at the other end 44 to a power supply 42 or V _DD . For purposes of illustration, FIG. 1 shows a single cell 10, but the invention is not limited to single cell 10. Inverter circuit 12 may be used to read and write binary information within cell 10.

The transistors 26, 28 forming the first gate network are connected to the one-bit line 46. Transistor 3 forming a second gate network
0 and 32 are connected to the 0 bit line 48. These bit lines 46 and 48 are connected to one bit line 46 or 0
A method of determining the state of the storage cell is provided by detecting whether or not current is flowing in the bit line 48.

The address lines 44 and 46 are used for reading and writing to the storage cell of the inverter circuit 12. To carry out read and write operations, the address lines 44, 46 are excited by clock pulses (not shown). The clock pulse typically contains a square wave stream representing a voltage, such as a high value of 0 volts, a low value of -10 volts (or -V _DD ), for example.

In the static state both address lines 4
4, 46 are at ground potential. In this state, one transistor 18 is on and one transistor 14 is off. For example, if transistor 18 is on and transistor 14 is off, the voltage at node 24 is low, eg -V _DD , and the voltage at node 22 is high, eg 0. The address lines 44, 46 are pulsed with clock pulses to read the data in the cells. The current flows through the 1-bit line 46, which is the one that is low (ie, −V _DD ), and the gate devices 26 and 2
8 and through the on transistor 18. Since the transistor 14 is off, this is also a low voltage (ie -V).
Little current flows in the 0 bit line 48 at _DD ).

To write data into the cell, the address lines 44, 46 are again pulsed with clock pulses and the 1-bit line 46 is grounded. Grounding the 0 bit line 48 pulls node 22 to ground, turning off transistor 18 and turning on transistor 14, while inverter circuit 12 transitions from one logic state to another.

However, while the inverter circuit 12 transitions from one logic state to another, both transistor 18 and transistor 14 are on for a short period of time. During this transitional period, a large amount of current surges through the device 10. This current surge triggers the corresponding voltage spike. If it is not controlled, this voltage spike causes noise to propagate to several components, such as analog devices, power buses, integrated circuit structures, power lines or silicon substrates. Current is needed to reduce voltage spikes.

In the steady state, the micro battery 34
Is not charged. However, when the inverter circuit 12 changes its logic state, that is, when it flips, a surge of current occurs and the resulting peak voltage flows to components including analog elements and disturbs them instead of disturbing them. It is absorbed by the battery 34. Since the micro battery 34 is gradually charged, no voltage spike occurs. When current is needed to reduce the high voltage, it is taken from the microbattery 34, and transistors and other devices are pulled from the power line 44, ie, the power supply V _DD , by a resistor 38 which limits the current drawn from the line 44. To be isolated. The size of the resistor 38 can vary depending on the size of the microbattery 34 used in the device 10.

A suitable microbattery 34 for use in the present invention is the thin film battery available from Excelatron Solid State LLP of Smyrna Sweet Jero's Well Street 1640, Georgia. This Exceratron Company is incorporated by reference in its entirety into U.S. Pat. No. 5,569,569.
It owns proprietary and licensed thin film battery technology, including the microbatteries disclosed in US Pat. No. 520 and US Pat. No. 5,597,660. Applicant's US patent application Ser. No. 09 / 286,11, entitled “Thin Lithium Film Battery,” filed Apr. 2, 1999, which is incorporated herein by reference.
No. 2 and US patent application Ser. No. 09/54 entitled “Method for manufacturing thin film batteries” filed April 5, 2000
No. 3,121, U.S. patent application Ser. No. 09 with the name “Method for manufacturing thin film battery” filed on Mar. 28, 2000
/ 536,594, US patent application Ser. No. 09 / 543,280, entitled “Method for Manufacturing Thin Film Battery Anodes”, filed Apr. 5, 2000, and entitled “Protective Package,” Mar. 28, 2000. Patent application for manufacturing method of thin film battery having 0 '
9 / 536,535 are incorporated herein by reference. Thin film batteries generally include a stacked form of film starting with an inert ceramic or aluminum substrate on which the cathode current collector and cathode are mounted.
A solid state electrolyte is deposited on the cathode, an anode is then deposited on the electrolyte, and an anode current collector is mounted on the anode.
A protective coating is typically applied to the entire cell. The preferably thin film battery is rechargeable.

FIG. 2 shows a circuit diagram 50 of bipolar transistors 52, 54, gate devices 56 and 58, microbatteries 60, 62 and address lines 64, 66 according to the second aspect of the invention. The gate devices 56, 58 include bipolar transistors, each connected to a bit line 68, 70.
The gate device 58 is connected to the 1-bit line 68, and the gate device 56 is connected to the 0-bit line 70.

In the initial stage, one bipolar transistor 52 is on and the other bipolar transistor 54 is off. The state of the transistors 52, 54 can be determined by examining which of the micro batteries 60, 62 is being charged. In the charged state, the 1-bit line 68 is low so that the transistor 52 is on. The address lines 64, 66 use clock pulses (not shown) to change the logic states of the transistors 52, 54 from a low value to a high value, ie -V.
Pulsed from _DD to 0. Micro battery 6
Charging 0, 62 allows the writing of one of the transistors 52, 54 and the transition of the logic states of the transistors 52, 54. During that transition, the microbatteries 60, 62 provide current when removal of voltage spikes that can cause system noise is required.

FIG. 3 shows a bipolar storage cell 72 including two cross-coupled three-emitter transistors 74, 76, a microbattery 78 and resistors 80, 82 and 84 to reduce switching noise. 2 shows a schematic circuit diagram of Transistor 7
One emitter 86 of 4 serves to sense or write logic 1 while transistor 74 conducts. One emitter 88 of transistor 76
Serves to read or write a logic 0 when transistor 76 is conducting. The emitter 90 of the transistor 76 and the emitter 92 of the transistor 74 are connected to the address line X94. Emitter 96 of transistor 76 and transistor 74
The emitter 98 of is connected to the address line Y100. Typically, the address lines 94, 100 have low values,
That is, the current from all conducting transistors that are kept at logic 0 is
It will flow out from 4,100.

Hello Bipolar RAM Storage Cell 7
If 2 is one of a number of cells in the matrix for addressing individual cells 72, address lines 94, 10
Activate the transistor so that 0 becomes logic 1. No change occurs in those cells because the remaining cells in the unaddressed matrix have at least one of their respective address lines at logic zero. Cell 72
The current from the conducting transistor is shunted from these address lines to the read line and then to one of the read amplifiers (not shown).

To write to the cell 72, the cell 72
Are addressed as above. A logic one applied to the write emitter input 86 pulls the transmitter 74 output to a logic zero. The logic 0 voltage on the output of write emitter 86 applies the same low voltage to all emitters of cell 72. No change occurs if the cell 72 is in the desired state. If the cell 72 is not in the desired state, a low voltage applied to the emitter 86 of the transistor 76 in the off state will turn on the transistor 76 and turn off the enable transistor 74.

When transistor 76 is turned on and transistor 74 is turned off, both transistors 74, 76 will be on for a period of time. During this period there is a high current, causing a voltage surge. Microbatteries 78 have been added to the network to prevent this surge from propagating noise to the device. Microbattery 78 functions like a capacitor and provides a temporary current. Therefore, when a voltage surge occurs and current needs to be drawn to reduce the voltage, the current is drawn from the microbattery 78. Resistor 80 isolates voltage line 102 from other elements and limits the amount of current drawn from line 102. Once discharged, the microbattery 78 is gradually recharged so that no voltage spike occurs.

FIG. 4 shows a schematic diagram of a random access memory network 104 having a microbattery 106 and a resistor 108 to reduce switching noise. Random access memory network 104
Is a plurality of cells 110, 112, 114, 116 and 11
8 (5 cells are shown for illustrative purposes only). Cells 110, 112, 114, 116 and 118 include the inverter circuit shown in FIGS. 1 and 3 or the transistor form shown in FIG.

Each cell 110, 112, 114, 11
6 and 118 have input / output leads for XY addressing 120, 122 and for read / write functions 124, 126. The read line 124, once enabled, for each cell 110, 112, 114, 116 and 11
Detect the digital information stored in each of the eight.
The write line 126 allows digital information to be stored in the selected cell. Decoder 128 decodes the addressing information and selects individual addressed cells selected to undergo a read or write transaction. Each cell 110, 11
2, 114, 116 and 118 are capacitors 130,
For example, a 125 microfarad capacitor may be included, which capacitor 110, 112, 11 when read / write or write / read upon transition from an on / off logic state or vice versa.
It serves to draw some current from 4, 116, 118. However, the capacitor 130 stores current until it is fully charged. However, the condenser 130
Cannot quickly charge, so during a transition of logic states, when there is a large amount of current, it slowly charges and maintains 0 volts until charged, thus handling a large amount of current surge. I can't do it. High current is present during this period. Therefore, current surges through network 104. A voltage spike may flow to power supply 132 while capacitor 130 charges and high current is present in network 104.

Therefore, as shown in FIG. 4, in order to solve the problem that the capacitor 130 cannot handle a large amount of current surge, the microbattery 106 and the resistor 108 are used.
Is added to the network. Cells 110, 112, 114,
More than one inverter is on for some time as 116, 118 transitions from one logic state to another. With the addition of the microbattery 106, the capacitor 130 does not remain uncharged but is charged from the microbattery 106, allowing the capacitor 130 to be ready to handle current surges that occur during the transition period. The resistor 108 serves to further limit the current drawn on the voltage line 132.

FIG. 5 shows cells 110, 11 of network 136.
2 shows a schematic diagram of a random access memory network 136 having a microbattery 138 and a resistor 140 associated with each of 2, 114, 116 and 118. Although the embodiment shown in FIG. 4 reduces switching noise, the speed of network 104 of FIG. 4 is limited by how fast each capacitor 130 charges. However, if the capacitor charges faster, more noise will be introduced into the network 104. The network shown in FIG. 5 has cells 110, 11
Local for each of 2, 114, 116 and 118 (loca
lized) Micro battery 138 source achieves increased speed and reduced noise. Moreover, the configuration of FIG. 5 allows for a reduction in the size of resistor 140.

Accordingly, the random access memory network 136 includes each cell 110, 112, 11 operating independently.
A microbattery 138 for each of 4, 116 and 118 is included. Microbattery 138 is typically smaller than microbattery 106 of FIG. The microbattery 138 provides the local energy to charge the capacitor 130, which causes the network 1
Increase the speed of 36. By placing the capacitor 130 closer to the power source, ie, closer to the microbattery 138, the capacitor 130 is charged faster. Because the time it takes to charge the capacitor is related to the resistance between the capacitor and the power supply. Further, if the capacitor 130 is placed closer to the power source or microbattery 138, the resistor 14
The size of 0 can be reduced, thereby increasing the overall speed of network 136.

More than one of cells 110, 112, 114, 116 and 118 are turned on for a period of time as cells 110, 112, 114, 116 and 118 transition from one logic state to another. It During this period, high currents are present, causing voltage spikes and consequently introducing noise to the network 136. In the specific example shown in FIG. 5, each cell 110, 112, 114, 11 is
Microbattery 13 connected to 6 and 118
Eliminate this noise by using 8. When high current is needed in the transition state, the current demand is met by microbattery 138.
The high current and the resulting voltage spikes are isolated from the power supply 132 by the use of a resistor 140 that limits the amount of current drawn. Thus, the network 136 of FIG. 5 provides increased speed while reducing or eliminating switching noise.

An advantage of the present invention is that adding a microbattery to an integrated circuit significantly reduces switching noise that occurs when switching between logic states that produce high currents that produce large voltage spikes. The microbattery supplies the current needed to eliminate the voltage spike.

Another advantage of the present invention is that the microbattery enables operation of high speed random access memory integrated circuits having multiple memory cells without introducing additional noise. By using locally located microbatteries in the integrated circuit, either alone or in combination with resistors, the devices can be charged at a faster rate and faster switching can occur.

Yet another advantage of the present invention is that by using a microbattery to reduce switching noise, it saves more energy with the microbattery using less area on the integrated circuit. This means that space on the circuit does not have to be used by this solution.

Yet another advantage of the present invention is the use of microbatteries instead of capacitors. Microbatteries typically store a relatively large amount of energy that is released slowly over a long period of time, while capacitors store a relatively large amount of energy available in short bursts, so the battery stores slowly. That is, the generated electric current can be discharged.

The foregoing is provided for purposes of illustrating, illustrating, and describing some embodiments of the present invention.
Modifications and adaptations to these embodiments will be apparent to those of ordinary skill in the art, eg, micro batteries and / or associated resistors have any high current requirements that result in voltage spikes and consequent transient noise. Can be used to reduce noise in semiconductor devices.
It will also be appreciated by those skilled in the art that the embodiments described in this document can be easily modified to modify the present invention in order to provide additional functions and new applications. It is not intended to limit the scope of the following claims in any way.

[Brief description of drawings]

FIG. 1 is an inverter for reducing switching noise in an integrated circuit, according to a first aspect of the present invention;
FIG. 6 is a circuit diagram of an integrated circuit including a microbattery and a resistor.

FIG. 2 is a schematic diagram of an integrated circuit including a bipolar transistor and a microbattery to reduce noise according to a second aspect of the present invention.

FIG. 3 is a schematic diagram of a bipolar RAM storage cell including two cross-coupled three-emitter transistors, a microbattery and a resistor to reduce switching noise according to a third aspect of the present invention. .

FIG. 4 is a schematic diagram of a random access memory network having a plurality of cells, a microbattery, and a resistor to reduce switching noise according to a fourth aspect of the present invention.

FIG. 5 has a plurality of cells having a microbattery and a resistor associated with each cell of the network to reduce switching noise in accordance with a fifth aspect of the present invention. FIG. 6 is a circuit diagram of a random access memory network.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Ronnie Gee Johnson             United States 30309 Georgia             Atlanta The Prado 201 F term (reference) 5B015 HH01 HH03 JJ12 KA13 QQ00                       QQ05 QQ10                 5F038 BB04 BH02 BH03 BH19 DF05                       DF12 EZ20

Claims (28)

[Claims] 1. A first transistor network in a first logic state, a second transistor network in a second logic state, and both the first transistor network and the second transistor network. A device for reducing noise in a mixed-mode integrated circuit including a connected microbattery, the device comprising: a transition between logic states of the first and second transistors; While both of the second transistor networks are on for some period of time, causing a current surge and a voltage spike, the current demand is met by the microbattery, which is distributed throughout the mixed-mode integrated circuit. Apparatus for reducing noise in a mixed mode integrated circuit, characterized in that it is gradually refilled to eliminate voltage spikes. 2. A first gate network further connected to the first transistor network, a second gate network further connected to the second transistor network, and achieving read and write operations. 2. The apparatus of claim 1 including an address line connected to said first and second gate networks to enable transitions of logic states of the first and second transistor networks. . 3. A resistor, one end of which is connected to the microbattery and the other end of which is connected to a voltage source, which isolates the power supply from the voltage spike and limits the amount of current drawn. 2. The container according to claim 2, further comprising a container.
The device according to. 4. The device of claim 1, wherein the first and second transistor networks comprise mosfet (MOSFET) random access memory cells. 5. The device of claim 2 wherein the microbattery further comprises a thin film battery. 6. The thin film battery further comprises an aluminum cathode collector, a cathode of a crystallized lithium interrupt compound deposited on the aluminum cathode collector having a cobalt coating, an anode,
The device of claim 5 including an electrolyte disposed between the lithium interrupt compound cathode and an anode, and an anode collector connected to the anode. 7. The thin film battery of claim 5, further comprising a battery cell substructure having a lithium-based cathode, an electrolyte, and a metal anode current collector alloyable with lithium. apparatus. 8. A cross-coupled flip-flop circuit comprising a first transistor group in a first logic state and a second transistor group in a second logic state static state, the cross-coupled flip-flop circuit including at least two transistor groups. Including a method for reducing switching noise of a semiconductor integrated circuit having analog and digital elements on the same substrate, including turning on a gate device and applying a voltage to a 1-bit line so that a cell of the integrated circuit can be read. A clock pulse that sends a pulse to an address line connected to each of the transistor groups, charges a microbattery connected to the transistor group at one end, and sends a pulse to the address line to a second transistor group. Grounding the 1-bit line associated with Logic state to the second logic state, causing the 0 bit line to transition from a low logic state to a ground state, thereby turning on the second transistor group and grounding the first transistor group to ground. To turn off the first group of transistors and to turn on both the first group of transistors and the second group of transistors for periods of high current and voltage spikes. A method comprising drawing current from a charged microbattery and limiting current flow by using a resistor having one end connected to the end of the battery and the other end connected to a voltage source. 9. A device for reducing noise in a mixed mode integrated circuit, comprising: a first transistor network in a first logic state; a second transistor network in a second logic state; A thin film battery connected to both one transistor network and the second transistor network, a first gate network connected to the first transistor network, connected to the second transistor network A second gate network connected to the first and second gate networks for activating read and write operations, thereby providing the first transistor network and the second transistor network. An address line that allows transitions of logic states, and one end connected to a thin film battery and the other end connected to a voltage source, isolating the voltage source and A resistor that limits the current drawn from the battery of the film, the logic state of the first and second transistors transitioning to turn on both the first and second transistor networks. The current demand is met by the thin film battery that is gradually charged during the current surge and voltage spike, while eliminating the voltage spike that occurs across the mixed mode integrated circuit. Characterized device. 10. The thin film battery further comprises an aluminum cathode collector, a cathode of crystallized lithium interrupt compound deposited on the aluminum cathode collector having a cobalt coating, an anode, a cathode and an anode of the lithium interrupt compound. 10. The device of claim 9 including an electrolyte disposed between and an anode collector connected to the anode. 11. The thin film battery of claim 9, further comprising a battery cell substructure having a lithium-based cathode, an electrolyte, and a metal anode current collector alloyable with lithium. apparatus. 12. A first bipolar transistor, a second bipolar transistor connected to the first bipolar transistor, and whether the microbattery associated with each bipolar transistor is charged or uncharged. A microbattery connected to the first bipolar transistor and the second bipolar transistor for determining whether the first bipolar transistor or the second bipolar transistor is operating based on A memory cell consisting of. 13. An integrated circuit including at least one bipolar random access memory (RAM) storage cell for reducing noise in a mixed mode circuit, the integrated circuit including a read or write logic value. At least two cross-coupled three emitter transistors having emitters, one of the transmitters in a first logic state and the other of the transmitters in a second logic state.
ransistor), an address line connected to the remaining two emitters of each transistor to select an individual cell, to activate the transition of each transistor from its current logic state to another Voltage source, a microbattery connected between the transmitter and the voltage source to absorb and gradually recharge the current surge, and the voltage source and the microbattery to isolate the current surge from the transistor. An integrated circuit including a connected resistor. 14. The integrated circuit of claim 13, wherein the microbattery further comprises a thin film battery. 15. The integrated circuit of claim 13, wherein the microbattery includes a battery cell substructure having a lithium-based cathode, an electrolyte, and a metal anode current collector alloyable with lithium. 16. The thin film battery is further disposed on a cathode collector, a cathode of crystallized lithium interrupt compound deposited on the cathode collector, an anode, and between the cathode of the lithium interrupt compound and the anode. 15. The integrated circuit of claim 14 including an electrolyte and an anode collector connected to the anode. 17. A first inverter in a first logic state connected to a first node; in a second logic state converted to a second node to a first inverter; A cross connected second inverter, a microbattery at the first end connected between the first and second inverters to charge to a power supply voltage, a microbattery at one end A resistor having a second end connected to a voltage source and the other end connected to a voltage source, a gate network connected to the first inverter and the second inverter, and activating a gate device. An address line connected to each gate network to receive a clock pulse for, and a current from the gate device when the gate device is activated , A bit line connected to each gate device, one of the bit lines serving as one bit line associated with the first inverter and another bit line associated with the second inverter A flip-flop circuit including the bit line acting as a 0 bit line, the first inverter transitioning to a second logic state and the second inverter being the first with a high current demand. The microbattery supplies its current required during the transition period when a pulse is sent to each address line to change the logic state of the first and second inverters as a transition to a logic state of And a flip-flop circuit that limits the amount of current drawn by the resistor. 18. The circuit of claim 17, wherein the microbattery further comprises a battery cell substructure having a lithium-based cathode, an electrolyte, and a metal anode current collector alloyable with lithium. . 19. A device for reducing noise in a mixed mode integrated circuit including at least one inverter having at least one logic state, the device surged during a logic state transition. A source of current emitted from the inverter, a microbattery connected to the inverter and adapted to absorb the source of current, and connected to the microbattery and power supply to limit the current drawn from the microbattery. A resistor, including a resistor. 20. A random access memory network having a plurality of memory cells having an inverter adapted to transition from a first logic state to a second logic state, each cell comprising: A capacitor connected to the cell and a circuit including a microbattery and a resistor connected between the cell and a voltage source, during a transition from one logic state to another. The microbattery charges the capacitor thereby charging it when more than one inverter is turned on to produce a high current and a voltage spike as a result of the potential, during the transition period. A random access memory network capable of absorbing the surge of current that occurs. 21. The network of claim 20, wherein the capacitor has a capacitance of 125 picofarads. 22. The circuitry defined in claim 20 wherein the microbattery further comprises a thin film battery. 23. The circuit of claim 20, wherein the microbattery further comprises a battery cell substructure having a lithium-based cathode, an electrolyte, and a metal anode current collector alloyable with lithium. network. 24. During the transition from one logic state to another, more than one inverter is turned on to produce high currents and voltage spikes as a result of the potential, while each capacitor is turned on. A microbattery and a resistor are connected to each cell to receive charge from the microbattery associated with the cell and dissipate high currents, thereby increasing the speed of the network and reducing switching noise. 21. The circuit network according to claim 20. 25. A semiconductor integrated circuit formed by integrating at least two functional circuit blocks on a semiconductor chip, wherein a power supply line for supplying a first power supply to the semiconductor chip, layers and layers. An ion-conducting material is included between two conductive layers formed on the insulating film between, and a capacitive device connected to the power line and a time constant of resistance value Multiplying the capacitance value of the capacitive device has a resistance value selected such that the amount of charge discharged from the capacitive device is within a range that can be recharged and recovered, and the power supply A semiconductor integrated circuit including a resistive device connected to a line. 26. A wiring resistor from the point of supply of the power source to the line connecting to the capacitive device, the resistive device having the selected resistance value, conductive impurities. A resistor made of a conductive material mainly made of silicon having a resistance value adjusted by selecting the concentration of the power source, and a power source having a wiring resistance higher than that of the power line. 26. The circuit of claim 25 selected from the group consisting of resistors made of the same material as described above. 27. Several resistive devices comprise one resistive device for each of the capacitive devices, one resistive device for at least two capacitive devices, one resistive device for all capacitive devices. 27. The circuit of claim 26 selected from the group. 28. One of the two conductive layers of the capacitive device is a cathode material and another layer of the two conductive layers is an anode material, whereby a cathode material, an ionic conductive material, and 28. The circuit of claim 27, wherein the anode material comprises an energy storage cell.