KR20030084086A - Systems and methods for reducing noise in mixed-mode integrated circuits - Google Patents

Abstract

Systems and methods for reducing switching noise comprising an inverter network having at least two transistors, a micro battery such as a thin film battery coupled to the inverter network, and a resistor one end connected to the micro battery and the other end to a power source. This is presented. When a transistor transitions from one logic state to another, one transistor is turned on for a predetermined time. Unless control is applied, this state creates a high amount of current and the resulting voltage spikes. The current required during this transition period is provided from the micro-battery to prevent peak voltage flow to the analog devices and thereby destroy them. The battery is gradually recharged, so no voltage spikes are generated. In addition, integrated circuit elements are isolated from the power supply by a resistor that limits the current drawn from the power supply.

Description

SYSTEM AND METHOD FOR NOISE REDUCTION IN MIXED-MODE INTEGRATED CIRCUITS {SYSTEMS AND METHODS FOR REDUCING NOISE IN MIXED-MODE INTEGRATED CIRCUITS

TECHNICAL FIELD The present invention generally relates to semiconductor integrated circuits, and more particularly to systems and methods for noise reduction in mixed-mode integrated circuits.

In the present environment, semiconductors include both analog and digital components and are generally considered mixed signal or mixed-mode integrated circuits (ICs). Integrating analog and digital components on the same chip reduces cost, area, and power requirements, which are important considerations in the production of ICs. However, combining analog and digital components on the same substrate introduces design challenges. Primarily, switching noise in high speed digital circuits easily interferes with and damages high frequency analog circuits. In general, digital circuits quickly position between preset voltage levels, resulting in transient noise on the power lines. Analog circuits operating at various voltage levels and frequencies are sensitive to induced noise while the digital circuits are resistant to interference from induced noise.

Integrated circuits include many high performance devices that are sensitive to noise. Rapid buildups and noncharges in the circuit cause a voltage drop. This transient voltage is large enough to affect the performance of these sensitive devices.

Substrate noise can affect many applications. For example, substrate noise is problematic for phase-locked loop systems (PLLs) and inverters. PLLs are used in many applications including data recovery in disk drives, wired and wireless communications, high speed microprocessors and memories.

Inverters (also referred to as flip-flops) are also widely used. Flip-flops provide an important function for reading and writing bits of words in memory devices. In general, flip-flops include fast switching circuits that address (need to define a flip-flop) addressing for writing and reading on the flip-flop.

In steady-state or quiescent conditions where no switching occurs between output states, no current flows from the garden to the flip-flop. Typically, the flip-flop includes a network of transistors connected to a power source and ground. In the steady-state, one transistor (or group of transistors) is turned on and the other transistor (or group of transistors) is turned off. In order to switch from one transistor to another, the power supply switches from one state to another, for example, by switching from low to high potential to flow current. When one transistor is turned off and the other transistor is turned on, for a period of time, two transistors are turned on. High current is provided to the network during the period. The high current causes voltage spikes that induce noise during the switching process. As current flows through the wires of the network, the voltage begins to drop as it encounters resistors, which becomes a transient voltage across the IC. Such transient voltages may propagate along a power source connected to the integrated circuit from a printed circuit board on which the integrated circuit board is loaded. The transient voltage produces radio frequency (RF) radiation that affects the proper operation of other circuits on the printed circuit board and other circuits within the integrated circuit itself.

Many prior attempts have been proposed to solve switching noise problems. Some proposed solutions have focused on controlling the current surge. U.S. Patent No. 5,905,389, filed on May 18, 1999, entitled "CMOS Integrated Circuit Regulator for Reducing Supply Noise" is an auxiliary metal-oxide-semiconductor (CMOS) for providing a fixed current to a set of logic gates during a switching transition. ) Includes a regulator. The configuration provides current to the supply rails separately from the external power source sharing with the analog circuits. The current is kept substantially constant by the clamping operation of the clamping transistors. The excess charge for the transients is supplied by the capacitor, which recharges during the time of no switching.

Another attempt to solve the noise problem involves the addition of decoupling capacitors disposed adjacent to the active devices. The decoupling capacitors stabilize the current flow for the devices. However, spy still occurs while the capacitor absorbs part of the voltage.

Another attempt to solve substrate noise problems involves an active method using linear feedback loops. The approach includes sampling noise at the analog receiver portion of the noise and passing the noise to an input stage of a negative feedback loop. After being amplified in reverse phase, the noise is reapplied to the substrate. The re-applied noise, having a reverse phase with respect to the original noise moving inside the substrate, dissipates the original noise by up to 83%. The solution is applied to mixed-mode integrated circuits operating in low voltage portable electronics with low frequencies and low digital clock speeds.

Another attempt to manage switching noise is to separate analog and digital functions. The treatment requires unique production processes and user designs. For example, US Pat. No. 6,020,614, filed Jan. 1, 2000, describes a method for reducing substrate noise coupling in a mixed signal integrated circuit that has an analog circuit having a power bus separate from the digital circuit, and the analog of a semiconductor substrate. It is proposed that setting the boundary zones between the and digital circuits can reduce the noise. The patent also describes the provision of interconnecting signal lines, wherein isolated wires between the circuits can functionally interact with other circuits while the substrate noise coupled from the other circuits is at low potential. However, separating analog components from the digital components wastes valuable semiconductor space, which is an important consideration in integrated circuit design.

Another attempt to eliminate switching noise is described in US Pat. No. 5,649,160, "Noise Reduction of Integrated Circuits and Circuit Assemblies," filed July 15,1997. The patent suggests that it can be reduced by shaping noise from digital circuitry and focusing it on fractional portions of the signal or frequency spectrum. The solution relies on the notion that the presence of noise in analog circuits is less important at certain frequencies, and hence there is little interference by carefully placing spectral peaks or peaks from the digital circuit.

Each of the various conventional attempts to solve the switching noise problems have limitations. Accordingly, what is needed is a system and method that substantially reduces the switching noise of mixed-mode integrated circuits.

It is an object of the present invention to include a micro battery on an integrated circuit to overcome the switching noise related problems encountered by integrated circuits with analog and digital components. Noise is generated in integrated circuits through several circumstances. Among other things, certain integrated circuits, such as inverters, transition from one logic state to another. For example, inverter A must be turned on and inverter B must be turned off. During the transition, both transistors are turned on for a predetermined time period and the transition is complete. In this example, there is a high current that results in spikes in the voltage and induce noise.

An integrated circuit configured to reduce switching noise includes an inverter network having at least two transistors, a gating network connected to the inverter network, a micro battery connected to the inverter, and one end connected to the micro battery. The other end includes a resistor connected to the power supply. In the normal state, the micro battery is uncharged. Once charged, a slight current flows through the micro battery. When the inverter transitions and a current surge occurs that causes a voltage spike, the current requiring a voltage drop is provided by the micro battery. Thus, the integrated circuit can avoid peak voltage flow into the analog components and collapse of the analog components. In addition, the battery is gradually recharged so that no voltage spike occurs. In addition, the components of the integrated circuit are isolated from the power line, ie V _DD . Alternatively, the inverter may include a bipolar RAM storage including three cross coupled three emitter transistors.

In another embodiment of the invention, switching noise is reduced in unswitched integrated circuits. The embodiment includes a plurality of transistors having one group of transistors in an on logic state and another group of transistors in an off logic state. Micro batteries are connected to each group of transistors. Awareness of the state of the transistors is determined by whether the associated micro battery is charged or uncharged. For writing to the cell, the associated micro battery is charged and the corresponding transistor is turned on.

Another alternative embodiment of the present invention for reducing switching noise includes a random access memory network having a micro battery and a resistor to reduce switching noise. The random access memory network includes a plurality of cells. The cells include inverter circuits. The addition of the micro battery is provided for the capacitor 130 that is charged from the micro battery. The capacitor can thus handle current surges that cause voltage spikes on the power lines. The resistance further limits the current flow to the voltage line.

Another alternative embodiment of the present invention includes a random access memory network having a micro battery and resistance circuits associated with each cell of the network, wherein each micro battery and the resistance circuit operate independently. Localized micro battery sources for each cell increase the speed of the network while reducing switching noise and resistance magnitudes.

The present invention is achieved by combinations of at least one or more of the following objects.

Reducing the switching noise of a mixed-mode integrated circuit provides systems and methods that prevent components of the integrated circuit from being damaged by transient noise.

Systems and methods are provided for reducing switching noise in integrated circuits using microbatteries to provide current to the integrated circuit as the current increases during the transition from one logic state to another.

Systems and methods for using a micro battery in an integrated circuit to indicate whether associated transistors are turned on or turned off.

Provided are systems and methods for reducing switching noise in micro-battery integrated circuits that efficiently use semiconductor space.

Other objects, advantages and features of the present systems and methods are listed in the following detailed description, will be apparent from the description, or may be learned by practice of the invention. The above objects, advantages and features of the invention may be realized and attained by means and combinations of components particularly pointed out in the claims.

1 is a schematic diagram of an integrated circuit including inverters, a micro battery and a resistor to reduce switching noise in an integrated circuit according to a first embodiment of the present invention.

2 is a schematic diagram of an integrated circuit including bipolar transistors and micro batteries to reduce noise in accordance with a second embodiment of the present invention.

3 is a schematic diagram of a bipolar RAM storage cell including two cross coupled three-emitter transistors, a micro battery and resistors to reduce switching noise in accordance with a third embodiment of the present invention.

4 is a schematic diagram of a random access memory network having a plurality of cells, a micro battery and a resistor to reduce switching noise in accordance with a fourth embodiment of the present invention.

5 is a schematic diagram of a random access memory network having a plurality of cells with microbatteries and a resistor coupled to each cell of the network to reduce switching noise in accordance with a fifth embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. 1-5 depict various aspects for protecting devices of an integrated circuit from noise.

1 is a schematic diagram of a single MOS-RAM cell 10 for use in a mixed-mode integrated circuit, in which the single MOS-RAM cell 10 is a cross-coupled transistor coupled at nodes 22 and 24. An inverter circuit 12 comprising 14, 16, 18 and 20, and a gating network of transistors 26, 28, 30 and 32 coupled to the inverter circuit 12. The micro battery 34 is coupled to the inverter circuit 12 at node 36. The resistor 38 is coupled to the micro battery 34 at one end 40 and to the power supply 42, ie V _DD at the other end. For illustrative purposes, FIG. 1 shows a single cell 10, but the invention is not limited to this single cell 10. The inverter circuit 12 is used to read the binary information in the cell 10 and to record the binary information in the cell 10.

Transistors 26 and 28 forming the first gating network are coupled to the 1-bit line 46. Transistors 30 and 32 forming the second gate network are coupled to a 0-bit line 48. The bit lines 46 and 48 provide a method for determining the state of the storage cell when the 1-bit line 46 or the 0-bit line 48 has current flowing through it.

The address lines 44 and 46 are used for reading and writing the storage cells of the inverter circuit 12. To perform a read or write operation, address lines 44 and 46 are excited by a clock pulse (not shown). A clock pulse usually contains a stream of square waves that represent voltages such as a high value of 0V and a low value of -10V (or -V _DD ).

In the steady state, the address lines 44, 46 have a ground potential. In this state, one transistor 18 is on and one transistor 14 is off. For example, when transistor 18 is on and transistor 14 is off, the voltage at node 24 is low, such as -V _DD , and the voltage at node 22 is high, such as 0V. do. To read the data in the cell, the address lines 44, 46 are pulsed by a clock pulse. Current flows through the gating devices 26 and 28 and the transistor 18 to the 1-bit line 46. Since transistor 14 is off, little current flows through 0-bit line 48, which is also a low voltage (i.e., -V _DD ).

To write data in the cell, the address lines 44, 46 are pulsed again by a clock pulse and the 1-bit line 46 is grounded. Grounding zero-bit line 48 pulls node 22 to ground, turning off transistor 18 and turning on transistor 14, which causes inverter circuit 12 to have a different logic in one logic state. This is because the transition to the state.

However, when the inverter circuit 12 transitions from the logic one state to another logic state for a while, the transistors 18 and 14 are turned on for a short period of time. During this transition period, a large amount of current is surged through the system 10. This current surge causes a corresponding voltage spike. If uncontrolled, this voltage spike causes noise to enter a number of devices, such as analog devices, power buses, integrated circuit structures, power lines or silicon substrates. Current is required to reduce voltage spikes.

As described above, the micro battery is discharged. However, when the inverter circuit 12 changes the logic state, i.e. flips it, and a current surge occurs, the resulting peak voltage flows into the elements, including analog elements, instead of turning them off. Absorbed by the battery 34. The micro battery 34 is gradually charged so that no voltage spike occurs. When a current is needed to reduce the high voltage, current is drawn from the micro battery 34, and transistors and other elements are connected to the power line 44 by a resistor 38 that limits the current induced on the line 44. That is, separate from the source V _DD . The size of the resistor 38 can vary and depends on the size of the micro battery 34 used in the system 10.

Suitable micro-batteries 34 for use in the present invention include: Excelltron Solit State LLP, Roswell Street, 1640, GA, Smyrna, GA. Is a thin film battery available from. Acceltron has a proprietary and licensed thin film battery technology, including the microbatteries disclosed in US Pat. Nos. 5,569,520 and 5,597,660, which are incorporated herein by reference. Applicant's patent application No. 09 / 286,112, filed April 2, 1999, entitled "Thin Lithium Film Battery," and filed on April 5, 2000, entitled "Method for Manufacturing Thin Film Battery." Patent Application No. 09 // 543,121, filed March 28, 2000, and filed Patent Application No. 09 / 536,594, entitled "Thin Film Battery Manufacturing Method," and filed on April 5, 2000, entitled "Thin Film. See patent application 09 / 543,280, which is a method of manufacturing a battery anode, and patent application 09 / 536,535, filed March 28, 2000, which is entitled "Method of manufacturing a thin film battery with a protective packaging." It is cited as. In general, thin film batteries include a stack configuration of films starting with a cathode current collector and a cathode mounted inert ceramic or aluminum substrate. A solid electrolyte is deposited on the cathode, the anode is deposited on the electrolyte in turn, and an anode current collector is mounted on the anode. Typically, the entire cell is provided with a protective coating. Preferably, the thin film battery is rechargeable.

2 is a schematic diagram of bipolar transistors 52, 54, gating devices 56, 58, micro batteries 60, 62 and address lines 64, 66 according to a second embodiment of the present invention. 50). Gating devices 56 and 58 include bipolar transistors, each bipolar transistor coupled to lines 68 and 70. Gating device 58 is coupled to one bit line 68, and gating device 56 is coupled to zero bit line 70.

In the initial state, one bipolar transistor 52 is on and the other bipolar transistor 54 is off. The state of the transistors 52, 54 can be determined by examining which micro battery 60, 62 is charged. In the charged state, one bit line 68 goes low to turn transistor 52 on. To change the logic state of the transistors 52, 54, the address lines 64, 66 are pulsed low to high by a clock pulse (not shown), ie from -V _DD to 0V. Charging the micro batteries 60, 62 enables writing to the transistors 52, 54 and transitioning the logic state of the transistors 52, 54. During the transition, micro batteries 60, 62 provide current when removal of voltage spikes that may cause system noise is required.

3 illustrates a bipolar RAM storage cell comprising two cross-coupled three-emitter transistors 74, 76, a micro battery 78 and resistors 80, 82, and 84 to reduce switching noise. 72 is a schematic diagram. One emitter 86 of transistor 74 functions to sense or write logic 1 when transistor 74 is energized. One emitter 88 of transistor 76 functions to read or write a logic zero when transistor 76 is energized. Emitter 90 of transistor 76 and emitter 92 of transistor 74 are connected to address line X 94. Emitter 96 of transistor 76 and emitter 98 of transistor 74 are connected to address line Y 100. Typically, address lines 94, 100 remain low, i.e., zero, and current from all conductive transistors flows from these address lines 94,100.

If the bipolar RAM storage cell 72 is one of a plurality of cells in the matrix array, then the address lines 94 and 100 are logical 1 to address the individual cell 72. The remaining cells in the unaddressed matrix array have at least one their respective address line in logic 0 such that no change occurs in these cells. In cell 72, current from the conducted transistor flows from the address lines to the read line and then to one of the read amplifiers (not shown).

To write cell 72, cell 72 is addressed as described above. Logic 1 applied to write emitter input 86 drops the output of transistor 74 to logic 0. The logic zero voltage on the output of the write emitter 86 applies the same low voltage to all emitters of the cell 72. If cell 72 is in the desired state, no change occurs. If cell 72 is not in the desired state, a low voltage applied to emitter 86 of transistor 76 that is off may turn transistor 76 on and turn off transistor 74.

When transistor 76 is turned on and transistor 74 is turned off, both transistors 74 and 76 will be turned on for a certain period of time. During this time period, there is a high current causing a voltage surge. In order to avoid such voltage surges that cause noise to pass into the system, microbatteries 78 have been applied to the network. Micro battery 78 operates like a capacitor and supplies a transition current. Thus, when the voltage surges and a current is required to reduce the voltage, the current is provided from the micro battery 78. Resistor 80 isolates power supply line 102 from other devices and limits the amount of current provided from line 102. Once discharged, the micro battery 78 gradually recharges to be free of any voltage spikes.

4 shows a schematic diagram of a random access memory network 104 having a micro battery 106 and a resistor 108 to reduce switching noise. Random access memory network 104 includes multiple cells 110, 112, 114, 116 and 118 (only five cells are shown for illustrative purposes). These cells 110, 112, 114, 116 and 118 include an inverter circuit such as the inverter circuits shown in FIGS. 1 and 3, and the transistor configuration shown in FIG. 2.

Each cell 110, 112, 114, 116 and 118 has input / output leads for X-Y addressing 120, 122 and read / write functions 124, 126. Read lines 124 enable the detection of digital information stored in each cell 110, 112, 114, 116 and 118. Read lines 126 allow digital information to be stored in the selected cell. Decoder 128 decodes the addressing information and selects the selected individual address cells to receive write or read transactions. Each cell 110, 112, 114, 116, and 118 is a capacitor 130, such as upon transition from an on / off logic state, or vice versa, that is, on a read / write or write / read transition. , 112, 114, 116 and 118, 125 microfarad capacitors that serve to draw some current. However, capacitor 130 stores current until fully charged. However, since capacitor 130 is not instantaneously charged while logic states are transitioning when a large amount of current is present, the capacitor is slowly charged until it is charged, thus preventing processing of a large current surge. During this period, a high current is present. Thus, current is surged through the network 104. While the capacitor 130 is charged and there is a high current in the network 104, voltage spikes can flow to the power supply line 132.

Thus, as shown in FIG. 4, the micro battery 106 and the resistor 108 are added to the network to address the inability of the capacitor 130 to regulate large current surges. One or more inverters are turned on for a period of time while the cells 110, 112, 114, 116, and 118 transition from one logic state to another. Due to the addition of the micro battery 106, instead of being discharged while allowing the capacitor 130 to adjust the current surge occurring during the transition period, the capacitor 130 is not used to store the micro battery 106. Is charged from. The resistor 108 acts to limit the current generated in the power line 132.

5 illustrates a random access memory having a micro battery 138 and a resistor 140 circuit associated with each cell 110, 112, 114, 116, 118 of the network 136. It is a schematic diagram of the network 136. The embodiment shown in FIG. 4 reduces switching noise, and the speed of the network 104 of FIG. 4 is limited by the rate at which each capacitor 130 is charged. However, if the capacitor is charged faster, more noise is induced in the network 104. The network shown in FIG. 5 can increase its speed and reduce noise due to the local micro battery 138 source for each cell 110, 112, 114, 116, 118. . In addition, the configuration of FIG. 5 may reduce the size of the resistor 140.

Accordingly, the random access memory network 136 has a micro battery 138 for each cell 110, 112, 114, 116, 118 operating independently. The micro battery 138 is generally smaller than the micro battery 106 of FIG. 4. The micro battery 138 provides local energy for charging the capacitor 130 to increase the speed of the network 136. By placing the capacitor 130 closer to the power source, i.e., closer to the micro battery 138, the capacitor 130 is more likely because the time it takes to charge the capacitor is related to the resistance component between the capacitor and the power source. It charges quickly. Also, if the capacitor 130 is located closer to the power source, ie closer to the micro battery 138, the size of the resistor 140 is reduced, thereby increasing the overall speed of the network 136.

When cells 110, 112, 114, 116, 118 transition from one logic state to another, one or more cells 110, 112, 114, 116, 118 are turned on for a one hour period. During this period, there is a high current that results in voltage spikes and the resulting induction of noise into the network. The embodiment shown in FIG. 5 removes this noise due to the use of the micro battery 138 connected to each cell 110, 112, 114, 116, 118. When a high current is required in the transition state, the current demand is satisfied by the micro battery 138. High current and subsequent voltage spikes are separated from the power line 132 by the use of the resistor 140 to limit the amount of current that occurs. Thus, the network 136 of FIG. 5 provides increased speed while reducing or eliminating switching noise.

An advantage of the present invention is that it significantly reduces the switching noise that occurs during switching between logic states that produce high currents resulting in large voltage spikes due to the addition of micro batteries to the integrated circuit. The micro battery supplies the current required to disperse the voltage spike.

Another advantage of the present invention is that the micro battery enables the operation of a high speed random access memory integrated circuit having a plurality of memory cells without causing additional noise. By using local micro-batteries, alone or in combination with resistors in the integrated circuit, components can be charged at a higher rate and high speed switching is possible.

Another advantage of the present invention is that by using micro batteries to reduce switching noise, the micro batteries store more energy using less area on the integrated circuit, so that expensive space on the integrated circuit is used in this way. It is not to lose.

Another advantage of the present invention is the use of micro batteries instead of capacitors. Micro-batteries generally store a relatively large amount of energy that is slowly released over a long period of time, while capacitors store a relatively large amount of energy that can be used for a short period of time, so that batteries can slowly release the stored current. have.

A number of embodiments of the invention, their description and the purpose thereof have been disclosed above. Modifications and variations of these embodiments will be apparent to those skilled in the art, and will not depart from the scope or spirit of the invention and the claims that follow. For example, micro batteries and / or associated resistors can be used to reduce noise in any semiconductor device with high current demands that cause voltage spikes and subsequent transition noise. Also, those skilled in the art will recognize that the present invention can be readily modified for use with additional functions and new applications, and therefore the embodiments disclosed in this application do not limit the scope of the following claims.

Accordingly, the above configuration and process of the present invention cause problems that cause the peak voltage to enter the devices and destroy them due to the high amount of current and the resulting voltage spikes that occur when the transistor transitions from one logic state to another. Can be solved.

Claims (28)

A system for reducing noise in mixed-mode integrated circuits, A first transistor network in a first logic state; A second transistor network in a second logic state; And A micro battery connected to the first transistor network and the second transistor network, Voltage spikes flowing through the mixed-mode integrated circuit during the transition of logic states by the first and second transistors, and during a current surge while the first and second transition networks are on to cause a voltage spike. A system for reducing noise in a mixed-mode integrated circuit, characterized in that the current requirement is met by a slowly recharging micro battery that eliminates The method of claim 1, A first gate network coupled to the first transistor network; A second gate network coupled to the second transistor network; And A mixed-mode integrated circuit coupled to the first and second gate networks, the address lines causing the logic states of the first and second transistor networks to transition by activating read and write operations. System to reduce noise in the The method of claim 2, The system further comprises a resistor, one end of which is connected to the micro battery, the other end of which is connected to a voltage source, the resistance separating the voltage source from the voltage spike and limiting the amount of generated current. A system for reducing noise in mode integrated circuits. The method of claim 1, And said first and second transistor networks are comprised of MOSFET random access memory cells. The method of claim 2, And the microbattery further comprises a thin film battery. The method of claim 5, The thin film battery further includes an aluminum cathode collector and a crystalline lithium intercalation composite cathode deposited on the aluminum cathode collector, The aluminum cathode collector includes a cobalt coating, an anode, an electrolyte deposited between the lithium intercalating composite cathode and the anode, and an anode collector connected to the anode to reduce noise in a mixed-mode integrated circuit. system. The method of claim 5, The thin film battery further includes a battery cell structure, The battery cell structure includes a lithium-based cathode, an electrolyte, and a metal anode current collector that can be mixed with lithium. A method for reducing switching noise in a semiconductor integrated circuit, The semiconductor integrated circuit includes a cross coupled flip-flop circuit having a first group of transistors in a first logic state and at least two groups of transistors in a dormant state comprising a second group of transistors in a second logic state. And analog and digital components on the same substrate, the method comprising: Generating clock pulses at each of the address lines connected to each of the transistors in the group, turning on gate devices and flowing a voltage to one bit line to allow one cell of the integrated circuit to be read; Charging a micro battery connected to one end of said group of transistors; A pulse is applied to the address lines, with a zero bit line transitioning from a low logic state to ground, to turn off the first transistors by turning on the second group of transistors and grounding the first group of transistors. Transitioning said first group of transistors from said first logic state to a second logic state by generating and grounding said one bit line associated with a second group of transistors; Causing the first group of transistors and the second group of transistors to be on, and while a high voltage is present, causing a voltage spike to draw current from the charged micro battery; Limiting the flow of current using a resistor connected at one end to one end of the battery and at the other end to the voltage source. In a system for reducing noise in a mixed-mode integrated circuit, the system comprises: A first transistor network in a first logic state; A second transistor network in a second logic state; A thin film battery connected to both the first and second transistor networks; A first gate network coupled to the first transistor network; A second gate network coupled to the second transistor network; And Address lines coupled to the first and second gate networks to enable logic states of the first and second transistor networks to transition by activating read and write operations; And One end of which is connected to the thin film battery, the other end of which has a resistor connected to a voltage source, The resistor separates the voltage source from the voltage spike and limits the amount of current generated from the thin film battery, during the transition of logic states by the first and second transistors, and the first and second transition breaks. During a current surge while on, causing a voltage spike, the current demand is met by a slowly recharging thin film battery that eliminates voltage spikes flowing through the mixed-mode integrated circuit. Reducing system. The method of claim 9, The thin film battery includes an aluminum cathode collector, a crystalline lithium intercalated composite cathode deposited on the aluminum cathode collector having a cobalt coating, an anode, an electrolyte deposited between the lithium intercalated composite cathode and the anode, and an anode collector coupled to the anode. And further comprising reducing noise in a mixed-mode integrated circuit. The method of claim 9, The thin film battery further comprises a battery cell substructure having a lithium based cathode, an electrolyte and a metal anode current collector that can be alloyed with lithium. A first bipolar transistor; A second bipolar transistor coupled to a second bipolar transistor on the first bipolar transistor; A micro battery coupled to the first and the bipolar transistors to determine whether to operate the first bipolar transistor or the second bipolar transistor based on charging or non-charging of the micro battery associated with each bipolar transistor. Characterized by memory cells An integrated circuit comprising at least one bipolar random access memory (RAM) storage cell to reduce noise in a mixed mode circuit, the method comprising: At least two cross-connected three emitter transistors having one emitter configured to sense read and write logic values, wherein one of the transistors is in a first logic state and the other is in a second logic state; An address line connected to the remaining two emitters of each transistor to select individual cells; A power supply for operating a transition of each transistor from its current logic state to another logic state; A micro battery coupled between the transistors and a power source to absorb current surges and gradually recharge; And, And a resistor coupled to the power supply, the resistor isolating current surges from the transistors. The method of claim 13, The micro battery is a thin film battery. The method of claim 13, And the micro battery further comprises a battery cell substructure having a lithium based cathode, an electrolyte, and a metal anode current collector that can be alloyed with lithium. The method of claim 14, The thin film battery further comprises a cathode collector, a crystalline lithium intercalating composite cathode deposited on the cathode collector, an anode, an electrolyte deposited between the lithium intercalating composite cathode and the anode, and an anode collector coupled to the anode. Integrated circuit. As a flip-flop circuit, A first inverter coupled to the first node in a first logic state; A second inverter coupled to a second mode and cross coupled with the first inverter and in a second logic state; A micro battery having a first end coupled between the first inverter and the second inverter to supply charge to the source voltage; A resistor having one end connected to a second end of the micro battery and the other end connected to a power source; A gating network coupled to the first and second inverters; An address line coupled to each gating network to receive a clock pulse for operating the gating network; And, Connected to each gating device, including bitlines that receive current from the gating device in operation, Some of the bit lines serve as one bit line associated with the first inverter, and other bit lines serve as zero bit lines associated with the second inverter, A pulse is applied to each address line to change the logic states of the first and second inverters so that the first inverter transitions to the second logic state with a high current demand and the second inverter is in the first logic state. When transitioning to the micro-battery, the micro-battery supplies the current required during the transition period and the resistance limits the amount of current induced. The method of claim 17, And the micro battery further comprises a battery cell substructure having a lithium based cathode, an electrolyte, and a metal anode current collector that can be alloyed with lithium. A system for reducing noise in a mixed mode integrated circuit having at least one inverter having at least one logic state, the system comprising: A current source from the inverter that is surged during the transition of the logic state; A micro battery coupled to the inverter and adapted to absorb the current source; And A resistor coupled to the microbattery and to a power source, the resistor limiting a current drawn from the microbattery. A random access memory comprising a plurality of memory cells having an inverter configured to transition from a first logic state to a second logic state, A capacitor coupled to each cell; And A circuit comprising a micro battery and a resistor coupled between the cells and a voltage source, During the transition period from one logic state to another when one or more inverters are turned on to generate voltage spikes due to high currents and potentials, the micro-battery charges the capacitors to charge the capacitors during the transition period. Random access memory network, characterized in that to absorb the generated current surge. The method of claim 20, And said capacitor has a capacity of 125 picofarads. The method of claim 20, The micro-battery further comprises a thin film battery. The method of claim 20, And the micro battery further comprises a battery cell substructure having a lithium based cathode, an electrolyte, and a metal anode current collector that can be alloyed with lithium. The method of claim 20, The capacitors are coupled to each of the cells such that each capacitor is turned on during a transition period from one logic state to another when one or more inverters are turned on to produce voltage spikes due to high current and potential. Random access memory network that is charged from the micro battery associated with a cell and dissipates a high current to increase the speed of the network and reduce switching noise. A semiconductor integrated circuit formed by integrating at least two functional circuit blocks on a semiconductor chip. A power supply for supplying a first power supply to the semiconductor chip; Capacitive devices comprising an ion conductive material between two electrically conductive layers formed on the interlayer insulating film and connected to the power source; And A time constant multiplied by the capacitance value of the capacitive devices and the resistance value has the resistance value selected to be within a range in which the amount of charge discharged from the capacitive devices can be recharged and recovered, and includes a resistive device coupled to the power source. A semiconductor integrated circuit, characterized in that. The method of claim 25, The resistance value is Wire resistance from an application point of the power supply line to a line connecting the capacitive devices; A resistance of the electrically conductive material, mainly made of silicon, in which the resistance value is adjusted by selecting a concentration of the electroconductive impurity; And And a resistor made of the same material surrounding the power supply line having a higher wire resistance than the wire resistance of the power supply line. The method of claim 26, The number of resistive devices One resistive device for each of the capacitive devices; One resistive device for at least two capacitive devices; And from the group consisting of one resistive device for all capacitive devices. The method of claim 27, One of the two electrically conductive layers of the capacitive devices is a cathode material, and the other of the two electrically conductive layers is an anode material, wherein the ion conductive material and the anode material constitute an energy storage cell Semiconductor integrated circuit.