JP2003315426A - Input-pattern feeder and inspection method for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the time required for observing a waveform and to suppress the failure analytical time. <P>SOLUTION: When an internal circuit waveform of a semiconductor device is observed, a reset circuit 19 used to output a reset signal 21 for setting a pseudorandom pattern generator 12 to an initial value is added to the pattern generator 12 so as to correspond to a specific output, a cycle of a random pattern to be output is shortened, the time required for observing the waveform is shortened, and the failure analytical time is suppressed. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input pattern feeder used for observing an internal circuit waveform of a semiconductor integrated circuit and a method for inspecting the semiconductor integrated circuit.

[0002]

2. Description of the Related Art Recently, a system L which has been increased in scale and speed.
BIST is one of the SI test methods. In the BIST method, a self-test circuit is built in the device and a test pattern is generated in the device.

Logic BIS for logic circuits
In T, a pseudo random pattern generated by the LFSR is often used as a test pattern given to a test target circuit (hereinafter, referred to as CUT). The pseudo-random pattern described here is an n-bit signal sequence that does not repeat the same pattern that makes one cycle with a cycle length M. The size of the cycle length M depends on the configuration of the LFSR. The maximum cycle length of a pseudo random pattern that can generate an n-bit LFSR is 2 ^n-1 clocks, and an LFSR configured to maximize the cycle length of a pseudo random pattern that is generated is normally used.

A conventional pseudo random pattern generator will be described below. FIG. 1 is a block diagram of a conventional input pattern supplier. Note that here, for simplicity, 3-bit L
This will be described using FSR. In actual logic BIST, 16-bit, 24-bit, and 32-bit LFSRs are often used.

In FIG. 1, 1 is a DFF and 4 is a DFF.
This is the Q output terminal of FF1. Similarly, 2 is DFF, 5 is Q output terminal of DFF2, 3 is DFF, 6 is Q of DFF3
It is an output terminal. Reference numeral 7 is a CK input terminal to which a clock signal is input, and 8 is an RST input terminal to which a reset signal is input. The 3-bit signal (A ₀ , B ₀ , C ₀ ) is an output signal value generated by the LFSR and is applied to the CUT. Here, A ₀ is the output signal value of the Q output terminal 4, and B ₀ is the Q output terminal 5
, And the output signal value of the Q output terminal 6 is C ₀ .

Before performing the generation of the pseudo random pattern,
First, the LFSR state is initialized. What is the initial state?
The output values of the output terminal 4, the Q output terminal 5, and the Q output terminal 6 are all "1". The state of LFSR is (A ₀ , B ₀ , C ₀ ) = at the rising edge of the clock signal applied to the CK input terminal 7 when the RST input terminal 8 = “1”.
It is initialized to (1,1,1). After that, the RST input terminal 8 is set to “0”, and the 3-bit signal (A ₀ , B ₀ ,
C ₀ ) is (1,1,1) ⇒ (1,1,0) ⇒ (1,0,
0) ⇒ (0,0,1) ⇒ (0,1,0) ⇒ (1,0,
1) ⇒ (0,1,1) ⇒ (1,1,1) ⇒ ... A 3-bit signal sequence that does not repeat the same pattern that makes one cycle with a cycle length of 7 is a pseudo-random pattern.

Incidentally, in recent years, in the failure analysis of highly integrated system LSI, the internal waveform is often observed by an EB tester. E for the suspected failure location that has been narrowed down in advance using a failure diagnosis system, etc.
The final failure point can be specified by observing the internal waveform with the B tester.

The EB tester first irradiates the signal wiring with an electron beam and detects the generated secondary electrons by the secondary electron detection system. Here, the secondary electrons generated near the high-potential signal wiring cannot reach the secondary-electron detection system unless they oppose the direction of the electric field formed near the signal wiring and exceed the potential wall. On the other hand, no electric field is generated near the 0 V wiring,
Since there is no potential barrier, the generated secondary electrons can easily reach the secondary electron detection system. Therefore, if the signal wiring has a high potential, the amount of secondary electrons detected is small,
If the potential is low, there will be many.

Since the EB tester performs measurement through the capacitance of the protective film (insulating film) on the device surface, the potential of the internal signal line to be measured causes a toggle change so that the relative potential of the observed waveform can be confirmed. It is necessary to give the CUT a test pattern that will cause it. By continuously giving such a test pattern, performing secondary electron detection multiple times at each sampling time in the observed waveform, and arranging the average value of the detected secondary electron amounts along the time axis, the voltage waveform To get

FIG. 2 is a block diagram of an input pattern supply device using a scan circuit, and FIG. 3 is a time chart of the input pattern supply device using a scan circuit. Logic B
When observing the potential state of the internal signal line of the semiconductor integrated circuit to which the IST is applied, the test pattern as described above is applied from the LFSR. Consider a case where the potential state of the internal signal line L of the circuit shown in FIG. 2 is toggled by the test pattern generated from the LFSR of FIG.

In FIG. 2, reference numerals 9, 10, and 11 are scan-in terminals. The circuit of FIG. 2 is set in the scan enable state, and the output signal value A ₀ , the output signal value B ₀ , and the output generated by the circuit of FIG. 1 are output to the scan-in terminal 9, the scan-in terminal 10, and the scan-in terminal 11, respectively. A signal value C ₀ is applied. At this time, as shown in the time chart of FIG. 3, the value of (A ₀ , B ₀ , C ₀ ) of the internal signal line L is (1, 1, 1) ⇒ (1, 1, ₀ ) ⇒ (1, 0,0) ⇒
(0,0,1) ⇒ (0,1,0) ⇒ (1,0,1) ⇒
(0,1,1) ⇒ (1,1,1) causes a signal change including a toggle change in one cycle in seven clock cycles.

However, the bit width of the LFSR used in the logic BIST is normally 16 bits, 24 bits, or 32 bits, and the 16-bit LFS is used.
In R, it takes 6 times for the pseudo random pattern to make a round.
It requires 5,535 clocks. Also, 1 in 24 bits
6,777,215 clocks, 32 bits 4,29
This requires 4,967,295 clocks.

Therefore, in the above-mentioned conventional pseudo random pattern generator, it is necessary for the EB tester to continuously apply a test pattern which causes a toggle change in the potential state of the internal signal line to be observed, resulting in an enormous number of clocks. There was a problem that it required.

That is, in the inspection for detecting a normal fault, it is sufficient to provide the CUT with input signals for the number of clocks required to reach a predetermined fault detection rate. However, when observing the potential change of the internal signal line that occurs when the pseudo random pattern generated by the LFSR is applied to the CUT, it is necessary to repeatedly apply the pseudo random pattern having a long cycle length to the CUT. Therefore, there is a problem that the time required for waveform observation becomes very long and the analysis time increases.

[0015]

In order to solve the above problems, the input pattern supplier and the method for inspecting a semiconductor integrated circuit according to the present invention reduce the time required for waveform observation and suppress failure analysis time. With the goal.

[0016]

In order to achieve the above object, an input pattern supply device according to a first aspect of the present invention is an input for supplying an n-bit signal string input when observing an internal waveform of a semiconductor integrated circuit. A pattern supply device, which generates an n-bit signal sequence that does not repeat the same pattern that makes a cycle of 2 ^n-1 clocks, and n bits that outputs an n-bit signal sequence of the pseudo-random pattern generator Output terminal, a reset terminal for setting the output value of the pseudo random pattern generator to an initial value, a mode setting terminal for setting the operation of the input pattern supplier according to the operation mode of the semiconductor circuit, and the n-bit and a reset circuit which signal sequence is set to an initial value the pseudo random pattern generator by outputting the arbitrarily set value, 2 ^n-1 Replace the n-bit signal sequence to cycle the lock to an initial value when the value set in the arbitrary is output, characterized in that to shorten the period of the input pattern.

The input pattern supply device according to claim 2 is an input pattern supply device for supplying an n-bit signal string input at the time of observing an internal waveform of a semiconductor integrated circuit, and the same pattern which makes ^one cycle ^every 2 ^n-1 clocks. A pseudo-random pattern generator for generating an n-bit signal sequence, an n-bit output terminal for outputting the n-bit signal sequence of the pseudo-random pattern generator, and an output value of the pseudo-random pattern generator as initial values. A reset terminal, a mode setting terminal for setting the operation of the input pattern supplier according to the operation mode of the semiconductor circuit, an n-bit input terminal corresponding to the n-bit signal string input from the outside, and Reset for setting the pseudo random pattern generator to an initial value by inputting an arbitrarily set value from an n-bit input terminal And a circuit, the ^n- bit signal sequence that makes a cycle of 2 ^n-1 clocks is returned to the initial value when the arbitrarily set value is input, and the cycle of the input pattern is shortened.

The input pattern supplier according to claim 3 is an input pattern supplier that supplies an n-bit signal string input when observing an internal waveform of a semiconductor integrated circuit, and has the same pattern that makes ^one cycle ^every 2 ^n-1 clocks. A pseudo-random pattern generator for generating an n-bit signal sequence, an n-bit output terminal for outputting the n-bit signal sequence of the pseudo-random pattern generator, and an output value of the pseudo-random pattern generator as initial values. A reset terminal, a mode setting terminal for setting the operation of the input pattern supplier according to the operation mode of the semiconductor circuit, an n-bit input terminal for controlling the output value of the pseudo random pattern generator, The n-bit signal sequence is input to the pseudo-random pattern generator from the input terminal by outputting an arbitrarily set value. And a reset circuit for setting a value, which sets an ^n- bit signal string that makes a cycle of 2 ^n-1 clocks to a value input from the input terminal when the arbitrarily set value is output. It is characterized by shortening the cycle of.

The input pattern supply device according to claim 4 is an input pattern supply device for supplying an n-bit signal sequence input at the time of observing an internal waveform of a semiconductor integrated circuit, and the same pattern which makes ^one cycle ^every 2 ^n-1 clocks. A pseudo-random pattern generator for generating an n-bit signal sequence, an n-bit output terminal for outputting the n-bit signal sequence of the pseudo-random pattern generator, and an output value of the pseudo-random pattern generator as initial values. , A mode setting terminal for setting the operation of the input pattern supplier according to the operation mode of the semiconductor circuit, and an n-bit first input terminal for controlling the output value of the pseudo random pattern generator. And an n-bit second input terminal that is externally input and corresponds to the n-bit signal string and an n-bit second input terminal. A reset circuit configured to set the value input from the first input terminal to the pseudo random pattern generator by inputting the set value.
^{The n-} bit signal train that makes a cycle of ^{n- 1} clocks is set to the value input from the first input terminal when the arbitrarily set value is input, and the cycle of the input pattern is shortened. .

According to a fifth aspect of the semiconductor integrated circuit inspection method of the present invention, a step of generating an n-bit signal string that makes a cycle of 2 ^n-1 clocks and an output of the n-bit signal string according to an arbitrary value of the n-bit signal string. The method is characterized by including a step of resetting a value to shorten a cycle of one round, and a step of performing a scan path test using an output value of the n-bit signal sequence in which the cycle of the round is shortened.

As described above, the time required for waveform observation can be shortened and the failure analysis time can be suppressed.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) Embodiment 1 of the present invention will be described with reference to the drawings.

FIG. 4 is a block diagram of the input pattern supply unit according to the first embodiment of the present invention. The same reference numerals are given to the already-described components, and the description thereof will be omitted. 5 is a time chart of the input pattern supply device in the operation mode I in the first embodiment of the present invention, and FIG. 6 is a time chart of the input pattern supply device in the operation mode II in the first embodiment of the present invention. It is a chart.

In FIG. 4, 12 is DFF1, DFF2, DF
A pseudo random pattern generator configured by F3 and EXOR13, which generates a 3-bit signal sequence that does not repeat the same pattern that makes one cycle in 7 clocks, and has a reset function to an initial state. The 3-bit signal (A ₁ , B ₁ , C ₁ ) is the output signal value generated by the pseudo random pattern generator 12, A ₁ is the output signal value of the Q output terminal 4, and B ₁ is the output of the Q output terminal 5. The signal value, C ₁ is the output signal value of the Q output terminal 6. This 3-bit signal is applied to the CUT.

A reset circuit 19 has a function of resetting the state of the pseudo random pattern generator 12 when (A ₁ , B ₁ , C ₁ ) satisfies a predetermined specific condition. Here, the reset circuit 19 includes an AND circuit 22 having an inverted value of the output signal value A _1, an inverted value of the output signal value B ₁ and the output signal value C ₁ as input values, and an AND circuit 22.
Of the AND circuit 23 and the MODE input signal 20, and an OR circuit 24 that receives the output of the AND circuit 23 and the input of the RST input terminal 8, and the input value of the RST input terminal 8 is "1". And MODE input signal 2
The input value of 0 is “1”, and (A ₁ , B ₁ , C ₁ ) =
When (0, 0, 1), the output value of the reset signal 21 is set to "
It is set to "1" and DFF1, DFF2, DFF3 are reset.

There are two operation modes of the semiconductor integrated circuit according to the first embodiment of the present invention: an operation mode I in a normal scan test and an operation mode II in a waveform measurement by the EB tester. The operation modes I and II are switched by the value given to the MODE input signal 20. When the MODE input signal 20 = “0”, the operation mode I is set, and when the MODE input signal 20 = “1”, the operation mode II is set.

The operation of resetting the pseudo random pattern generator 12 to the initial state will be described. Here, the initial state is a state in which the output values of the Q output terminal 4, the Q output terminal 5, and the Q output terminal 6 are all "1". Reference numeral 21 denotes a reset signal of the pseudo random pattern generator 12, which is output from the reset circuit 19. In the operation mode I (MODE input signal 20 = "0"), the input value of the RST input terminal 8 is "
When it is 1 ", the reset signal 21 =" 1 ", and when the input value of the RST input terminal 8 is" 0 ", the reset signal 21 =""
0 ". Operation mode II (MODE input signal 20 =""
1 "), when the input value of the RST input terminal 8 is" 1 "or (A ₁ , B ₁ , C ₁ ) = (0, 0, 1), the reset signal 21 =" 1 ", and In all other cases, the reset signal 21 is “0.” The state of the pseudo random pattern generator 12 is C when the reset signal 21 is “1”.
The initial state is reset in synchronization with the rising edge of the clock signal applied to the K input terminal 7, and the operation is continued when the reset signal 21 = "0".

The operation of each of the operation modes I and II in the first embodiment of the present invention will be described. First, the operation mode I will be described. MOD to set to operation mode I
The E input signal 20 is fixed to "0". RST input terminal 8
The clock signal is applied to the CK input terminal 7 with the input value of 1 set to "1". After the start of clock application, the pseudo random pattern generator 12 is reset to the initial state at the first rising edge. RS on the falling edge of the next clock
The input value of the T input terminal 8 is set to "0". Then, the rising edge of the clock, the value of A _1, the value of B _1, C ₁ are as shown in the time chart of FIG. _{5 (A 1, B 1,} C 1) is (1,1,1) ⇒ ( 1,1,0) ⇒ (1,0,0) ⇒
(0,0,1) ⇒ (0,1,0) ⇒ (1,0,1) ⇒
It cycles through (0,1,1) → (1,1,1) in 7 clock cycles. This mode is mainly used when performing a scan test.

Next, the operation mode II will be described. The MODE input signal 20 is fixed to "1" to set the operation mode II. Set the input value of RST input terminal 8 to "1"
A clock signal is applied to the K input terminal 7. After the clock is applied, the pseudo random pattern generator 12 is reset to the initial state at the first rising edge. The input value of the RST input terminal 8 is set to "0" at the next falling edge of the clock.
And Then on the rising edge of the clock,
A _1, the value of B _1, C ₁ are as shown in the time chart of FIG. 6, is reset at _{(A 1, B 1, C} 1) = (0,0,1), (A 1, B 1 , C ₁ ) is (1,1,1) ⇒
(1,1,0) ⇒ (1,0,0) ⇒ (0,0,1) ⇒
It cycles through (1, 1, 1) and 4 clock cycles. This mode is used when the state of the internal signal line of the CUT is observed by the EB tester.

The circuit shown in FIG. 2 will be described by taking the case of observing the state of the internal signal line L as an example. First, the pseudo random pattern generator according to the first embodiment of the present invention shown in FIG. 4 is operated in the operation mode II. The circuit of FIG. 2 is set in the scan enable state, and the scan-in terminal 9, the scan-in terminal 10, and the scan-in terminal 11 generate the output signal value A ₁ , the output signal value B ₁ , and the output signal of the circuit of FIG. 4, respectively. Apply the value C ₁ . At this time, as shown in the time chart of FIG. 6, the internal signal line L can cause a signal change including a toggle change that makes one cycle in four clock cycles after the lapse of four clocks from the reset.

As described above, (A ₁ , B ₁ , C ₁ ) =
Since the reset is applied at (0, 0, 1) and the same cycle is repeated, the EB tester waveform measurement time is shortened to 4/7 as compared with the configuration shown in the related art according to the first embodiment of the present invention. it can. (Embodiment 2) Embodiment 2 of the present invention will be described with reference to the drawings.

FIG. 7 shows a block diagram of an input pattern supply device according to the second embodiment of the present invention. The same reference numerals are given to the already-explained components, and the description thereof will be omitted. In FIG. 7, 3
The bit signals (A ₂ , B ₂ , C ₂ ) are output signal values generated by the pseudo random pattern generator 12, A ₂ is an output signal value of the Q output terminal 4, and B ₂ is an output signal of the Q output terminal 5. The value, C ₂ is the output signal value of the Q output terminal 6. This 3-bit signal is applied to the CUT.

31 is a signal value (A
_{'2, B'2,} as input _{C'2), (A 2,} B 2, C2)
_{= (A'2, B'2,} C'2) when a is a reset circuit having a function of resetting the state of the pseudo-random pattern generator 12 to the initial state. Here, the reset circuit 31 includes an EXOR circuit 25 having the output signal value A ₂ and the signal value A ′ ₂ as input values, the output signal value B ₂ and the output signal value B ′ _2.
An EXOR circuit 26 having an input value of, an EXOR circuit 27 having an output signal value C ₂ and a signal value C ′ ₂ as input values, and an EX
Output of OR circuit 25, output of EXOR circuit 26 and EXO
A NOR circuit 28 that receives the output of the R circuit 27 as an input;
An AND circuit 29 that receives the output of the R circuit 28 and the MODE input signal 20 and an OR circuit 30 that receives the output of the AND circuit 29 and the input of the RST input terminal 8 as input, and the input value of the RST input terminal 8 When is "1" and MOD
The input value of the E input signal 20 is “1”, the output signal value A ₂ and the signal value A ′ ₂ are the same value, the output signal value B ₂ and the signal value B ′ ₂ are the same value, and the output signal value When C ₂ and the signal value C ′ ₂ have the same value, the output value of the reset signal 21 is set to “1”, and the DFF1, DFF2, and DFF3 are reset.

The operation modes of the semiconductor integrated circuit according to the second embodiment of the present invention include the operation mode I during the normal scan test and the operation during the waveform measurement by the EB tester, as in the first embodiment of the present invention. There are two modes, Mode II. The operation modes I and II are switched by the value given to the MODE input signal 20. When the MODE input signal 20 = “0”, the operation mode I is set, and when the MODE input signal 20 = “1”, the operation mode II is set.

The operation of resetting the pseudo random pattern generator 12 to the initial state will be described. Here, the initial state is a state in which the output values of the Q output terminal 4, the Q output terminal 5, and the Q output terminal 6 are all "1". Reference numeral 21 denotes a reset signal of the pseudo random pattern generator 12, which is output from the reset circuit 19. In the operation mode I (MODE input signal 20 = "0"), the input value of the RST input terminal 8 is "
When it is 1 ", the reset signal 21 =" 1 ", and when the input value of the RST input terminal 8 is" 0 ", the reset signal 21 =""
In the operation mode II, the input value of the RST input terminal 8 is “1” or (A ₂ , B ₂ , C ₂ ) = (A ′ ₂ ,
_B'2, the reset signal 21 = "1" when the _C'2), the reset signal 21 = "0" at other times. The state of the pseudo random pattern generator 12 is reset to the initial state in synchronization with the rising edge of the clock signal applied to the CK input terminal 7 when the reset signal 21 = "1", and the reset signal 21 = "0". When, the operation is continued.

The respective operations of the operation modes I and II in the second embodiment of the present invention will be described. First, the operation mode I will be described. MOD to set to operation mode I
The E input signal 20 is fixed to "0". RST input terminal 8
The clock signal is applied to the CK input terminal 7 with the input value of 1 set to "1". After the start of clock application, the pseudo random pattern generator 12 is reset to the initial state at the first rising edge. RS on the falling edge of the next clock
The input value of the T input terminal 8 is set to "0". Then, the rising edge of the clock, the output value A _2, the output value B _2, the value of the output value C ₂ is as shown in the time chart of FIG. 5 (A _2,
The value of B ₂ , C ₂ ) is (1,1,1) ⇒ (1,1,0) ⇒
(1,0,0) ⇒ (0,0,1) ⇒ (0,1,0) ⇒
(1,0,1) ⇒ (0,1,1) ⇒ (1,1,1) and 7
It patrols in clock cycles. This mode is mainly used when performing a scan test.

Next, the operation mode II will be described. motion
Set MODE input signal 20 = "1" to set to mode II
Fix it. In addition, (A₂, B₂, C₂) = (0,0,1)
At the time of, the state of the pseudo random pattern generator 12 is initialized.
In order to realize (A '₂, B '₂, C '₂) = (0,0,
A signal is given from the outside so that 1). RST input terminal
Set the input value of child 8 to "1" and clock to CK input terminal 7
Apply a signal. After the clock is applied, the first rising edge
The pseudo random pattern generator 12 to the initial state.
Set. RS on the falling edge of the next clock
The input value of the T input terminal 8 is set to "0". Then the clock
Output signal value A at the rising edge of ₂, Output signal value
B₂, Output signal value C₂Values are shown in the time chart of FIG.
So that (A₂, B₂, C₂) = (0,0,1)
It takes a lot of time (A₂, B₂, C₂) Is (1,1,1)
⇒ (1,1,0) ⇒ (1,0,0) ⇒ (0,0,1) ⇒
It cycles through (1, 1, 1) and 4 clock cycles. This mo
DO observes the state of the internal signal line of the CUT with the EB tester.
It is used when

The case of observing the state of the internal signal line L of the circuit shown in FIG. 2 will be described as an example. The semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 7 is operated in operation mode II. The circuit of FIG. 2 is set to the scan enable state, and the output signal value A ₂ , the output signal value B ₂ , and the output signal value C ₂ of FIG. ₇ are applied to the scan terminal 9, the scan terminal 10, and the scan terminal 11, respectively. At this time, the internal signal line L
4 from reset as shown in the time chart of FIG.
A signal change including a toggle change occurs once every four clock cycles after the clock has elapsed.

As described above, (A ₂ , B ₂ , C ₂ ) =
Since the reset is applied at (0, 0, 1) and the same cycle is repeated, according to the configuration of the second embodiment of the present invention, the EB tester waveform measurement time is 4/7 compared to the configuration shown in the conventional technique. Can be shortened to (Embodiment 3) Embodiment 3 of the present invention will be described with reference to the drawings.

FIG. 8 is a block diagram of an input pattern supply unit according to the third embodiment of the present invention, in which already-explained components are given the same symbols and their explanations are omitted. In FIG. 8, 5
0 is a pseudo random pattern generator, and DFF1, D
FF2, DFF3, MUX46, MUX47, MUX4
8, EXOR13. 43, 44, 45
Are D inputs of DFF1, DFF2, and DFF3, respectively. The MUX 46 selects either the output value of the Q output terminal 5 or the input value of the external input terminal X ₀ by the reset signal 21 and inputs it to the DFF 1 as the D input 43 of the DFF 1, and the MUX 47 outputs the output of the Q output terminal 6. One of the value and the input value of the external input terminal Y ₀ is selected by the reset signal 21 and input to the DFF 2 as the D input 44 of the DFF 2, and the MUX 48 outputs the output value of the EXOR 13 and the input value of the external input terminal Z ₀ . Reset signal 21 from either
Selected by DFF2 as D input 45 of DFF3
To enter.

The 3-bit signals (A ₃ , B ₃ , C ₃ ) are output signal values generated by the pseudo random pattern generator 50, A ₃ is the output signal value of the Q output terminal 4, and B ₃ is the Q output terminal. 5 is an output signal value of C, and C ₃ is an output signal value of the Q output terminal 6. This 3-bit signal is applied to the CUT.

49 is (A ₃ , B ₃ , C ₃ ) = (0, 0,
The reset circuit has a function of resetting the state of the pseudo random pattern generator 50 at the time of 1). Here, the reset circuit 49 receives the inverted value of the output signal value A ₃ , the inverted value of the output signal value B ₃ , and the output signal value C ₃ as input values A.
An ND circuit 40 and an AND circuit 41 that receives the output of the AND circuit 40 and the MODE input signal 20 as input,
When the input value of the MODE input signal 20 is “1”, (A ₃ ,
B _3, C ₃₎ = and becomes (0, 0, 1), the reset signal 2
"1" is output as 1.

As in the first embodiment of the present invention, the operation modes of the semiconductor integrated circuit in the third embodiment of the present invention include the operation mode I in the normal scan test and the operation mode in the waveform measurement by the EB tester. There are two, II. The operation modes I and II are switched by the value given to the MODE input signal 20. When the MODE input signal 20 = “0”, the operation mode I is set, and when the MODE input signal 20 = “1”, the operation mode II is set.

The operation of resetting the pseudo random pattern generator 50 to the initial state will be described. Here, the initial state is a state in which the output values of the Q output terminal 4, the Q output terminal 5, and the Q output terminal 6 are all "1". Reference numeral 21 is a reset signal of the pseudo random pattern generator 50, which is output from the reset circuit 49. Further, when the input value of the RST input terminal 8 is “1”, it is reset to the initial state in synchronization with the rising edge of the clock signal applied to the CK input terminal 7.

With the above configuration, the output value of the pseudo random pattern generator 50 can be output as an arbitrary output value by external control. The reset signal 21 is a signal that sets the pseudo random pattern generator 50 to an arbitrary state, and is output from the reset circuit 49 of the present invention. When the reset signal 21 = “1”, the value of the Q output terminal 4 becomes the input value of the external input signal X ₀ in synchronization with the rising edge of the clock signal applied to the CK input terminal 7.
The value of the Q output terminal 5 is set to the input value of the external input signal Y ₀ , and the value of the Q output terminal 6 is set to the input value of the external input signal Z ₀ .

Operation mode I (MODE input signal 20 = ""
0 "), the reset signal 21 is always" 0 ". In the operation mode II (MODE input signal 20 =" 1 "),
When (A ₃ , B ₃ , C ₃ ) = (0, 0, 1), the reset signal 21 becomes "1", and the input value of the external input signal X ₀ ,
The input value of the external input signal Y _{0 and} the input value of the external input signal Z ₀ are set in the pseudo random pattern generator 50.

The operation of each of the operation modes I and II will be described. First, the operation mode I will be described. In order to set the operation mode I, the MODE input signal 20 is fixed to "0". The input value of the RST input terminal 8 is set to "1" and the clock signal is applied to the CK input terminal 7. After the start of clock application, the pseudo random pattern generator 50 is reset to the initial state at the first rising edge. The input value of the RST input terminal 8 is set to "0" at the next falling edge of the clock.
And Then on the rising edge of the clock,
A _3, B _3, the values of C ₃ is as shown in the time chart of FIG. _{5 (A 3, B 3,} C 3) is (1,1,1) ⇒ (1,
1,0) ⇒ (1,0,0) ⇒ (0,0,1) ⇒ (0,
1,0) ⇒ (1,0,1) ⇒ (0,1,1) ⇒ (1,
1, 1) and 7 clock cycles. This mode is mainly used when performing a scan test.

Next, the operation mode II will be described. MODE input signal 20 = “1” to set to operation mode II
Fixed to. Further, here, (X ₀ , Y ₀ , Z ₀ ) =
It is assumed that it is (1, 0, 0). The input value of the RST input terminal 8 is set to "1" and the clock signal is applied to the CK input terminal 7. After applying the clock, the pseudo random pattern generator 50 is reset to the initial state at the first rising edge. The input value of the RST input terminal 8 is set to "0" at the next falling edge of the clock. Then, at the rising edge of the clock, the values of A ₃ , B ₃ , and C ₃ are (A ₃ , B ₃ , C ₃ ) = (0, 0, as shown in the time chart of FIG.
The reset is applied in 1), and the value of (A ₃ , B ₃ , C ₃ ) cycles from (1, 0, 0) to (0, 0, 1) in 2 clock cycles after 4 clocks have elapsed from the reset. . This mode is used when the state of the internal signal of the CUT is observed by the EB tester.

The case of observing the state of the internal signal line L of the circuit shown in FIG. 2 will be described as an example. The semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. 8 is operated in operation mode II. The circuit of FIG. 2 is set to the scan enable state, and the output signal value A ₃ , the output signal value B ₃ , and the output signal value C ₃ of FIG. 8 are applied to the scan terminal 9, the scan terminal 10, and the scan terminal 11, respectively. At this time, the internal signal line L
Causes a signal change including a toggle change that makes a cycle in two clock cycles, as shown in the time chart of FIG.

As described above, (A ₃ , B ₃ , C ₃ ) =
Reset is applied at (0, 0, 1), and (X
By inputting ₀ , Y ₀ , Z ₀ ) = (1, ₀ , ₀ ), (A ₃ , B ₃ , C ₃ ) = (0, 0, at the next clock.
1) and the operation is repeated in two clock cycles. Therefore, according to the configuration of the third embodiment of the present invention, compared to the conventional method,
The EB tester waveform measurement time can be shortened to 2/7. (Embodiment 4) Embodiment 4 of the present invention will be described with reference to the drawings.

FIG. 10 is a block diagram of the input pattern supply unit according to the fourth embodiment of the present invention, in which already-explained components are given the same symbols and their explanations are omitted. In FIG. 10, the 3-bit signals (A ₄ , B ₄ , C ₄ ) are the output signal values generated by the pseudo random pattern generator 50, A ₄ is the output signal value of the Q output terminal 4, and B ₄ is the Q output. The output signal value of the terminal 5 and C ₄ are the output signal value of the Q output terminal 6. This 3-bit signal is applied to the CUT. 31 signals are given from the outside _{(A'4, B'4, C'} 4) as inputs, (A4, B4, C4) = (A'4, B'4, C'4)
In this case, the reset circuit has a function of setting the state of the pseudo random pattern generator 50 to a value given from the outside, and when the input value of the RST input terminal 8 is “1” and the MODE input signal 20 is input. The value is "1", and
The output signal value A ₄ and the output signal value A ′ ₄ are the same value, the output signal value B ₄ and the output signal value B ′ ₄ are the same value, and the output signal value C
₄ and the output signal value C ′ ₄ are the same value, the output value of the reset signal 21 is set to “1”, and DFF1, DFF2, DFF3
To reset.

The operation mode of the semiconductor integrated circuit according to the fourth embodiment of the present invention is similar to that of the first embodiment of the present invention.
There are two operation modes, i.e., an operation mode I at the time of the normal scan test and an operation mode II at the time of waveform measurement by the EB tester. The operation modes I and II are switched according to the value given to the external input terminal MODE input signal 20. MODE input signal 20
When = "0", the mode input signal 20
When it is "1", it becomes the operation mode II.

The operation of resetting the pseudo random pattern generator 50 to the initial state will be described. Here, the initial state is a state in which the output values of the Q output terminal 4, the Q output terminal 5, and the Q output terminal 6 are all "1". Reference numeral 21 is a reset signal of the pseudo random pattern generator 50, which is output from the reset circuit 31. Further, when the input value of the RST input terminal 8 is “1”, it is reset to the initial state in synchronization with the rising edge of the clock signal applied to the CK input terminal 7.

With the above configuration, the output value of the pseudo random pattern generator 50 can be output as an arbitrary output value by external control. The reset signal 21 is a signal that sets the pseudo random pattern generator 50 to an arbitrary state, and is output from the reset circuit 31 of the present invention. When the reset signal 21 = “1”, the value of the Q output terminal 4 becomes the input value of the external input signal X ₀ in synchronization with the rising edge of the clock signal applied to the CK input terminal 7.
The value of the Q output terminal 5 is set to the input value of the external input signal Y ₀ , and the value of the Q output terminal 6 is set to the input value of the external input signal Z ₀ .

Operation mode I (MODE input signal 20 = ""
0 "), the reset signal 21 is always" 0 ". In the operation mode II (MODE input signal 20 =" 1 "),
(A4, B4, C4) = (A'4, B'4, C'4) reset signal = "1", the input value of the external input signal X ₀ when the input value of the external input signal Y _0, The input value of the external input signal Z ₀ is set in the pseudo random pattern generator 50.

The operation of each of the operation modes I and II will be described. First, the operation mode I will be described. In order to set the operation mode I, the MODE input signal 20 is fixed to "0". The input value of the RST input terminal 8 is set to "1" and the clock signal is applied to the CK input terminal 7. After the start of clock application, the pseudo random pattern generator 50 is reset to the initial state at the first rising edge. The input value of the RST input terminal 8 is set to "0" at the next falling edge of the clock.
And Then on the rising edge of the clock,
A _4, B _4, the value of such that the value of C ₄ is shown in the time chart of FIG. _{5 (A 4, B 4,} C 4) is (1,1,1) ⇒ (1,
1,0) ⇒ (1,0,0) ⇒ (0,0,1) ⇒ (0,
1,0) ⇒ (1,0,1) ⇒ (0,1,1) ⇒ (1,
1, 1) and 7 clock cycles. This mode is mainly used when performing a scan test.

Next, the operation mode II will be described. motion
Set MODE input signal 20 = "1" to set to mode II
Fix it. Also, here, (X₀, Y₀, Z₀) =
(1,0,0), (A '_Four, B '_Four, C '_Four) = (0,
0, 1). Set the input value of RST input terminal 8 to "
The clock signal is applied to the CK input terminal 7 as 1 ″.
Pseudo-lander on the first rising edge after applying the clock
The pattern generator 50 is reset to the initial state. Next
Input of RST input terminal 8 at the falling edge of
The force value is "0". After that, the rising edge of the clock
A,_Four, B_Four, C _FourValues are shown in the time chart of Fig. 9.
As shown, (A_Four, B_Four, C_Four) = (0,0,1)
It takes a set, (A_Four, B_Four, C_Four) Is (1,0,
0) ⇒ (0, 0, 1), 4 clocks have elapsed since reset
After that, it goes around in two clock cycles. This mode is EB
Used when observing the internal signal state of the CUT
It

The case of observing the state of the internal signal line L of the circuit shown in FIG. 2 will be described as an example. The semiconductor integrated circuit according to the fourth embodiment of the present invention shown in FIG.
To work with. The circuit of FIG. 2 is set to the scan enable state, and the output signal value A ₄ , the output signal value B ₄ , and the output signal value C ₄ of FIG. 10 are applied to the scan terminal 9, the scan terminal 10, and the scan terminal 11, respectively. At this time, the internal signal line L causes a signal change including a toggle change that makes one cycle in two clock cycles, as shown in the time chart of FIG.

As described above, (A ₄ , B ₄ , C ₄ ) =
Reset is applied at (0, 0, 1), and (X
By inputting ₀ , Y ₀ , Z ₀ ) = (1, ₀ , ₀ ), (A ₄ , B ₄ , C ₄ ) = (0, 0, at the next clock.
1), the operation is repeated in two clock cycles, so that according to the configuration of the fourth embodiment of the present invention, compared to the conventional method,
The EB tester waveform measurement time can be shortened to 2/7. (Fifth Embodiment) A fifth embodiment of the present invention will be described with reference to the drawings.

Generated by the semiconductor integrated circuit shown in FIG.
The scan chain shown in FIG.
The case of operating the circuit in which the
It The semiconductor integrated circuit shown in FIG. 4 is operated in operation mode II.
Let Set the circuit of Figure 2 to the scan enable state and
Can-in terminal 9, scan-in terminal 10, scan-y terminal
Output signal value A of FIG.₁, Output signal
Issue B₁, Output signal value C ₁Apply a scan path test
To do. At this time, the internal signal line L is shown in the time chart of FIG.
As shown, it includes a toggle change that makes one cycle in four clock cycles.
Signal changes. As a result, in the semiconductor integrated circuit
EB tester with embedded pseudo-random pattern
When observing a waveform, check the signal wiring you want to observe.
Signal toggle change in a shorter cycle than the conventional method.
Therefore, the EB tester waveform measurement time can be shortened.
Similarly, the signals generated from the circuits of FIG. 7, FIG. 8 and FIG.
When applied to the scan chain of the circuit in Figure 2,
Toggle the signal value of the observation target signal wiring in a short cycle.
And further reduce the EB tester waveform measurement time.
It

[0061]

As described above, according to the input pattern supply device and the semiconductor integrated circuit inspection method of the present invention, when observing the internal circuit waveform of the semiconductor device, the pseudo random pattern generator outputs a specific output. Correspondingly, by adding a reset circuit that sets the pseudo random pattern generator to the initial value, the cycle of the output random pattern can be shortened, the time required for waveform observation can be shortened, and the failure analysis time can be suppressed. it can.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a conventional input pattern supply device.

FIG. 2 is a block diagram of an input pattern supplier using a scan circuit.

FIG. 3 is a time chart of an input pattern supplier using a scan circuit.

FIG. 4 is a configuration diagram of an input pattern supply device according to the first embodiment of the present invention.

FIG. 5 is a time chart of the input pattern supply device in the operation mode I according to the first embodiment of the present invention.

FIG. 6 is a time chart of the input pattern supply device in the operation mode II according to the first embodiment of the present invention.

FIG. 7 is a configuration diagram of an input pattern supply device according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram of an input pattern supply device according to a third embodiment of the present invention.

FIG. 9 is a time chart of the input pattern supply device in the operation mode II according to the third embodiment of the present invention.

FIG. 10 is a configuration diagram of an input pattern supply device according to a fourth embodiment of the present invention.

[Explanation of symbols]

1 DFF 2 DFF 3 DFF 4 Q output terminal 5 Q output terminal 6 Q output terminal 7 CK input terminal 8 RST input terminal 9 scan-in terminal 10 scan-in terminal 11 scan-in terminal 12 pseudo-random pattern generator 13 EXOR 19 reset circuit 20 MODE input signal 21 reset signal 22 AND circuit 23 AND circuit 24 OR circuit 25 EXOR circuit 26 EXOR circuit 27 EXOR circuit 28 NOR circuit 29 AND circuit 30 OR circuit 31 reset circuit 40 AND circuit 41 AND circuit 43 D input 44 D input 45 D Input 46 MUX 47 MUX 48 MUX 49 Reset circuit 50 Pseudo random pattern generator A ₀ Output signal value B ₀ Output signal value C ₀ Output signal value A ₁ Output signal value B ₁ Output signal value C ₁ Output signal value A ₂ Output signal Value B ₂ output signal Value C ₂ output signal Value _A'2 signal values _B'2 signal values _C'2 signal value A ₃ output signal values B ₃ output signal values C ₃ output signal values A ₄ output signal value B ₄ output signal value C ₄ output signal value _A'4 signals value _B'4 signal values _C'4 signal values L internal signal lines X ₀ external input terminal Y ₀ external input terminal Z ₀ external input terminal

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2G132 AA01 AC14 AG05 AG08 AK07                       AK14 AK15 AK22 AK29 AL09                 5F038 DT02 DT03 DT06 DT07 DT15                       EZ20

Claims (5)

[Claims] 1. An input pattern supply device for supplying an n-bit signal string input when observing an internal waveform of a semiconductor integrated circuit, which generates an n-bit signal string that does not repeat the same pattern that makes a cycle of 2 ^n-1 clocks. A pseudo-random pattern generator, an n-bit output terminal that outputs an n-bit signal string of the pseudo-random pattern generator, a reset terminal that sets an output value of the pseudo-random pattern generator to an initial value, and the semiconductor A mode setting terminal for setting the operation of the input pattern supplier according to the operation mode of the circuit, and the pseudo random pattern generator is set to an initial value by outputting a value to which the n-bit signal string is arbitrarily set. And a reset circuit for resetting the ^n- bit signal sequence that makes a cycle of 2 ^n-1 clocks, and returns it to the initial value when the arbitrarily set value is output. An input pattern supply device characterized by shortening the cycle of the input pattern. 2. An input pattern supply device for supplying an n-bit signal string input at the time of observing an internal waveform of a semiconductor integrated circuit, which generates an n-bit signal string that does not repeat the same pattern that makes a cycle of 2 ^n-1 clocks. A pseudo-random pattern generator, an n-bit output terminal that outputs an n-bit signal string of the pseudo-random pattern generator, a reset terminal that sets an output value of the pseudo-random pattern generator to an initial value, and the semiconductor A mode setting terminal for setting the operation of the input pattern supplier according to the operation mode of the circuit, an n-bit input terminal corresponding to the n-bit signal string input from the outside, and arbitrarily set from the n-bit input terminal and a reset circuit for setting the pseudo-random pattern generator to the initial value by inputting the value, one 2 ^n-1 clock n-bit signal string back to the initial value when the value set in the arbitrary inputs, input pattern feeder, characterized in that to shorten the period of the input pattern. 3. An input pattern supply device for supplying an n-bit signal string input when observing an internal waveform of a semiconductor integrated circuit, which generates an n-bit signal string that does not repeat the same pattern that makes a cycle of 2 ^n-1 clocks. A pseudo-random pattern generator, an n-bit output terminal that outputs an n-bit signal string of the pseudo-random pattern generator, a reset terminal that sets an output value of the pseudo-random pattern generator to an initial value, and the semiconductor A mode setting terminal for setting the operation of the input pattern supplier according to the operation mode of the circuit, and n for controlling the output value of the pseudo random pattern generator.
A bit input terminal; and a reset circuit for setting the value input from the input terminal to the pseudo random pattern generator by outputting an arbitrarily set value of the n-bit signal string. An input pattern supply, characterized in that an n-bit signal train that makes a cycle of ^n-1 clocks is set to a value input from the input terminal when the arbitrarily set value is output, and the cycle of the input pattern is shortened. vessel. 4. An input pattern supply device for supplying an n-bit signal string input at the time of observing an internal waveform of a semiconductor integrated circuit, which generates an n-bit signal string that does not repeat the same pattern that makes a cycle of 2 ^n-1 clocks. A pseudo-random pattern generator, an n-bit output terminal that outputs an n-bit signal string of the pseudo-random pattern generator, a reset terminal that sets an output value of the pseudo-random pattern generator to an initial value, and the semiconductor A mode setting terminal for setting the operation of the input pattern supplier according to the operation mode of the circuit, and n for controlling the output value of the pseudo random pattern generator.
A bit first input terminal, an n-bit second input terminal that is externally input and corresponds to the n-bit signal sequence, and an arbitrarily set value is input from the n-bit second input terminal And a reset circuit for setting the value input from the first input terminal to the pseudo random pattern generator, and the value obtained by arbitrarily setting the n-bit signal sequence that makes a cycle of 2 ^n-1 clocks is An input pattern supply device characterized by setting the value input from the first input terminal at the time of input to shorten the cycle of the input pattern. 5. A step of generating an n-bit signal string that makes a cycle in 2 ^n-1 clocks, and resetting an output value of the n-bit signal string by an arbitrary value of the n-bit signal string to shorten a cycle of the cycle. And a step of performing a scan path test using the output value of the n-bit signal string with the cycle cycle shortened, the method of inspecting a semiconductor integrated circuit.