JP2003309613A - Clock phase control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize an advance/delay decision less dependent on the layout/ number of signal points with little characteristics deterioration. <P>SOLUTION: A weighted means over a demodulated signal value or its decision value at a decision timing t1 and a demodulated signal value or its decision value at the next decision timing t3 is obtained to set up a phase decision threshold to be compared with a demodulated signal value at an intermediate timing t2. This decision threshold uses no fixed set threshold for deciding the phase and hence does not cause characteristics deterioration due to an amplitude error or a center signal level offset. Even the increase in the number of signal points does not complicate the decision condition, this facilitating embodiments and easily dealing with various modulation systems. This ensures a sufficient phase decision executing frequency. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to multi-valued QAM (Quad
rature Ampliude Modulation) A clock phase control method executed in a demodulator or the like.

[0002]

2. Description of the Related Art FIG. 3 shows an example configuration of a QAM demodulator. The demodulator shown in this figure is a demodulator used in a receiver or the like for a communication system that transmits and receives a signal modulated by a multilevel QAM method. This demodulator has in-phase (I)
And a circuit system corresponding to each component of the quadrature (Q). Each circuit system has a configuration in which the mixer 10, the LPF 16, the A / D converter 18, and the detector 20 are connected in cascade. The mixer 10 mixes the received signal and the local oscillation signal,
The LPF 16 low-pass filters the output of the corresponding mixer 10, and the A / D converter 18 outputs the output of the corresponding LPF 16 to A
After the D / D conversion, the detector 20 determines the sign of the output of the corresponding A / D converter 18 according to the determination clock.

In addition to these circuit systems, the illustrated demodulator includes a local oscillator 12, a π / 2 phase shifter 14, a clock recovery unit 22 and a P / S converter 30. The local oscillator 12 generates a local oscillation signal by oscillating at a predetermined frequency. The π / 2 phase shifter 14 has a π / 2 between the local oscillation signal supplied to the mixer 10I for the I component and the local oscillation signal supplied to the mixer 10Q for the Q component.
The output of the local oscillator 12 is phase-shifted / distributed so that a phase difference of [rad] is generated. The clock recovery unit 22 includes the detector 2
The judgment clock is regenerated from the output of 0I and 20Q, and P / S
The converter 30 performs parallel / serial conversion on the outputs of the wave detectors 20I and 20Q and outputs the reception data as a result.

The clock reproduction section 22 is composed of a clock reproduction phase detection section 24, an LPF 26 and a voltage controlled oscillation circuit 28. The clock reproduction phase detection unit 24 detects and determines an oscillation phase control error, that is, a clock phase in the voltage control oscillation circuit 28 from the outputs of the detectors 20I and 20Q, and outputs a voltage according to the result. LPF26 is
The output voltage of the clock recovery phase detector 24 is low pass filtered. The voltage controlled oscillator circuit 28 oscillates in a phase according to the output voltage of the clock reproduction phase detector 24 given through the LPF 26, and supplies the oscillation output to the detectors 20I and 20Q as a determination clock. If the timing of the judgment clock is deviated from the ideal timing (the position of the signal point), the code cannot be judged appropriately. Therefore, the clock reproduction by the clock reproduction unit 22, especially the detection / judgment operation by the clock reproduction phase detection unit 22 is properly performed. It is important to do so.

FIGS. 4 and 5 show the flow and timing of the operation of the conventional clock recovery phase detector 24, taking 16QAM demodulation as an example. This prior art is a modification and application of the technology described in Japanese Patent No. 2949996, so refer to that patent for details. Here, the parts related to the present invention will be briefly described.

In this prior art, not only a threshold value for code judgment but also a threshold value having an intermediate value therebetween is used. In FIG. 5, thresholds (1), (3), and (5) are thresholds for code determination. The threshold (2) for detecting the delay / advance is the threshold (1) and the threshold (3)
Similarly, the threshold value (4) for detecting the delay / advance is a threshold value having an intermediate value between the threshold value (3) and the threshold value (5). The modulation method assumed here is 16
QAM, and in 16QAM, the I and Q component values can take four values (for example, +3, +1, -1, -3) (4 x 4 = 16), so the code determination threshold value is (1 ), (3), and (5) are required, and the phase determination threshold value (described later) is these three types of code determination threshold values and the delay / advance detection threshold value (2), which is in between. (4)
There will be five, including and.

Further, in this prior art, the clock recovery phase detecting section 24 shows the demodulated signal value at the timing (hereinafter referred to as "intermediate timing") located in the middle of the adjacent determination timings on the time axis. It is determined whether the clock phase is advanced or delayed by comparing with the threshold value, and the control voltage of the voltage controlled oscillator circuit 28 is generated according to the result.
In the example shown in FIG. 5, rising timings t1, t3, t5, t7 ... )
/ 2, t6 = (t5 + t7) / 2 ... Is used as the intermediate timing.

As shown in FIG. 4, the clock recovery phase detector 24 fetches and holds the demodulated signal values at the determination timing and the intermediate timing that sequentially arrive (40).
1). The clock reproduction phase detection unit 24 obtains the code determination value by comparing the demodulated signal value at the determination timing with the code determination threshold value (402). The clock recovery phase detector 24 further sets the threshold value (1) based on the determination values at two determination timings adjacent to each other on the time axis.
From (5) to (5), a threshold value, that is, a phase determination threshold value, which is a comparison partner of the demodulated signal value at the intermediate timing sandwiched by these two determination timings, is selected (403). The clock recovery phase detection unit 24 compares the demodulated signal value at the intermediate timing with the selected phase determination threshold value, and determines the determination value change tendency between two adjacent determination timings sandwiching the intermediate timing. By combining the results, it is detected whether the determination timing is advanced or delayed with respect to the position of the signal point on the time axis, that is, whether the clock phase is advanced or delayed (4
04). The clock recovery phase detection unit 24 adjusts the clock phase according to the result so that the detected phase advance / delay is canceled out.
Generate a control voltage for.

Taking the demodulated signal waveform shown in FIG. 5 as an example, the judgment values at the judgment timings t1, t3, t5, t7 ... Become "+3""-3""-1""+3". Therefore, the phase determination threshold values for the intermediate timings t2, t4, t6 ... Are “+3” and “−”, respectively.
The threshold value (3) located in the middle of "3", "-3" and "-"
Threshold value (5) located in the middle of "1", "-1" and "+"
The threshold value (2) is located in the middle of "3". The demodulated signal values at the intermediate timings t2, t4, t6 ... Are respectively larger than the threshold value (3), smaller than the threshold value (5) and smaller than the threshold value (2). Further, the change in the judgment value from the judgment timing t1 to t3, t3 to t5, t5 to t7 ... Is decreasing, increasing, and increasing in order. In step 404, since the change in the judgment value between the judgment timings t1 and t3 before and after that is negative and the demodulated signal value is larger than the phase judgment threshold value, it is judged to be "advance" at the intermediate timing t2. Also, the determination timing t before and after that
Since the change of the judgment value between 3 and t5 is positive and the demodulated signal value is smaller than the phase judgment threshold value, it is judged as "advance" at the intermediate timing t4. The same logic is used to determine “advance” for the intermediate timing t6. That is, the positive / negative sign of the change in the judgment value between the judgment timings and the positive / negative sign of the demodulation signal value at the intermediate timing with respect to the phase judgment threshold value are “advance”, and if they are the same, “delay”. judge.

[0010]

As described above, according to the conventional technique described in the above-mentioned patent, the threshold value determination for the demodulated signal value at the intermediate timing and the determination between the determination timings sandwiching the threshold value determination are performed. By detecting the value increase / decrease tendency and making a logical judgment based on the result, the advance / delay of the clock phase is discriminated and detected. However, in this method, if the number of signal points is large, the number of threshold values becomes large and it becomes difficult to judge “advance” or “delay” as follows. However, there are problems in that it is unavoidable and the characteristic deterioration due to amplitude gain error and center signal level offset cannot be avoided.

The example given above is 16QAM as the modulation method.
Therefore, it is sufficient to prepare a total of five types of phase determination threshold values including three types of code determination threshold values and two types of delay / advance detection threshold values between them. However, in general, when considering 2 ⁿ QAM (n: a natural number of 2 or more), for each of the I and Q components, there are n−1 types of code determination threshold values and n−2 types of delay / advance between them. There are 2n-3 types of phase determination thresholds including the detection threshold. Therefore, as n increases, the number of phase determination thresholds also increases, the number of paths that cross them increases, and the number of conditional branches at the time of phase determination also increases. In addition, even when trying to design a demodulator that is compatible with multiple modulation methods with different numbers and arrangements of signal points, that is, a demodulator with high versatility, the phase determination threshold value is set so that it can support multiple modulation methods. Due to the need to prepare, such designs are difficult or costly in development. Since the code judgment threshold value and the delay / advance detection threshold value in the middle thereof are used as the phase judgment threshold value, the signal for the desired amplitude is detected at the threshold comparison stage in the clock recovery phase detection unit 24. If the amplitude error remains,
Alternatively, if the center signal level offset (deviation of the origin of the IQ plane) remains, an erroneous determination regarding "advance" or "delay" of the clock phase occurs.

By applying the technique disclosed in Japanese Patent Laid-Open No. 9-942229, the determination operation for detecting the clock phase is executed only when the demodulated signal value transition across the center signal level occurs. However, if so, the processing becomes simpler than that of the above-mentioned prior art. However, as is obvious, the frequency of execution of the clock phase detection is reduced, and this demerit becomes remarkable especially when the number of signal points is large. Further, similarly to the above-mentioned prior art, the characteristic deterioration due to the center signal level offset cannot be avoided.

The present invention has been made to solve the above problems, and is suitable and simple irrespective of the number of signal points and without reducing the execution frequency of the clock phase detection operation. It is an object of the present invention to realize a demodulator that can perform clock phase detection in processing, is suitable for general-purpose design, and is less likely to cause characteristic deterioration due to an amplitude error / center signal level offset.

[0014]

In order to achieve such an object, the present invention (1) compensates for a phase error of a decision clock with respect to an input signal being QAM-modulated,
In a clock phase control method for controlling the phase of a decision clock, (2) an input signal value at a plurality of decision timings sequentially given by the decision clock and an input signal at an intermediate timing sandwiched by the plurality of decision timings on the time axis. By inputting a value and (3) calculating a weighted average value of the input signal values at the plurality of determination timings with the load determined according to the time interval of the intermediate timings with respect to the plurality of determination timings, input at the intermediate timings. (4) Positive / negative of the input signal value or the change of the determination value over the plurality of determination timings, and the phase determination threshold of the input signal value at the intermediate timing. If the positive and negative values of and are the same as each other It is determined that the determination clock is delayed with respect to the signal point in the input signal, and is determined to be advanced when they do not match, and (5) the above control is executed according to the result of the determination. To do. As an example, the determination clock is a signal with a duty ratio of 50%. In that case, it is desirable to use two adjacent determination timings on the time axis as the plurality of determination timings, and use a timing positioned exactly in the middle of the two determination timings as the intermediate timing.

Here, in the above-mentioned prior art, the phase determination threshold value is selected from the plurality of threshold values based on the determination values at the plurality of determination timings sandwiching the intermediate timing. That is, the phase determination threshold value in the prior art is determined by "selection", and the selection is based on "determination value". On the other hand, in the present invention, the input signal value at the determination timing and the intermediate timing (corresponding to the demodulated signal value in the above-mentioned conventional technique) is input, and the weighted average of the input signal values at the plurality of determination timings sandwiching the intermediate timing is input. The phase determination threshold value is set by obtaining the value. That is,
The phase determination threshold value in the present invention is determined by the “weighted average” calculation, and the calculation is performed by the “input signal value”.
It is intended for.

As described above, according to the present invention, the phase determination threshold value at the intermediate timing is calculated by the weighted average calculation based on the input signal values at the plurality of determination timings sandwiching the intermediate timing. Since it is set as a threshold that is interlocked / driven with respect to, even if there is an error in the signal amplitude with respect to the expected amplitude or the center signal level offset remains at the stage of threshold comparison,
In principle, erroneous determinations regarding "lead" and "lag" of the clock phase do not occur. In addition, since there is no phase determination condition that depends on the number of signal points, such as it is not necessary to prepare the phase determination threshold value by design, it is possible to support even if the number of signal points (2 ⁿ in 2 ⁿ QAM) is large. The present invention is useful for easily realizing a demodulator capable of handling a plurality of types of modulation methods having different numbers and arrangements of signal points, that is, a demodulator having high versatility. Further, the execution frequency of the clock phase detection is the same as that of the conventional technique shown in FIGS.
The frequency does not decrease as in the case where the technique described in Japanese Patent No. 229 is applied.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. Since the present invention can be carried out under the apparatus configuration shown in FIG. 3, FIG. 3 will be referred to in the following description. Further, for convenience of comparison with the prior art, as shown in FIG. 2, the determination clock and the demodulated signal waveform are shown in FIG.
Assume the same as shown in.

FIG. 1 shows an operation procedure of the clock recovery phase detector 24 in the preferred embodiment of the present invention, and FIG. 2 shows an example of its operation timing. The procedure shown in FIG. 1 is repeated, for example, every time the determination timing arrives.
As shown in FIG. 1, also in the present embodiment, the clock recovery phase detector 24 inputs and holds the demodulated signal values at the determination timing and the intermediate timing that sequentially arrive (101). The clock recovery phase detection unit 24 in the present embodiment calculates the average value of the demodulated signal values at the two determination timings adjacent to each other on the time axis among the held demodulated signal values (102), and then, It is used as a comparison target with the demodulated signal value at the intermediate timing, that is, a phase determination threshold value. For example, in the example shown in FIG. 2, the determination timing t
The average value of the demodulated signal values at 1 and t3 is set as the phase determination threshold value for the intermediate timing t2. Similarly, the average value of the demodulated signal values at the determination timings t3 and t5 is the phase determination threshold value for the intermediate timing t4, and the average value of the demodulated signal values at the determination timings t5 and t7 is the phase determination threshold value for the intermediate timing t6. It is set to each value.

The clock recovery phase detector 24 compares the phase determination threshold value set in this way with the demodulated signal value at the intermediate timing sandwiched by the two determination timings, while the above 2 Detects the demodulated signal value over the individual judgment timings or the increasing / decreasing tendency of the judgment value,
The clock phase is "advanced" by combining the results.
Or "delay" is determined and detected (103). That is, Table 1
As shown in, the sign of the difference between the phase determination threshold value (“threshold value by average value” in Table 1) for the intermediate timing and the demodulated signal value (the “center signal”) at the intermediate timing, and If the sign of the demodulated signal value or the judgment value change (the same “2 signal state transition”) between the two judgment timings sandwiching the intermediate timing coincides, the position of the signal point on the time axis is compared. The determination clock is “delayed”, and conversely, if it is “decreased”, it is determined to be “advanced”. If the demodulated signal value or the change in the determination value over the two determination timings can be said to be “no change”, it is determined to be “hold”. Then, the clock recovery phase detector 24 determines the voltage controlled oscillator 2 according to the result.
A control voltage is supplied to 8. That is, the phase of the determination clock is controlled so that if the determination result is “delayed”, the determination clock is advanced further, and conversely if it is “advanced”, the determination clock is further delayed. If it is "hold", the current oscillation state is maintained.

[0020]

[Table 1] As described above, according to the present embodiment, the phase determination threshold value at the intermediate timing is set by the average calculation based on the demodulated signal values at the plurality of determination timings sandwiching the intermediate timing. Therefore, it is not necessary to previously set the code determination threshold value and the threshold value located in the middle thereof as the phase determination threshold value. Therefore, it is not only possible to easily support a modulation method with more signal points,
It is possible to easily realize a highly versatile demodulator capable of supporting a plurality of modulation methods in which the number and arrangement of signal points are different. Furthermore, since the threshold value set in step 102 is dependent / followed by the value of the actual demodulated signal value, the characteristic error due to the amplitude error of the demodulated signal value and the center signal level offset does not occur. In addition, since the opportunity of clock phase detection is not limited to the occurrence of a symmetrical transition (for example, a transition from +3 to -3), the frequency does not decrease as in the case of applying the technique described in Japanese Patent Laid-Open No. 9-247229. .

In this embodiment, as the average value calculation in step 102, simple average calculation (in other words, weighted average calculation with load = 0.5) is performed. In this way, the reason why the weighted average calculation of weight = 0.5 is performed is that the duty ratio of the determination clock is 50%. When the present invention is implemented in a circuit that uses a clock whose duty ratio is not 50%, it is desirable to determine the load based on the duty ratio. For example, if the duty ratio is ON period / cycle = a [%], the load for setting the phase determination threshold value for an arbitrary intermediate timing is 100 for the determination timing that arrives immediately before the intermediate timing. -A [%], and the determination timing that arrives immediately after is preferably a [%].

The present invention can also be implemented in a demodulator using a decision clock having a frequency N times (N: a natural number of 2 or more) the decision clock shown in FIGS. In FIG. 2, all the rising timings are used as the judgment timings, but when the judgment clock having a frequency N times that is used, the rising timings are used as the judgment timings every N cycles. When using the N-fold frequency determination clock, the rising or falling timing located between the determination clocks is used as the intermediate timing. In this case as well, the load for calculating the phase determination threshold value at the intermediate timing from the demodulated signal value at each determination timing follows the same principle as the load setting according to the duty ratio, and the interval between the determination timing and the intermediate timing. It is desirable to set according to the ratio.

Further, in the above description, the determination timing is based on the rising edge and the intermediate timing is based on the falling edge, but conversely, the determination timing may be based on the falling edge and the intermediate timing may be based on the rising edge.

In addition, as to whether the demodulated signal value transition (“2 signal state transition” in Table 1) between determination timings is “increase” or “decrease”, as described above, the determination values at those determination timings are determined. The determination can be performed by comparing (+3, +1, -1, -3) (difference calculation) or by comparing demodulated signal values (difference calculation) at the determination timings. When the judgment values are compared with each other, the demodulated signal value at the judgment timing is compared with the code judgment threshold values (1), (3) and (5) shown in FIG. Is performed and the judgment value is obtained. When the demodulated signal values are compared with each other, it is determined that there is no change when the difference between the demodulated signal values is equal to or smaller than a predetermined minute value.

The present invention can be implemented by either hardware or software.

[Brief description of drawings]

FIG. 1 is a flowchart showing an operation procedure of a clock recovery phase detecting section in an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the principle of clock phase lead / lag determination in the present embodiment.

FIG. 3 is a block diagram showing a configuration of a demodulator to which the present invention can be applied.

FIG. 4 is a flowchart showing an operation procedure of a clock recovery phase detecting section in a conventional technique.

FIG. 5: Advancement of clock phase in this prior art /
6 is a timing chart for explaining a delay determination principle.

[Explanation of symbols]

22 clock recovery unit, 24 clock recovery phase detection unit, 28 voltage controlled oscillator circuit, t1, t3, t5, t7
Judgment timing, t2, t4, t6 Intermediate timing.

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Claims (2)

[Claims] 1. A clock phase control method for controlling the phase of a decision clock so that a phase error of the decision clock with respect to a QAM-modulated input signal is compensated. Input signals at a plurality of decision timings sequentially given by the decision clock. The value and the input signal value at the intermediate timing sandwiched by the plurality of determination timings on the time axis are input, and the load determined in accordance with the time interval of the intermediate timings with respect to the plurality of determination timings causes the plurality of determination timings to be determined. By calculating the weighted average value of the input signal value, the phase determination threshold value for the intermediate timing is set, and the positive / negative of the change of the input signal value or the determination value over the plurality of determination timings, and the intermediate Determine the phase of the input signal value at the timing The positive and negative of the threshold value are obtained, and when the positive and negative values match each other, it is determined that the determination clock is behind the signal point in the input signal, and when they do not match, it is determined that it is advanced. A clock phase control method, characterized in that the above control is executed in accordance with a result of the determination. 2. The clock phase control method according to claim 1, wherein the determination clock is a signal having a duty ratio of 50%, and the plurality of determination timings are two determination timings adjacent to each other on the time axis, A phase clock control method characterized in that the intermediate timing is a timing located exactly in the middle of these two determination timings.