JP2003299862A - Chip and method for controlling game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip and method for controlling a game machine by which illegal access is made to be difficult. <P>SOLUTION: The chip comprises: a CPU; a storage means; a random number generation circuit for generating the random number of an M sequence system or a counter system; a bit scramble circuit for bit-scrambling the random number outputted from the random number generation circuit; a random number maximum value comparing circuit for comparing the output of the bit scramble circuit with a random number maximum value stored in advance; a random number holding circuit which requests the random number generation circuit and repeats a request for the random number until obtaining a random number value which does not exceed the maximum value when the result of comparing processing by the random number maximum value comparing circuit exceeds the maximum value, and which obtains and holds the random number when it does not exceed the maximum value; and a random number reading circuit in which the random number which is obtained by taking the random number which has been held in the random number holding circuit in the case of a request by external trigger input or the reading request of the random number by a user. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine control chip and a gaming machine control method used for a pachinko gaming machine, a rotating body type gaming machine, or the like.

[0002]

2. Description of the Related Art <General Content> A gaming machine manufacturer sets a constant value, for example, every 2 ms for a central processing unit (hereinafter, abbreviated as "CPU" in this specification) that controls a gaming machine as a measure against runaway of the gaming machine. Reset is input at a cycle, and processing of an interval reset interrupt is executed from the start address of the game program. That is, even if a CPU runaway occurs due to noise or the like, a reset is input to the CPU at the above cycle and the CPU returns to the start address of the game program, so damage caused by the runaway can be minimized. <Plus 1 method> As a random number generation method used for gaming machines, "1" is added to the random number value for each reset interrupt process,
There is a so-called "plus 1 system" that returns to "0" when the maximum value of a predetermined random number range is reached. <Plus-one method by initial value update type> There is also a method by the "plus-one method by initial value update type" in which the initial value is changed every cycle of the random number cycle and "1" is added to the random number value in the same manner. <Random Number Generation by Software> Furthermore, in any of the above methods, random numbers are generated by software.

[0003]

<Problems to be solved by the invention><Problem of plus 1 method> Random number generation by the "plus 1 method" causes regularity in the appearance cycle of the random number value, so that an illegal person (goto act etc.) generates a big hit random number value generation cycle. "Sensors" that aim at and hit the jackpot judgment value, and generate a suspicious winning signal to the winning sensor in accordance with the jackpot occurrence cycle. However, there was a problem of getting a large profit. <Issue of plus 1 method by initial value update type>
In the "plus one method by the initial value update type", the cycle in which the specific random number value appears is more irregular than the "plus one method" due to the change of the initial value, and it is difficult for the "experience sensor" to aim and so on. In the random number generation by, the data is output to the system bus every time the random number is updated, so it is possible to specify the random number sequence and the timing of the initial value update by analyzing the appearance data externally. In any case, it will be possible to aim and hit the jackpot according to the cycle. <Issues of Random Number Generation by Software> Also, a person who creates software or an illicit person who knows the contents by leakage can easily determine the appearance period of a specific random number value if only the timing of updating the random number initial value can be determined. The present invention has been made in view of the problems of the related art. That is, an object of the present invention is to provide a gaming machine control chip and a gaming machine control method that are difficult to be illegally accessed.
Also, by incorporating a random number generator into the gaming machine control chip, it is possible to set whether or not to put a random number on the data bus, and to prevent an illegal person from easily predicting the random number sequence or cycle. .

[0004]

In order to solve such a problem, a gaming machine chip according to the present invention includes a CPU, a storage unit, a random number generation circuit that generates a random number of an M-series method or a counter method, and A bit scramble circuit that bit scrambles the random number output from the random number generation circuit, a random number maximum value comparison circuit that compares the output of the bit scramble circuit with a prestored random number maximum value, and the random number maximum value comparison circuit Makes a request to the random number generation circuit again when the maximum value is exceeded as a result of the comparison process, repeats the random number request until a random number value that does not exceed the maximum value is obtained, and acquires it if it is a random number that does not exceed the maximum value. And a random number holding circuit that holds the random number, and a random number that is fetched when the random number held in the random value holding circuit is requested by an external trigger input or when the user makes a read request for the random number. And a random number reading circuit in which is stored.

The invention of claim 2 is the gaming machine control chip according to claim 1, wherein a random number initial value selection circuit for selecting a random number initial value from a predetermined number of values, and the random number generation circuit. From the random number generation circuit, the random number initial value of the random number generation circuit is rewritten by the random number initial value selection circuit, and the random number generated by the random number generation circuit makes one round of the random number initial value. Each time, the auxiliary random number value generated by the auxiliary random number generating means is used as the initial value.

A third aspect of the present invention is the gaming machine control chip according to the second aspect, wherein the random number initial value selection circuit selects a random number initial value stored in a ROM as an option to select as a random number initial value. It includes a constant, a fixed value specific to the random number generator, a predetermined value of the random number generator, an ID number of the gaming machine control chip, a RAM value or a RAM operation value.

A fourth aspect of the present invention is the gaming machine control chip according to the first aspect, wherein a random number update trigger for selecting a trigger condition for update control of the random number generation circuit from among several predetermined trigger conditions. It further has a selection circuit and an update control circuit for controlling the start, continuation, and end of updating these trigger conditions.

A fifth aspect of the present invention is the gaming machine control chip according to the first aspect, wherein the bit scramble circuit performs a process of exchanging bits according to a bit scramble table prepared in advance.

According to a sixth aspect of the present invention, in the gaming machine control chip according to the fifth aspect, the scramble processing in the bit scramble circuit prepares a plurality of bit scramble tables and executes bit swapping in a plurality of stages. Is.

According to a seventh aspect of the present invention, in the gaming machine control chip according to the fifth aspect, the plurality of bit scramble tables include a random number round end signal from a random number generation circuit and a bit scramble from a bit scramble request circuit. This is to randomly exchange arbitrary bits based on the request and the random number from the auxiliary random number generating means.

The invention of claim 8 is the gaming machine control chip according to claim 1, further comprising: a random number value request circuit for reading the random number stored in the random number value reading circuit, The timing required by the numerical value request circuit can be selected from a plurality of trigger conditions.

The gaming machine control according to the present invention is a gaming machine control method using a gaming machine control chip, which is a random number generating step of generating a random number of an M series system or a counter system, and is output from the random number generating circuit. A bit scrambling step that applies bit scrambling to the random number
A random number maximum value comparison step of comparing the output of the bit scramble circuit with a previously stored random number maximum value, and the random number maximum value comparison circuit requests the random number generation circuit again when the comparison result exceeds the maximum value. Repeat the random number request until a random value that does not exceed the maximum value is obtained, and if the random number does not exceed the maximum value, obtain and hold it, and hold the random value held in the random value holding circuit. And a random number reading step in which a random number fetched when a request by an external trigger input or a user makes a random number reading request is stored.

The invention of claim 10 is the gaming machine control method according to claim 9, further comprising a random number initial value selection step of selecting a random number initial value from among a predetermined number of values, The random number initial value in the random number generating step is rewritten in the random number initial value selecting step, and the random number initial value is stored in the auxiliary random number generating means independent from the random number generating circuit every time the random number generated by the random number generating circuit makes one cycle. The generated auxiliary random number value is used as an initial value.

The invention of claim 11 is the gaming machine control method according to claim 10, wherein a ROM is selected as an option selected as the random number initial value in the random number initial value selection step.
The random number initial value selection constant stored therein, a fixed value unique to the random number generator, a predetermined value of the random number generator, an ID number of the gaming machine control chip, a RAM value or a RAM calculation value are included.

The invention of claim 12 is the gaming machine control method according to claim 9, wherein a random number update trigger for selecting a trigger condition for update control of the random number generation step from among several predetermined trigger conditions It further includes a selection step and an update control step for controlling the start, continuation, and end of updating these trigger conditions.

A thirteenth aspect of the present invention is the gaming machine control method according to the ninth aspect, wherein the bit scrambling step is a process of exchanging bits according to a bit scrambling table prepared in advance.

A fourteenth aspect of the present invention is the gaming machine control method according to the thirteenth aspect, wherein the scramble processing in the bit scramble circuit prepares a plurality of bit scramble tables and executes bit swapping in a plurality of stages. Is.

A fifteenth aspect of the present invention is the gaming machine control method according to the thirteenth aspect, wherein the plurality of bit scramble tables include a random number round end signal from the random number generation step and a bit scramble from the bit scramble request step. This is to randomly exchange arbitrary bits based on the request and the random number from the auxiliary random number generating means.

The invention of claim 16 is the gaming machine control method according to claim 9, further comprising a random number value requesting step for reading the random number stored in the random value reading step, The timing requested by the numerical value request step is selectable from a plurality of trigger conditions.

The invention described in claim 17 is the invention according to claim 1.
The gaming machine control chip described above, further comprising a clock generation means and a runaway monitoring means, the runaway monitoring means counting a time-out time based on a signal from the clock generation means, and the time-out time elapses. Then, a time-out signal is generated, and the CPU receives the time-out signal to generate a reset, and the program is re-executed from the reset address of the user program.

The invention described in claim 18 relates to claim 1.
The gaming machine control chip described in 7, wherein the timeout time can be changed.

The invention described in claim 19 is the invention according to claim 1.
In the gaming machine control chip described in 1), illegal execution prohibiting means is further provided to prohibit opcode fetch from an illegal address.

The invention described in claim 20 is the same as claim 1
The gaming machine control chip described in 1., which has an ID number unique to each chip.

The invention described in claim 21 is the invention according to claim 1.
In the gaming machine control chip described in (1), the parallel input / output port is also used as an external chip select signal.

According to the invention described in claim 22,
The gaming machine control chip described in 1., further comprising security means for executing a security check and stopping the CPU according to the authentication result.

The invention described in claim 23 is the first aspect.
It is possible to set whether or not to put the random number on the data bus in the gaming machine control chip.

According to a twenty-fourth aspect of the present invention, there is provided a gaming machine control chip used in a gaming machine, wherein the gaming machine control chip authenticates a CPU, a storage unit, and a program, and is written in the storage unit. And an authentication check control means for stopping the CPU when the authentication code is illegal.

According to a twenty-fifth aspect of the present invention, there is provided a gaming machine control chip for use in a gaming machine, wherein the gaming machine control chip is a CPU, a storage means, and an illegal execution for prohibiting instruction execution outside a designated area. It has prohibition means and illegal execution prohibition control means for controlling the illegal execution prohibition means.

According to a twenty-sixth aspect of the present invention, there is provided a gaming machine control chip used in a gaming machine, wherein the gaming machine control chip has a CPU, a storage means, a program mode, a security mode, a user mode and the like. And a mode control means for controlling.

A twenty-seventh aspect of the present invention is a gaming machine control chip used in a gaming machine, wherein the gaming machine control chip includes a CPU, a storage means, a bus / signal line control, and C.
PU stop control, random number failure diagnosis function control, and ROM read / write function control function control means.

The invention described in claim 28 is the invention according to claim 2
7. A gaming machine control chip according to 7, further comprising a random number generator, which enables control of shutting off random numbers generated by the random number generator from the outside of the chip by the function of the function control means. is there.

According to a twenty-ninth aspect of the present invention, there is provided a gaming machine control chip used in a gaming machine, wherein the gaming machine control chip is a CPU, a storage means, a storage means control means for performing device disconnection and memory bank switching. And ,.

According to a thirtieth aspect of the present invention, there is provided a gaming machine control method using a gaming machine control chip, wherein a timeout count step for counting a timeout time based on a signal from the clock generation means, and the timeout count step. And a reset signal generating step of generating a reset when the CPU receives the time-out signal generated in the time-out signal generating step, when the time-out time counted in 1 has elapsed, a time-out signal generating step of generating a time-out signal, And a program re-execution step for re-executing the program from the reset address of the program based on the reset signal generated in the reset signal generation step.

The invention described in claim 31 is the same as claim 3
In the gaming machine control method described in 0, the timeout time can be changed.

According to a thirty-second aspect of the present invention, there is provided a gaming machine control method using a gaming machine control chip, wherein the illegal execution monitoring step monitors whether or not an instruction is executed outside a predesignated address range. When an illegal execution is detected in the illegal execution monitoring step, an IAT signal generating step for generating an illegal address trap (IAT) signal and a reset signal are generated based on the IAT signal generated by the IAT signal generating step. And a reset signal generating step for generating the reset signal.

According to a thirty-third aspect of the present invention, there is provided a gaming machine control method using a gaming machine control chip, comprising a function selecting step of selecting a function of a parallel input / output port and an external chip select signal, and respective input / output. And an input / output control step for controlling the above.

According to a thirty-fourth aspect of the present invention, there is provided a gaming machine control method using a gaming machine control chip, wherein an ID number unique to the chip, a predetermined value possessed by a random number generation device, and a secret while executing a normal game. External input / output request signal acquisition step of acquiring a signal for extracting information, data stored in a designated area to the outside, and an ID number unique to the chip, a predetermined value possessed by a random number generator while executing a normal game , A secret information, and a data output step of outputting the data stored in the designated area to the outside.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail according to the illustrated embodiments.

<Outline Description of Form of Chip> The gaming machine control chip according to the present invention is configured as an integrated circuit mounted on a substrate inside the gaming machine. There are a development chip and a mass production chip as the classification of the chip type. The mass production chip and the development chip will be described with reference to FIG. The development chip is a chip that does not have a security judgment function, and has the same functions as the mass production chip except for the above. The mass-production chip has a security judgment function for judging whether or not the program stored in the built-in storage means is an appropriate one that has passed the test by a third-party organization.

<Outline of Mass-Production Chip> The mass-production chip has a user ROM that cannot be erased and rewritten by the user, and as shown in FIG. If there is a mismatch, the CPU is stopped. In addition, due to the out-of-designated area travel prohibition function, the program cannot be executed in a range other than the set address range (that is, an address range indicating outside the designated area).

<Outline of Development Chip> The development chip is a user R that can be erased and rewritten by the user.
The OM is provided, and as shown in FIG. 8B, the mode shifts to the user mode regardless of the result of the security check. Further, even in the function of prohibiting traveling outside the designated area, there is no limit to the address range that can be set (the address range indicating the designated area), so that the user can freely develop and debug. Here, the user is
A game machine maker that manufactures and sells a game machine control chip according to the present invention by incorporating it into a game machine.

<Operation Mode> What is the operation mode? CPU
This mode controls basic operations such as operation control, memory mapping, and access rights to various registers built into the chip. There are a security mode, a user mode, and a program mode.

<Security Mode> In this mode, the storage means for booting is executed and the environment setting and security check of each function are performed. During the security mode, the internal bus during CPU operation is not output to the external terminal.

<Security Check> This is a function for authenticating a user program. When the system reset is input, recalculate whether the authentication code calculated based on the user program is correct. If the result is NG, CP
Stop U. The authentication code is written together with the user program when it is written in the storage means for the user.

<User Mode> In this mode, a regular user program that has passed the security check is executed. If the security check in the security mode does not become "OK", this mode will not be entered. During the user mode, the internal bus during CPU operation is output to the external terminal as an external bus. The boot storage unit cannot be accessed during the user mode.

<Program Mode> In this mode, the CPU does not operate and the read / write is directly performed to the user ROM. After the system reset, this mode is entered by a predetermined level (for example, high level) of the PRG terminal.
Note that the mass-production chip can be written only once, and the development chip can be erased and rewritten.

Each functional block built in the gaming machine control chip of the present invention will be described with reference to FIG. In FIG. 9, c1 is a CPU. For example, Zilog Z80 or Motorola 68HC11, or compatible software compatible C.
PU or the like can be used.

<Timer System> c2 of FIG. 9 is a timer system. The timer system incorporates n (for example, 4) n-bit (for example, 8 or 16 bits) counters and various control registers, and can operate in independent modes. For example, the modes are roughly classified into a timer mode, a counter mode, and the like, and as functions for specifically realizing these modes, (1) interval timer function, (2) event count function, (3) one-shot output function, ( 4) PWM function (pulse width modulation function), (5) pulse width measurement function, (6) time difference measurement function, etc. are provided, and it is possible to perform real-time interrupt generation and time measurement. These functions described above can be controlled by setting various control registers in the timer system. Further, it is provided with a timer input bus for inputting a gate signal or a trigger signal for realizing the above function and a timer output bus for outputting various timer output signals generated by the timer system to the outside.

C3 in FIG. 9 is an unauthorized execution prohibition means. The illegal execution prohibiting means monitors whether or not the user program created by the game machine maker is correctly executed in a predetermined designated area, and resets when the user program is executed outside the designated area. For example, when the entire memory space is 64 kbytes, in the setting of the specified area (address range where the user program can be executed), the start address of the range is 0 as the program code start address (PCS) and the end address is the program code end. Address (hereinafter PC
If EFF is 1FFF (hexadecimal), 200
Even if an illegal program is stored and executed in the range of 0 (hexadecimal) to FFFF (hexadecimal), it cannot be executed. That is, the illegal execution prohibition means is a function of prohibiting instruction execution outside the designated area, and when an instruction is executed (opcode fetch) outside the address range (designated area) designated in advance, IAT (Illegal).
This is a function of generating an Address Trap) signal. This IAT signal causes a reset. The information in this designated area is the R for user along with the user program
Write to OM.

Reference numeral c4 in FIG. 9 is a runaway monitoring means. The configuration of the runaway monitoring means c4 will be described in more detail with reference to FIG. The runaway monitoring means c4 includes a clock selection means c4a, an n-bit counter c4b, and a runaway monitoring control means c.
4c, operation mode control means c4d, control word setting means c4e, and output control means c4f. The runaway monitoring means c4 generates a time-out signal. This time-out signal causes a reset. Further, by various settings of the operation mode control means c4d and the control word setting means c4e, (1) setting / changing of the timeout time,
(2) Count clear & restart, (3) Operation permission /
It is possible to set prohibition, etc.

The runaway monitoring means c4 is automatically activated when shifting to the user mode, and generates a timeout signal when the timeout time has elapsed. By receiving this time-out signal, a user reset is generated and the user program is re-executed from the reset address (for example, address 0) of the user program.

<Clock Selector> Clock Selector
c4a is the system sent from the clock generation means c9.
Each divided clock including system clock CLKO / m ⁰・ ・
・ CLKO / mⁿN bit counter by selecting one of
To be sent to.

<N-bit Counter> The n-bit counter c4b counts the timeout time based on the divided clock sent from the clock selecting means c4a.

<Runaway Monitoring Control Unit> The runaway monitoring control unit c4c performs control for setting a timeout time, prohibiting operation of the n-bit counter, clearing, restarting, and the like.

<Operation Mode Control Means> The operation mode control means c4d can select the count clock for setting the timeout time, control the operation permission / prohibition, and change the timeout time. Note that once the timeout time is changed, it may not be changed until the system is reset.

<Control Word Setting Means> The control word setting means c4e sets clearing and restarting of the timeout time, and operation prohibition. For example, by writing a control word (for example, CC (hexadecimal)) in the control word setting means c4e, the runaway monitoring means is disabled. This setting may be enabled only once after the system is reset. 55 (Hex) → AA (Hex) → 33 (Hex)
The time-out time can be extended by clearing and restarting (starting counting again). It is not necessary to write the control word continuously for 3 bytes.

<Explanation of Operation of Runaway Monitoring Unit> The runaway monitoring unit c4 is automatically activated by shifting to the user mode. The timeout time is set by the operation mode control means c4d, and the default value is set to the longest timeout time. Settings can be set only once after a system reset, and resetting cannot be done without a system reset. When the time-out is reached, the output control means c4f outputs a time-out signal, and the runaway monitoring means c
The operation of 4 is continued as it is.

Next, the reset / interruption control means c5 shown in FIG. 9 will be described with reference to FIGS. 13 shows an internal block diagram of the reset / interrupt control means, FIG. 14 shows a timing chart example of a system reset, FIG. 15 shows a timing chart example of a user reset, and (a) is a timing chart example by an XURST terminal. , (B) is an example of a timing chart when a time-out signal or an IAT signal is generated, and FIG. 16 shows an example of a timing chart of an interrupt.

<Reset / Interrupt Control Means> The reset / interrupt control means c5 controls various resets, and external interrupt requests and interrupt requests from a built-in peripheral circuit (timer system).

<System Reset> This is a reset generated by inputting a low level for a certain period to the XSRST terminal. All the internal circuits including the CPU are initialized, and the mode shifts to the security mode or the program mode according to the input level of the PRG terminal. If there is no abnormality in the security mode, the mode is shifted to the user mode and the user program is executed from the reset address (for example, address 0) of the user program. Further, the system reset signal supplied to the CPU and each internal circuit is XSR as a reset signal to an external device outside the chip.
It is output to the outside from the STO terminal.

<User Reset> Next, user reset will be described. The factors of the user reset are a user reset request by the XURRST terminal, a user reset request by the SC terminal abnormality of the external input / output means c14, a terminal check request, a reset request by the IAT generation of the illegal execution prohibiting means c3, and a runaway monitoring means c4. There may be a user reset request due to a timeout or a user reset request due to a mode trigger from the mode control means of the security means c10.

<Operation of User Reset> When a user reset occurs and the user reset is accepted, the CP
U, the timer system c2, and the input / output means c7 are initialized, and the execution of the user program is started from the reset address (for example, address 0). (User reset does not shift to security mode or program mode.)

<Non-Maskable Interrupt (NMI)>
Next, the non-maskable interrupt will be described. The non-maskable interrupt (NMI) is an interrupt that is unconditionally accepted even in the interrupt disabled state of the CPU, and is processed with the highest priority for all interrupt requests. The non-maskable interrupt from the XNMI terminal is input to the CPU via the noise filter c5a. FIG. 16 is an example of a timing chart showing the relationship between before and after passing through the noise filter c5a. When the XNMI signal is at the low level for a certain period (here, while detecting the rising edge of 4 clocks), the signal passed through the noise filter c5a becomes the NMI signal and is input to the CPU.

<Maskable Interrupt (INT)> The maskable interrupt (INT) is an interrupt that enables / disables acceptance of an interrupt request by a user program.
Multiple interrupts can be executed by the INT priority control circuit c5d.

<External Maskable Interrupt> The external maskable interrupt is generated by inputting a low level for a certain period to the XINT terminal, and the maskable interrupt from the XINT terminal is input to the CPU via the noise filter c5a. FIG. 16 is an example of a timing chart showing the relationship between before and after passing through the noise filter c5a. When the XINT signal is at the low level for a certain period (here, while detecting the rising edge of 4 clocks), the signal passed through the noise filter c5a is IN.
It becomes a T signal and is input to the CPU.

<Internal Maskable Interrupt> The internal maskable interrupt is generated by an interrupt request signal from the timer system.

<Decoding Means> Decoding Means c6
Is a memory-mapped I / O system, I / O-mapped I / O
It is possible to perform decoding by the method, and to decode each functional block inside the chip and a chip select signal which is a decoding signal for an external device. Further, it is possible to set the address range of the chip select signal. Taking the chip select signal as an example, the chip select signal by the memory mapped I / O method is shown in FIG.
Mapped to F00 (hexadecimal) to FF19 (hexadecimal), and the chip select signal according to the I / O mapped I / O method is mapped to 00 (hexadecimal) to 19 (hexadecimal) in FIG. 11B. It is shown that. Since there are a plurality of chip select signals, they are collectively referred to as an external output bus in this specification for convenience.

<Input / Output Means> The input / output means c7 controls the function of the input / output port and the chip select signal which is a decoding signal for the external device.
It comprises a function selecting means c7a and (2) input / output control means c7b. The input / output control means c7a includes (a) parallel input / output ports (a plurality of input / output ports having different arbitrary bit widths are built in, and input / output of each port can be set), and (b) external device decoding. It has two functions. Any one of the functions is selected by the function selecting means c7a to perform input / output with the outside. As a result, the external terminal functions as either the state of the input / output port bus or the external output bus.

<Clock Generating Unit> The clock generating unit c9 is a clock input terminal (corresponding to the EX terminal in FIG. 2).
It is a circuit that divides the clock input from the CPU with an arbitrary division ratio (for example, divide by 2) and supplies the divided clock to the CPU and each internal circuit. Further, the generated clock is output to the outside from the clock output terminal (corresponding to the CLKO terminal in FIG. 2). In addition, the clock source source (s
3) is supplied to the random number generator c8.

<Security Means> The security means c10 is (1) authentication check control means, (2) unauthorized execution prohibition control means, (3) mode control means, (4) function control means, (5) storage means control means. It consists of 5 means.

<Authentication Check Control Unit> The authentication check control unit has a function of authenticating the user program (UP). At the time of system reset input, whether or not the authentication code calculated based on the user program is correct is recalculated, and if the result is NG, the CPU is stopped. The authentication code is written in the storage means together with the user program at the time of writing.

<Unauthorized Execution Prohibition Control Means> The unauthorized execution prohibition control means is a function of prohibiting instruction execution outside the designated area. (A) Instruction execution prohibition outside the designated area,
(B) Program execution prohibition on RAM (both external / internal), (c) reset control, and (d) program execution monitoring control in a designated area.

<Mode Control Means> The mode control means controls three modes: (a) program mode, (b) security mode, and (c) user mode.

<Function Control Means> The function control means is
(A) Bus / signal line control, (b) CPU stop control,
(C) Random fault diagnosis function control, (d) user ROM read / write function control.

<Storage Means Control Means> The storage means control means performs (a) device disconnection and (b) memory bank switching.

Next, the storage means c11 will be described with reference to FIGS. FIG. 10 shows a specific example diagram of the memory map of the entire chip, FIG. 11 shows a specific example diagram of the area in the user ROM, (a) is a specific example diagram of the program management area, and (b) is I / I. FIG. 9 is a diagram showing a specific example of a decode area of an internal register and an external output bus according to the O-mapped I / O system.

<Storage Unit> The storage unit c11 stores the ID
The storage means c11a, the boot storage means c11b, and the user storage means c11c are included.

<ID Storage Means> ID Storage Means c11
a includes (a) test date, (b) manufacturing date, (c) manufacturing location, (d) manufacturing plant, (e) manufacturing line, (f) manufacturing lot, and (g) manufacturing. Number, (h) user management number, (i) serial number, etc., some of the information data can be stored as n different types of ID numbers. 10 million pieces) and distribution can be managed. In addition to the ID number, secret information, which is information that can be specified by only a chip manufacturer / seller unknown to a third party or a user, is stored. As a concrete example of confidential information,
There may be detailed information on material management (wafer management number, etc.) and code numbers for cooperating factories.

<Boot Storage Means> The boot storage means c11b is composed of (a) boot ROM and (b) boot RAM, and (a) boot ROM includes:
The (a) security check program, (b) failure diagnosis program, (c) environment setting program, (d) collation program, etc. are stored. Further, (b) the boot RAM is used as a work area (data area, stack area, etc.) of the boot program.

<User Storage Means> The user storage means c11c is composed of (a) user ROM and (b) user RAM.

<User ROM> User ROM
Is a program created by the user (user program)
To store. The user ROM has a predetermined designated area, and is assigned with two areas: (a) program code / data area and (b) program management area. (A) The program code / data area is an area for storing a user program. (B)
The program management area is an area for storing information necessary for the CPU to execute the user program, and the user sets the value. The size of the user RAM (for example, 256/512 bytes) is also selected in this area.

<Data Set in Program Management Area> As shown in FIG. 11, the data set in the program management area includes (1) “header (HDR)” (sets a code string indicating the start of the program management area). As an example, 1F80 (hexadecimal) to 1F87 (hexadecimal) is mapped), (2) “Maker code (MCD)” for setting the manufacturer code (1F88 (hexadecimal) to 1F as an example)
8A (hexadecimal), (3) "Product code (PCD)" for setting the product code (1F8B (1
(Hexadecimal) to 1F92 (hexadecimal)), (4) Set the final address of the program code area of the user program "Program code end address (PC
E) ”(for example, 1F93 (hexadecimal) to 1F94 (16)
(RAM)), (5) "RAM size selection (RSS)" for setting the size of user RAM (1F as an example)
95 (mapped to hexadecimal), (6) "terminal function selection" (1 as an example) for setting whether to use the terminal as a parallel I / O port or chip select for an external device
F96 (hexadecimal), (7) “Select random number initial value” to set random number initial value (1F97 (16
(8)), (8) "random number initial value data address" that sets the address of the designated user RAM value when selecting the random number initial value (1F as an example)
98 (hexadecimal) to 1F99 (hexadecimal)),
(9) User RA read by an external device (collating device, etc.)
There is a "read RAM address" for setting the M address (mapping to 1FA0 (hexadecimal) to 1FBF (hexadecimal) as an example).

<User RAM> User RAM
Is the user program work area (data area,
Used as a stack area). The RAM size can be changed (for example, 512/256 byte switching, etc.) according to user settings. The user RAM has a backup function. When the backup function is used, data in the RAM can be saved even after the power (V ⁺ ) of the chip is cut off by supplying another power supply between the V _BB terminal and the GND terminal. Can be retained (backed up).

<Memory Monitoring Unit> The memory monitoring unit c12 in FIG. 9 is a circuit for monitoring RAM writing. The storage monitoring means c12 monitors the contents and writing of the storage means.
In the security mode, the address range of a predetermined storage means is set as the monitoring range.

<Bus / Signal Line Control Means> The bus / signal line control means c13 is an interface function between the external bus and the internal bus of the chip and an address bus, a data bus,
And a bus interface that strengthens the direction control and drive capability of each control signal. Each terminal is internally pulled up / down.

<Description of Each Terminal> The address bus specifies an address for data transmission / reception with a memory or an I / O device. The data bus transmits and receives data. X
M1 indicates a machine cycle. XMREQ is a request signal to the memory space and indicates a memory access period. XIORQ is a request signal to the I / O space and indicates an access period of the I / O space. XRD indicates a read cycle. X
WR indicates a write cycle. XRFSH
Is a refresh signal to a dynamic memory or the like outside the chip. XHALT is a signal indicating the state where the CPU is executing the HALT instruction. During the halt state, the state that the instruction is not executed is held. The halt state is released by a reset signal or interrupt, and the CPU operation is restarted. To do.

<External Input / Output Means> The external input / output means c14 shown in FIG. 9 is for connecting an external device (a collation device or the like) to this chip and inspecting the authenticity of this chip. This chip monitors the SC terminal and the BRC terminal, waits for authentication with an external device when a signal such as a clock is supplied to the BRC terminal, and when a predetermined signal is received from the SC terminal, the received signal is received. Performs authentication control for signals. The random number generator c8 also performs a process of checking the random numbers output from the random number generator c8.

<Random Number Generator> The random number generator c8 of FIG. 9 will be described with reference to FIGS. 1 to 7.

The random number generator c8 will be described with reference to FIG. FIG. 1 is a block diagram showing a circuit configuration of random number generation. The update cycle setting data holding circuit 1 is a circuit for holding setting data for designating an interval cycle for the user to update a random number at an arbitrary interval cycle, and is a reference interval for designating a reference interval cycle. It is composed of a cycle designating circuit 1a and a fixed cycle set value storage circuit 1b which carries out settings for designating an interval cycle for actually updating a random number based on the interval cycle serving as a reference. The data designated by the circuit 1 is loaded into the update cycle setting circuit 2.

The update cycle setting circuit 2 is a circuit that sets an interval cycle for updating a random number at a fixed cycle.
A reference interval cycle generation circuit 2a for generating a reference interval cycle corresponding to the data specified by the reference interval cycle specification circuit 1a, and a fixed cycle set value based on the reference interval cycle clock supplied from the circuit 2a. A reference interval cycle counting circuit 2b for counting the reference interval cycle based on the count data number specified by the storage circuit 1b, and an interval cycle when the count data number specified by the fixed cycle set value storage circuit 1b is reached. Of the reload timing generation circuit 2c for generating the reload timing for designating the update / continuation. Therefore, the interval cycle set by the update cycle setting circuit 2 is supplied to the random number update trigger selection circuit 6.

For example, assuming that the divided frequency of the system clock is the reference interval period (provisionally I),
The clock divided based on the data designated by the reference interval period designating circuit 1a (for example, the data designating 128 division) becomes the reference interval period. If the setting range that can be specified by the fixed cycle set value storage circuit 1b is 8 bits, the settable interval cycle for updating the random number in the actual fixed cycle is "128 x system clock x 1 to 128 x system clock x It is possible to set an interval period of "up to 256". If the set value specified in the fixed cycle set value storage circuit 1b is "5", this set value is similarly loaded into the reload timing generation circuit 2c, and the circuit reaches "128 x system clock x 5". In that case, the reload timing for renewing and continuing the interval cycle is supplied to the reference interval cycle counting circuit 2b.

The software update trigger generation circuit 3
A software trigger signal is generated by write-accessing data (address, data generated by decoding predetermined data, etc.) combining predetermined conditions in accordance with an instruction from the CPU.

The operation start instruction circuit 4 is for specifying the stop, restart, continuous operation, etc. of the random number update operation.

The random number update trigger selection information holding circuit 5
In updating the random number value, an automatic update method using an interval cycle for updating the random number at a fixed cycle generated by the update cycle setting circuit 2 or a software trigger signal generated by the software update trigger generation circuit 3 is used. One of the methods of using the manual update method to be used is selected.

The random number update trigger selection circuit 6 selects one of the interval cycle clock generated by the update cycle setting circuit 2 and the software trigger signal generated by the software update trigger generation circuit 3. It is supplied to the update control circuit 7.

The update control circuit 7 controls operations such as stopping, restarting, and continuing the random number updating operation.

The random number generation circuit 8 has a plurality of n-th order generator polynomials or n-bit counters for generating different random number sequences according to predetermined settings.

The bit scramble setting circuit 9 exchanges or transposes the bits of the random number data output from the random number generation circuit 8, and the bit scramble request circuit 9a, the bit scramble key generation circuit 9b, and the bit scramble circuit 9c. Composed. The bit scramble request circuit 9a is a circuit that specifies a request to scramble the random number data output from the random number generation circuit 8 at the timing updated by the update unit selected by the random number update trigger selection circuit 6. The bit scramble key generation circuit 9b is for arranging and transposing random number data based on the auxiliary random number for generating the bit scrambling key generated by the auxiliary random number generating means 19 and the data value from the bit scramble request circuit 9a. This is a circuit for selecting a bit scramble table. The bit scramble circuit 9c is a bit scramble key generation circuit 9b.
It is a circuit for arranging and transposing the bits of random number data based on the bit scramble table selected by the key data specified by. It should be noted that the user can freely set whether to scramble by the bit scramble request circuit 9a, but the bit scramble key is changed by the random number cycle end signal S1 output from the random number generation circuit 8. Bit scramble request circuit 9
Even if there is the bit scramble request signal S2 output from a, if the random number round end signal S1 does not exist, the bit scramble key is not changed. This makes the probability of each round of random numbers constant.

The random number maximum value storage circuit 10 is a circuit for storing the maximum value of the random number cycle arbitrarily set by the user. For example, if the random number generation range is from 1 to 4095, and if the user only needs a random number from 1 to 36, a random number from 1 to 36 can be obtained by setting 36 as the maximum value in the circuit 10. Is.

The random number maximum value comparison circuit 11 compares the maximum value of the random number cycle arbitrarily set by the user with the output value obtained by bit scrambling the random number value generated by the random number generation circuit 8 by the bit scramble circuit 9c, and outputs the result. When the value is larger than the maximum value, the random number generation circuit 8 is instructed to generate the next random number. If it is less than the maximum value, it is stored in the random number holding circuit 12.

The random number holding circuit 12 holds the scrambled random number data when the value is equal to or less than the maximum value of the random number cycle arbitrarily set by the user. That is, it is a circuit that holds random number data until the maximum period is reached.

The random number value request circuit 13 is a request for the user to read random number data, and may output a request by an external trigger input or information when the request is made to the outside as an interrupt signal. It is possible.

The random value reading circuit 14 is a circuit for the user to read random number data.

The ROM program management area 15 is
The random number initial value selection constant 15a is an area for designating the operating environment set by the user to specify the operation and control of the random number generator of the present invention, which is the first start value for generating a random number sequence. When it is desired to use the data stored in a predetermined RAM address as the initial value of a random number sequence to be generated, the data is used as the random number initial value selection circuit 17
RAM addressing 15b intended to be sent to
Composed of and. When the random number initial value is selected as the RAM value in the initialization program, the RAM value at the address indicated by the RAM address designation is stored in the random number initial value selection circuit 17.

The software operation 16 refers to an operation for updating a random number and performing a control for loading a predetermined initial value. The software operation 16 has a fixed value 16a, which is a value that the random number generation device of the present invention itself has, ID number 16 which is a unique number assigned to the random number generator of the invention for recognizing itself
b, R which is the value designated by RAM address designation 15b
A RAM that is a value that has undergone arithmetic processing such as addition / subtraction / multiplication / division based on the AM value 16c and data at all addresses in the RAM.
It is composed of a calculated value 16d and a RAM 16e which is a data area for controlling the program.

The ID number 16b is the above-mentioned ID.
This is the same as the chip ID number stored in the storage means c11a. The chip ID described above uniquely identifies the chip itself, and the ID number of the random number generator sets the initial value of the random number for each chip.
Therefore, the difference between the two is only the difference in specifications, and the actual ID numbers of the two may be different or may be the same, and it does not matter at all. Therefore, paragraph number 007
It is possible to use some of the information data (a) to (i) shown in 8 as ID numbers for random number initial values. The random number initial value selection circuit 17 uses the fixed value 16a as the random number initial value,
ID number 16b, RAM value 16c, RAM calculation value 16d
1 is selected to load the initial value into the random number generation circuit 8.

The random number initial value storage circuit 18 is a circuit for storing an initial value selected by the random number initial value selection circuit 17 or a random number generated by the auxiliary random number generating means 19 as an initial value. The random number initial value can be updated by the random number initial value storage circuit 18 from the auxiliary random number generating means 19 every time the random number value generated by the random number generating circuit 8 makes a round.

The auxiliary random number generating means 19 is a means for generating random numbers by means different from the present random number generating device.

Next, random number generation will be described with reference to FIG. 2 is a block diagram showing an outline of the auxiliary random number generating means 19, (1) when there is no external trigger input bus (see FIG. 9), and (2) when there is an external trigger input bus (see FIG. 17). Is shown. As generation means, (a) random number generation by command control of CPU, (b) random number generation by thermal noise, (c) random number generation by another clock,
(D) 4 of random number generation by trigger input from outside the chip
Including two cases.

The random number generation by the instruction control of the CPU in (a) is performed by the instruction (the instruction execution number counting circuit 2) executed by the CPU.
The data obtained by counting the information (retained in 1)) is used as a random number.

The random number generation by thermal noise of (b) uses noise components such as thermal noise generated from resistors and diodes as random numbers, and is generated from the thermal noise generation circuit 22 including these thermal noise generators. The analog noise component
The digital data converted by the / D conversion circuit 23 is used as a random number.

(C) Random number generation by another clock is to generate a random number by a clock different from the clock used in this random number generator.

(D) The random number generation by the trigger input from the outside of the chip is to generate the random number by the trigger input arbitrarily set by the user.

These (a), (b), (c),
The random number generated by the method (d) is supplied to the bit scramble key generation circuit 9b or the random number initial value storage circuit 18 as a random number initial value. The supply method is a combination of the above (a), (b), (c) and (d) as appropriate.

In (c) above, the counter circuit has two
If the external trigger input bus of (1) does not exist as the clock to be supplied to 5, the clock source source (s3) having a frequency division ratio different from that of the clock to be supplied to each functional block is supplied from the clock generation means c9, and (2) If there is an external trigger input bus of 1), a clock different from the EX terminal is supplied from the OSC terminal. As a clock to be supplied, in order to avoid synchronization with a predetermined interval period, for example, a different frequency (for example, 11 MHz) different from the frequency (for example, 12 MHz) supplied to the EX terminal is supplied. Needless to say, it is also good.

Next, random number generation will be described with reference to FIG. FIG. 3 is a specific explanatory diagram of the bit scramble setting circuit 9 of the random number generator. The bit scramble table is a bit scramble table showing a pattern of bit replacement (hereinafter, for convenience, a “conversion table” or a “conversion pattern”). May be abbreviated)
And the arrangement of bits based on this conversion table
The transposed position is determined. For example, the data length is 8 bits, and the original arrangement is D0-D1-D2-D3-in order from the least significant bit.
If it is D4-D5-D6-D7, (1) D0-D1-D2-D3-D4-D5-D6-D
7 (2) D3-D0-D5-D1-D7-D2-D4-D
6 Omitted description from (3) to (255). (256) D7-D5-D2-D4-D1-D6-D0
If you take into account things that do not perform the original conversion, such as -D3, 25
There are six conversion patterns. A schematic image of this situation is shown in FIG.

However, if the conversion pattern is realized by hardware instead of software, the circuit scale becomes large and the number of gates increases.

Therefore, the bit scramble setting circuit 9 of the present invention makes it possible to secure 256 conversion patterns without decreasing the number of gates by increasing the number of conversion tables by reducing the number of conversion tables.
3 (b) is a characteristic image of the principle of FIG. The principle will be described below, but for convenience, the data length is 8 bits.

First, 16 conversion tables are generated by KEY_A (4 bits) of the bit scramble key generation circuit 9b. That is, the first 16 conversion patterns are individually the original patterns. (Tentatively O1 to O16)

Next, the 16 original patterns are individually converted by KEY_B (2 bits). That is, from (O1 × 4 ways) to (O1
Since the added value is up to 6 × 4), a total of 64 conversion patterns are realized. Therefore, similarly to the above, each of the 64 conversion patterns becomes the original pattern. (Tentatively OH1 to OH4)

Next, similarly to the above, 64 patterns are individually converted by KEY_C (2 bits). That is, since the added value is from (OH 1 × 4 ways) to (OH 4 × 4 ways), as a result of the final summation, 256 actual conversion patterns are realized.

Therefore, although 256 conversion tables were originally required, only 24 conversion tables were prepared by the above method, and 256 conversion patterns were substantially realized, and the circuit scale was small. Become.

Further, since the logic circuit of the conversion pattern of the above method can be designed only by the gate circuit without using the shift register, the processing speed for exchanging the next conversion pattern is one cycle of the system clock operating the gaming machine. I don't need it.

FIG. 4 is a block diagram showing the internal configuration of the update cycle setting data holding circuit 1 and the update cycle setting circuit 2.

Next, the operation of the random number generator will be described in order according to the general flow shown in FIG.

FIG. 5 is a flowchart showing an initialization routine process for setting environment settings for the random number generator to perform a desired operation. When a system reset for initializing the entire gaming machine is input, as a random number initial value to be used first, (1) a fixed value of the random number generator, (2) an ID number of the random number generator, (3) RAM value, (4 After selecting the RAM operation value to be used and setting the environment for the initialization process of the internal circuits of the random number generator, etc., the mode is changed to the user mode in which the user can use and waits for user reset. Note that the user reset does not initialize the above process.

Next, description will be made with reference to the outline flow of FIG. FIG. 6 is a flow chart showing an operation setting process for the user to freely read a random number after the random number generator completes the initialization process shown in FIG. When a user resets each peripheral device connected and inputs a user reset to return to the start address of the game control program created by the user, a fixed cycle for the interval operation is activated. The update trigger condition is set whether to use the update at a fixed cycle or the manual update (update by the software). When the manual update is set, the random number update is performed by the software update trigger. Next, when it is judged whether it is the timing for reading the random number such as the start sensor input of the game machine and using the acquisition trigger by software, the random number value holding circuit is accessed and the random number value held in the random number value holding circuit is taken in and disturbed. It is loaded into the numerical reading circuit. After that, the user performs application operations such as lottery processing based on the read random numbers.

Next, description will be made with reference to the outline flow of FIG. FIG. 7 shows an example of a flowchart of random number updating and random number reading processing of the random number generator. (A) is a random number updating processing by automatic updating (constant cycle) and manual updating (software), and (b) is an external trigger. 3 is a flow showing a random number reading process by a capture trigger by software.

When the random number is updated, the bit scramble table indicated by the bit scramble key data is used to perform bit scrambling of the random number value. When the random number value is within the maximum value, the random number value is stored in the random value holding circuit, and the maximum value is stored. If it exceeds, the random number is updated again. Next, it is judged whether or not the generation of random numbers has completed one cycle, and if there is a cycle, it is judged whether or not there is a request to change the bit scramble. If there is a request, update processing of the bit scramble key data is performed. To do.

It should be noted that taking in a random number value means a process of whether or not the generated random number is sent from the random number holding circuit 12 to the random value reading circuit 14 accessible by the user. When a random number update trigger with a fixed cycle is used, the random number value is fetched automatically. Whether the user uses (1) the random number values automatically and continuously generated by the update cycle setting circuit by selecting whether or not to perform the process of capturing the random number value (2) at any time It is possible to select the preference of game play whether the updated and read random number value is used.

Therefore, in order to actually obtain a random number, the user can obtain the random number value generated by the present random number generation device by accessing the random number value request circuit 13.

Further, the user can freely change the setting of the operation designating condition each time the user reset is input.
The (1) maximum value setting and (2) update trigger condition setting cannot be changed once they have been set.

Next, Embodiments 2 and 3 will be described with reference to FIGS. Embodiment 2
Is almost the same as the configuration of FIG. 9 showing the embodiment of the present invention, but in FIG. 9, a dedicated signal (s3) is input from the clock generation means c9 to the random number generator c8. In the configuration of FIG. 17, the random number generator c8 has an input trigger input bus for receiving a trigger signal from the outside of the chip, and an OSC terminal for supplying a different clock in addition to the EX terminal. It is possible to incorporate a trigger, a random number request trigger, an auxiliary random number request trigger, etc. from the outside.

In the third embodiment, the external output control means 2 is further added.
0 is provided, and the random number data output from the random number holding circuit 12 is sent to the external input / output means c14 by a switch operated by software, and FIG. 18 shows a circuit configuration functional block diagram of random number generation showing the third embodiment. Is shown. A switch operated by software is one that cannot be accessed or operated by the user. For example, a signal obtained by encrypting a command or control sequence by a predetermined algorithm is input to the external input / output unit c14.
It is activated when the CPU recognizes the signal.
When this switch is activated, the random number data of the random number holding circuit 12 is sent to the external input / output means c14 in real time regardless of the winning state or the gaming state of the chip. That is, all the generated random number data will be output, and the uniformity of the appearing random numbers can be checked by a third party organization.

Note that the random number value is usually read in a timely manner at the timing when the random number is needed, so the updated content of the random number and the random number sequence are not output to the external bus. However, if it becomes necessary to output all the random number values to the data bus for inspection, every time the software update trigger is used, if the CPU reads the random number data of the random number value reading circuit 14, all the random number values will be obtained. It becomes possible to output to the data bus. Figure 1
9 shows a flowchart of the random number reading process and the random number output process of the random number generator regardless of the winning state.

Further, since the random number output from the random number maximum value comparison circuit 11 is not directly connected to the data bus, the random number data does not get on the data bus each time it is updated unlike the above and software random numbers. . That is, the update control is automatically performed on the bus in the random number generator, regardless of the read instruction or read cycle of the CPU. Therefore,
The update timing of this random number and the arrangement of the random number sequence (mathematical expression for generating the random number sequence) cannot be predicted by an illicit person.

[0137]

EFFECTS OF THE INVENTION (1) In updating the initial value of a random number,
Allows the user to select multiple random number update trigger conditions,
Further, by using the ID number for each gaming machine control chip, it becomes possible to have irregularity in the generation of random numbers and different random number sequences for each model / table of the gaming machine manufacturer. (2) Since the M-series or counter type random numbers are adopted,
It is possible to generate uniform random numbers. (3) Since the random number generator is built in the game machine control chip by hardware and built-in, by controlling not to output the update timing to the system bus, the random number generated in the random number generation circuit can be changed. Update timing is not output to the outside. Therefore, it becomes impossible for an illegal person to predict the period in which the random number appears. (4) Since the random number maximum value storage circuit is provided, the user can arbitrarily set the maximum period of the generated random numbers. (5) Since the random number update trigger selection circuit and the update control circuit are provided, the random number update timing can be set by the user. Further, since the trigger other than the random number update timing by the user's arbitrary setting is also adopted, the random number can be generated without depending only on the user setting. (6) By providing the bit scramble circuit, the generated random numbers can be scrambled. Further, by providing the bit scramble key generation circuit and using a plurality of tables, it becomes possible to change the setting of the scramble method for each cycle (one cycle) of the random number.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of random number generation.

FIG. 2 is a block diagram showing a specific example of auxiliary random number generation means 19.

FIG. 3 is a conceptual explanatory diagram showing a configuration of a bit scramble table.

FIG. 4 is a block diagram showing an internal configuration of an update cycle setting data holding circuit 1 and an update cycle setting circuit 2.

FIG. 5 is a flowchart showing an initialization routine process for setting environment settings for the random number generator to perform a desired operation.

FIG. 6 is a flowchart showing an operation setting process in which the random number generation device allows the user to freely read a random number after the initialization process of FIG. 5 is completed.

FIG. 7 shows a flowchart of random number updating and random number reading processing of the random number generator.

FIG. 8 is an operation mode transition diagram of the chip.

FIG. 9 is a functional block diagram of the entire chip.

FIG. 10 is a specific example diagram showing a memory map of the entire chip.

FIG. 11 is a specific example diagram showing an area in a user ROM.

FIG. 12 is a block diagram of a runaway monitoring means.

FIG. 13 is a block diagram of reset / interruption control means.

FIG. 14 is an example of a system reset timing chart.

FIG. 15 is an example of a user reset timing chart.

FIG. 16 is an example of an NMI and INT interrupt timing chart.

FIG. 17 is a functional block diagram of the entire chip when an external trigger input is possible according to the second and third embodiments of the present invention.

FIG. 18 is a functional block diagram of a circuit configuration of random number generation showing a third embodiment of the present invention.

FIG. 19 is a flowchart showing a random number reading process and a random number output process of the random number generator irrespective of the winning state according to the present invention.

[Explanation of symbols]

1 update cycle setting data holding circuit 1a reference interval cycle specifying circuit 1b constant cycle set value storage circuit 2 update cycle setting circuit 2a reference interval cycle generating circuit 2b reference interval cycle counting circuit 2c reload timing generating circuit 3 software update trigger generating circuit 4 operation Start instruction circuit 5 Random number update trigger selection information holding circuit 6 Random number update trigger selection circuit 7 Update control circuit 8 Random number generation circuit 9 Bit scramble setting circuit 9a Bit scramble request circuit 9b Bit scramble key generation circuit 9c Bit scramble circuit 10 Maximum random number storage Circuit 11 Random value maximum value comparison circuit 12 Random value holding circuit 13 Random value request circuit 14 Random value reading circuit 15 ROM program management area 15a Random initial value selection constant 15b RAM address designation 16 Software operation 16a Fixed value 16b ID number 16c RAM value 16d RAM operation value 16e RAM 17 Random number initial value selection circuit 18 Random number initial value storage circuit 19 Auxiliary random number generation means 20 External output control means 21 Instruction execution number counting circuit 22 Thermal noise generation circuit 23 A / D conversion circuit 25 Counter circuit 26 External trigger control means S1 Random number cycle end signal S2 Bit scramble request signal S3 Clock source source S4 having a frequency division ratio different from the clock supplied to each functional block R1 output data c1 CPU which cannot be accessed by the user c2 timer system c3 illegal execution prohibiting means c4 runaway monitoring means c4a clock selecting means c4b n bit counter c4c runaway monitoring control means c4d operation mode control means c4e control word setting means c4f output control means c5 reset / interrupt control means c5 Noise filter c5b OR (or) circuit c5c extension circuit c5d INT priority control circuit c6 decoding means c7 input / output means c8 random number generator c9 clock generation means c10 security means c11 storage means c12 storage control means c13 bus / signal line control means c14 External input / output means

Claims (34)

[Claims] 1. A gaming machine control chip used in a gaming machine, wherein the gaming machine control chip comprises a CPU, a storage means, a random number generation circuit for generating random numbers of M-sequence type or counter type, and the random number generation. A bit scramble circuit that bit scrambles the random number output from the circuit, a random number maximum value comparison circuit that compares the output of the bit scramble circuit with a prestored random number maximum value, and a random number maximum value comparison circuit If the result of the processing exceeds the maximum value, the random number generation circuit is requested again, the random number request is repeated until a random number value that does not exceed the maximum value is obtained, and if it is a random number that does not exceed the maximum value, it is acquired and held. And a random number holding circuit that stores the random number held in the random number holding circuit when the user makes a request by an external trigger input or when the user makes a request to read the random number. It includes a random number reading circuit to be stored, the gaming machine control chip and executes the game program based on the random number stored in the random number reading circuit. 2. The gaming machine control chip according to claim 1, wherein the random number initial value selection circuit selects a random number initial value from a predetermined number of values stored in the storage means, and the random number. An auxiliary random number generating means independent of the generating circuit is further provided, wherein the random number initial value of the random number generating circuit is rewritten by the random number initial value selecting circuit, and the random number initial value is a random number generated by the random number generating circuit. A gaming machine control chip, wherein an auxiliary random number value generated by the auxiliary random number generating means is set as an initial value every time the setting is performed. 3. The gaming machine control chip according to claim 2, wherein the random number initial value selection circuit selects the random number initial value as a random number initial value, the random number initial value selection constant stored in the storage means, and the random number. A fixed value unique to the generator, a predetermined value of the random number generator, an ID number of the gaming machine control chip,
A gaming machine control chip including a RAM value or a RAM calculation value of the storage means. 4. The gaming machine control chip according to claim 1, further comprising: a random number update trigger selection circuit for selecting a trigger condition for update control of the random number generation circuit from among several predetermined trigger conditions. A gaming machine control chip further having an update control circuit for controlling the start, continuation, and end of update of trigger conditions. 5. The gaming machine control chip according to claim 1, wherein the bit scramble circuit performs a process of exchanging bits according to a bit scramble table prepared in advance. 6. The gaming machine control chip according to claim 5, wherein the scrambling process in the bit scrambling circuit prepares a plurality of bit scrambling tables and executes bit swapping in a plurality of stages. Machine control chip. 7. The gaming machine control chip according to claim 5, wherein the plurality of bit scramble tables generate a random number cycle end signal from a random number generation circuit and a bit scramble request and auxiliary random number generation from a bit scramble request circuit. A gaming machine control chip, which randomly executes arbitrary bit replacement based on a random number from a means. 8. The gaming machine control chip according to claim 1, further comprising a random value request circuit for reading the random number stored in the random value read circuit, wherein the random value request circuit requests The gaming machine control chip is characterized in that the timing to be selected can be selected from a plurality of trigger conditions. 9. A gaming machine control method using a gaming machine control chip, comprising: a random number generating step of generating a random number of an M series method or a counter method; and a bit for the random number generated in the random number generating step. A bit scramble step for scrambling, a random number maximum value comparison step for comparing the output of the bit scramble step with a pre-stored random number maximum value, and a comparison processing by the random number maximum value comparison step, when the maximum value is exceeded. Request the random number generation circuit again, repeat the random number request until a random number value that does not exceed the maximum value, and if the random number does not exceed the maximum value, obtain and hold the random number value holding step; The random number held in the holding step is the random number that was fetched when a request was made by an external trigger input or when the user issued a random number read request. Game machine control method and a game execution step of executing a game program based on pay random number reading step and the random number stored in the random number reading step. 10. The gaming machine control method according to claim 9, further comprising a random number initial value selection step of selecting a random number initial value from a predetermined number of values, the random number of the random number generation step. The initial value is rewritten in the random number initial value selecting step, and the random number initial value is an auxiliary random number value generated by an auxiliary random number generating means independent from the random number generating circuit every time the random number generated by the random number generating circuit makes one cycle. A method for controlling a gaming machine, wherein is set as an initial value. 11. The gaming machine control method according to claim 10, wherein the random number initial value selection step selects as a random number initial value, a random number initial value selection constant stored in a ROM, and the random number generation. A fixed value unique to the device, a predetermined value of the random number generator, an ID number of the gaming machine control chip,
A gaming machine control method comprising a RAM value or a RAM calculation value. 12. The gaming machine control method according to claim 9, wherein a random number update trigger selection step of selecting a trigger condition for update control of the random number generation step from among some predetermined trigger conditions, and further these. A gaming machine control method further comprising an update control step for controlling start, continuation, and end of update of trigger conditions. 13. The gaming machine control method according to claim 9, wherein the bit scrambling step performs a process of exchanging bits according to a bit scrambling table prepared in advance. 14. The gaming machine control method according to claim 13, wherein in the scrambling process in the bit scrambling step, a plurality of bit scrambling tables are prepared and a plurality of stages of bit swapping are executed. Machine control method. 15. The gaming machine control method according to claim 13, wherein the plurality of bit scramble tables generate a random number round end signal from the random number generation step and a bit scramble request and auxiliary random number generation from the bit scramble request step. A gaming machine control method characterized by randomly performing arbitrary bit replacement based on a random number from the means. 16. The gaming machine control method according to claim 9, further comprising a random number value requesting step for reading the random number stored in said random number value reading step, The gaming machine control method, wherein the requested timing can be selected from a plurality of trigger conditions. 17. The gaming machine control chip according to claim 1, further comprising a clock generation means and a runaway monitoring means, wherein the runaway monitoring means is based on a signal from the clock generation means and has a timeout time. Counting, and when a time-out time has elapsed, a time-out signal is generated, the CPU receives the time-out signal to generate a reset, and the program is re-executed from the reset address of the program. Chips. 18. The gaming machine control chip according to claim 17, wherein the timeout time is changeable. 19. The gaming machine control chip according to claim 1, further comprising: illegal execution prohibiting means to prohibit opcode fetch from an illegal address. 20. The gaming machine control chip according to claim 1, wherein the gaming machine control chip has an ID number unique to each chip. 21. The gaming machine control chip according to claim 1, wherein the parallel input / output port is also used as an external chip select signal. 22. The gaming machine control chip according to claim 1, wherein a security check is performed, and a CP is obtained based on an authentication result.
A gaming machine control chip, further comprising security means for stopping U. 23. The gaming machine control chip according to claim 1, wherein it is possible to set whether or not to put the random number on a data bus. 24. A gaming machine control chip used for a gaming machine, wherein the gaming machine control chip authenticates a CPU, a storage means, and a program, and an authentication code written in the storage means is illegal. An authentication check control means for stopping the CPU, and a gaming machine control chip. 25. A gaming machine control chip used for a gaming machine, the gaming machine control chip comprising a CPU, a storage means, an illegal execution prohibiting means for prohibiting instruction execution outside a designated area, and the illegal execution. A gaming machine control chip comprising: unauthorized execution prohibition control means for controlling the prohibition means. 26. A gaming machine control chip used in a gaming machine, wherein the gaming machine control chip comprises a CPU, a storage means, and a mode control means for controlling modes such as a program mode, a security mode, and a user mode. A gaming machine control chip having. 27. A gaming machine control chip for use in a gaming machine, wherein the gaming machine control chip comprises a CPU, a storage means, a bus / signal line control, a CPU stop control, a random number fault diagnosis function control, and a ROM read. A gaming machine control chip having: a function control unit for controlling a writing function. 28. The gaming machine control chip according to claim 27, further comprising a random number generator, wherein the random number generated by the random number generator is shut off from the outside of the chip by the function of the function control means. A gaming machine control chip that enables control. 29. A gaming machine control chip for use in a gaming machine, the gaming machine control chip comprising: a CPU, a storage means, and a storage means control means for performing device disconnection and memory bank switching. Chips. 30. A game machine control method using a game machine control chip, comprising: a time-out count step for counting a time-out time based on a signal from a clock generation means; and a time-out time counted in the time-out count step. When time elapses, a time-out signal generating step for generating a time-out signal, a reset signal generating step for generating a reset by the CPU receiving the time-out signal generated in the time-out signal generating step, and a reset signal generating step And a program re-execution step for re-executing the program from the reset address of the program based on the generated reset signal. 31. The gaming machine control method according to claim 30, wherein the timeout time can be changed. 32. A gaming machine control method using a gaming machine control chip, comprising: an unauthorized execution monitoring step of monitoring whether an instruction is executed outside a predesignated address range; and an unauthorized execution monitoring step. When fraudulent execution is detected in
IAT generating an illegal address trap (IAT) signal
A gaming machine control method comprising: a signal generating step; and a reset signal generating step of generating a reset signal based on the IAT signal generated by the IAT signal generating step. 33. A gaming machine control method using a gaming machine control chip, comprising a function selecting step of selecting a function of a parallel input / output port and an external chip select signal, and an input / output controlling step of controlling each input / output. And a gaming machine control method comprising: controlling the combined function. 34. A game machine control method using a game machine control chip, wherein a chip unique ID number, a predetermined value of a random number generator, secret information, and a designated area are stored while a normal game is executed. External input / output request signal acquisition step of acquiring a signal for extracting the data, and an ID number unique to the chip, a predetermined value of the random number generator, secret information, and a designated area while performing a normal game. A data output step of outputting the stored data to the outside, and a gaming machine control method.