CN201489524U

CN201489524U - Code integrity check circuit

Info

Publication number: CN201489524U
Application number: CN2009201342852U
Authority: CN
Inventors: 郭小强; 黄洋
Original assignee: Shenzhen State Micro Technology Co Ltd
Current assignee: Shenzhen State Micro Technology Co Ltd
Priority date: 2009-07-29
Filing date: 2009-07-29
Publication date: 2010-05-26
Anticipated expiration: 2019-07-29

Abstract

The utility model discloses a code integrity check circuit which comprises a system bus, a flash memory, a real-time integrity checking unit, an one-time programmable memory, a DMA controller and a CPU, wherein the lash memory, the real-time integrity checking unit, the one-time programmable memory, the DMA controller and the CPU are all connected on the system bus; and the integrity checking unit is connected with the DMA controller. The code integrity check circuit has the advantage of high safety.

Description

The code integrity checking circuit

Technical field

The utility model relates to field of information security technology, is specifically related to a kind of code integrity checking circuit.

Background technology

General data integrity verifying method mainly is the dynamic data of verification, for example, 1. some message transmit mechanism in the communication process, before the message that will send, add a bit preamble, or add a CRC16 effect value in the message back, send together with message, receiver makes message synchronization according to bit preamble, judges according to CRC effect value whether the message of sending out makes a mistake; 2. adopt password or non-cryptographic methods to make message related, can verify the source of the whether complete and message of message by this information with a segment information.But the integrality of protection static data is important too, such as the program and the data that are stored in the FLASH flash memory, is the economic interests of protection company, and any illegal distorting all should be under an embargo.

The chip code completeness protection method of prior art, its implementation procedure is mostly as follows:

1. chip internal is all integrated two processors that priority level is arranged, the work that comes dispatch processor by arbitration modules.For example, the chip MCIMX31RM of Freescale Semiconductor Co., Ltd independent research just contains two kinds of processors of CPU and DMA.DMA generally contains a plurality of passages, and each passage can both carry out the transportation processing of data, wherein, is responsible for that passage of code integrity protection, such as passage 0, and CPU can not visit its control, and controls it by special code integrity holding circuit.Passage 0 has the highest priority, and when each passage of CPU and DMA during simultaneously to moderator application system bus, passage 0 can be taken bus control right earlier.

2. to needing the code section of effect, calculate summary with certain HASH algorithm, for example (,) the SHA1 algorithm, then summary being stored in the chip internal place of safety, the CPU visit must be forbidden in this place of safety.

3. use a timer to regulate the ratio that DMA and CPU take system bus.

Yet, in the prior art, only support the SHA1 algorithm, cause security not high.

The utility model content

The purpose of this utility model is to provide a kind of safe code integrity holding circuit.

The utility model provides a kind of code integrity checking circuit, it comprises system bus, flash memory, real-time completeness check unit, disposable programmable memory, dma controller and CPU, described flash memory, real-time completeness check unit, disposable programmable memory, dma controller and CPU are connected on the described system bus, and described realization completeness check unit is connected with described dma controller.

More excellent, described realization completeness check unit comprises the algorithm controls module, algoritic module, time-sequence control module, DMA configuration module and house dog, described algorithm controls module is connected to described algorithm stores module, time-sequence control module, DMA configuration module and house dog respectively, and described DMA configuration module is connected to described dma controller.。

More excellent, described algoritic module comprises SHA1 and two kinds of HASH algorithms of SHA256.

Compared with prior art, the utility model has increased the SHA256 algorithm in algoritic module, has higher security; The RTIC designated lane is carried out individual processing, completely cut off the visit of CPU fully the RTIC designated lane; Result register provides with register and pointer mode, uses more flexible; Dma operation is packaged into instruction type, and is integrated convenient.

Description of drawings

Fig. 1 is the system chart of code integrity holding circuit.

Fig. 2 is the workflow diagram of the real-time completeness check unit among Fig. 1.

Embodiment

As shown in Figure 1, code integrity checking circuit of the present utility model system comprises system bus and is connected to flash memory (Flash Memory) on the system bus, completeness check unit (Real Time Integrate Check in real time, RTIC), disposable programmable memory (One Time Programmable, OTP), dma controller, CPU.Flash memory is deposited protected content (instruction and data that CPU carries out), and dma controller is system's general purpose controller.OTP is the permanent storage of a writable disposable in the sheet, is used for depositing critical datas such as key, generally configures when dispatching from the factory, and the user can not change.The RTIC unit is used to check whether the content in the flash memory is distorted by unauthorized user.

The RTIC unit comprises the algorithm controls module, algoritic module, time-sequence control module, DMA configuration module and house dog.The algorithm controls module is connected to algorithm stores module, time-sequence control module, DMA configuration module and house dog respectively.Each functions of modules is described below:

The algorithm controls module is a RTIC unit controls part, has the result relatively, error handling processing, the functions such as issue of dma controller operational order, it comprises following 11 kinds of instructions altogether: treat the effect content be transported to SHA1256 message registration device, to algoritic module put initial value, obtain the algoritic module initial value, give algoritic module result register initialize, starting algorithm module begin computing, evaluation algorithm module whether computing finish, construct that message fills that content obtains that final digest, DMA remove that locking, chained list control to bus transferred, empty transmission, end chained list; The DMA configuration module is connected to dma controller, and the enforcement of control dma controller operational order, when program run, at set intervals, the RTIC designated lane that the DMA configuration module can be controlled dma controller is carried part and is treated the effect content from MEMORY, carry out a HASH computing; Algoritic module can be carried out SHA1 and two kinds of HASH algorithms of SHA256; Time schedule controller is used to regulate the time scale that DMA and CPU take bus; Whether house dog is used to monitor the dma controller operational order and finishes at the appointed time.

As shown in Figure 2, the workflow of RTIC unit is as follows:

In step 100, system power-on reset, dma controller locking bus, through a series of initialization procedures, chained list is transferred the dynamic link table of RTIC unit to, ensuing process is guided by the dynamic link table, the RTIC unit is totally two kinds of working methods, is respectively HASHONCE pattern and RUNTIME pattern, and the HASHONCE pattern is monopolized bus, major function is to check in the vectoring phase whether the content in the storer is modified, and the RUNTIME pattern is DMA and CPU time-division operation.

If what select in step 110 is the RUNTIME pattern, then execution in step 120, and DMA discharges the operation 120 to lock bus, if do not select the then direct execution in step 130 of RUNTIME pattern; In step 130, calculate the HASH value for the treatment of the effect content; In the step 140, relatively whether whether illegally changed by the consistent MEMORY of judgement content with actual value for theoretical value, if treat that the effect content is distorted, then execution in step 150, the generation erroneous resets signal total system that resets; If effect is correct, then execution in step 160, judge whether present mode concludes whether need to continue effect for the RUNTIME pattern; If present mode is the RUNTIME pattern, then get back to step 130, if not RUNTIME pattern, mean that then HASHONCE pattern effect finishes, execution in step 170 checks whether following chained list address register is NULL, if not NULL, execution in step 180 is transferred down the chained list control to the address of opening in the chained list address register; If NULL illustrates that current circuit has only carried out the effect of HASHONCE pattern, and effect finishes, and then execution in step 190, removes the locking of DMA to bus, and finishes chained list.

Safety analysis of the present utility model is as follows:

1. when the disabled user is very difficult can be that DMA is working according to outside Memory IO pin difference, when is that CPU is working, and disabled user's plug-in Memory can't avoid the detection of RTIC unit.

2. the disabled user is difficult to make and carries out single-step debug in any way, has monitored the time that the DMA instruction is transmitted because of the built-in house dog in RTIC unit, and the single-step debug meeting causes that house dog is overflowed and forced system resets again.

3.RTIC use an independent DMA designated lane, other passage of DMA and CPU can not visit it, so the disabled user can't be with the work of CPU or other passage interference of DMA RTIC designated lane.

4. expected result can not be changed after the product issue if be stored among the interior OTP of sheet, and the disabled user can not revise expected result allows the MEMORY of oneself work; Expected result also can be encrypted and be stored among the outside FLASH, but key is stored in the safety disc among the OTP, and the disabled user does not know key, can not be according to own demand change preset value.

Compared with prior art, the utility model has increased the SHA256 algorithm in algoritic module, has higher security; The RTIC designated lane is carried out separately processing, completely cut off the access of CPU to the RTIC designated lane fully; Result register provides with register and pointer mode, uses more flexible; Dma operation is packaged into instruction type, and is integrated convenient.

Claims

1. code integrity checking circuit, it is characterized in that comprising system bus, flash memory, real-time completeness check unit, disposable programmable memory, dma controller and CPU, described flash memory, real-time completeness check unit, disposable programmable memory, dma controller and CPU are connected on the described system bus, and described realization completeness check unit is connected with described dma controller.

2. code integrity checking circuit as claimed in claim 1, it is characterized in that, described realization completeness check unit comprises the algorithm controls module, algoritic module, time-sequence control module, DMA configuration module and house dog, described algorithm controls module is connected to described algorithm stores module, time-sequence control module, DMA configuration module and house dog respectively.

3. code integrity checking circuit as claimed in claim 2 is characterized in that, described DMA configuration module is connected to described dma controller.

4. code integrity checking circuit as claimed in claim 2 is characterized in that, described algoritic module comprises SHA1 and two kinds of HASH algorithms of SHA256.