JP2003298955A - Drive circuit for solid-state image sensor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive circuit of a solid-state image sensor which suppresses a voltage drop caused at the start of power supply to the solid-state image sensor and to provide the drive circuit. <P>SOLUTION: A basic clock generating circuit 1 generates a basic clock signal. A vertical drive pulse generating circuit 2 uses the basic clock signal to produce four vertical drive pulse signals V1 to V4. A vertical driver circuit 4 converts the peak level of the vertical drive pulse signals V1 to V4 into a peak level required for the solid-state image sensor 6. A horizontal drive pulse generating circuit 3 uses the basic clock signal to produce two horizontal drive pulse signals H1 and H2. The horizontal drive pulse signals H1 and H2 are outputted with a frequency half the frequency of the basic clock signal until a prescribed time elapses after the start of power supply and with a frequency equal to that of the basic clock signal after the lapse of a prescribed time. A horizontal driver circuit 5 converts the peak level of the horizontal drive pulse signals H1 and H2 into a peak level required for the solid-state image sensor 6. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for driving a solid-state image pickup device such as a CCD image sensor.

[0002]

2. Description of the Related Art Solid-state image pickup devices represented by CCD image sensors are widely used in electronic cameras and the like. C
In the CD image sensor, the signal charges accumulated in each pixel are vertically transferred according to the vertical transfer clock signal, and after the vertical transfer, are horizontally transferred according to the horizontal transfer clock signal. When an image sensor having a large number of pixels is used for the purpose of improving the image quality of image pickup, the number of signal charges to be transferred and driven increases in accordance with the number of pixels, so that power consumption during transfer and driving increases. Therefore, in an electronic camera that operates with electric power supplied from a battery, a power saving operation is performed by turning on / off the electric power supply to a CCD image sensor and a drive circuit that generates a transfer clock signal as needed. There is.

[0003]

Generally, when the power supply to a circuit is turned on from off, an inrush current flows through the circuit and the power supply voltage temporarily drops. When the power supply voltage is lowered in the CCD image sensor and the driving circuit, the pulse peak value of the transfer clock signal is lowered. The decrease of the pulse peak value makes the transfer operation of the accumulated charges unstable, so that the image quality is deteriorated. In particular, this is likely to cause a problem when the CCD image sensor has a large number of pixels or when the transfer clock frequency is high.

An object of the present invention is to provide a drive circuit for a solid-state image pickup device, which suppresses image quality deterioration that occurs immediately after power supply to the solid-state image pickup device is started.

[0005]

According to a first aspect of the present invention, there is provided a drive circuit for a solid-state image sensor, a clock signal generating circuit for generating a clock signal to be supplied to the solid-state image sensor, and a clock signal generating circuit. A frequency conversion circuit that converts the frequency of the clock signal so as to be low, a time counting circuit that detects that a predetermined time has elapsed from the start of power supply, and a time until the elapse of a predetermined time is detected by the time counting circuit,
The low-frequency clock signal converted by the frequency conversion circuit is supplied to the solid-state image sensor, and the unconverted clock signal is supplied to the solid-state image sensor by the frequency conversion circuit after the elapse of a predetermined time is detected by the timing circuit. By including a clock signal selection circuit, the above-mentioned object is achieved. The frequency conversion circuit may convert the frequency of the clock signal generated by the clock signal generation circuit to ½ lower. The solid-state image pickup device may form an image pickup device of a camera, and the clock circuit in this case can also be formed by a counter. The time required for the counter to count a predetermined value may be the predetermined time. The frequency conversion circuit may be configured by a frequency dividing circuit, and in this case, the clock signal selection circuit may be any one of the clock signal generated by the clock signal generation circuit and the clock signal frequency-divided by the frequency dividing circuit. You may comprise by the selector circuit which selects one. The clock signal includes a horizontal drive pulse signal supplied to the solid-state image sensor, and the frequency conversion circuit in this case can also convert the frequency of the horizontal drive pulse signal. According to another aspect of the present invention, there is provided a drive circuit for a solid-state image sensor, a clock signal generating circuit for generating a clock signal supplied to the solid-state image sensor, and a frequency conversion for converting a frequency of a clock signal generated by the clock signal generating circuit. The above-described object is achieved by including a circuit and a control circuit that controls the frequency conversion circuit so as to change the frequency of the clock signal supplied to the solid-state image sensor from a low frequency to a high frequency. The solid-state image sensor may be configured to start supplying power and a clock signal at the time of outputting the imaging signal, and stop supplying the power and the clock signal at the end of outputting the imaging signal, and the drive circuit further starts supplying the power and the clock signal. It is also possible to provide a time counting circuit that detects that a predetermined time has elapsed from. The control circuit in this case can also control the frequency conversion circuit so as to change the frequency of the clock signal from the low frequency to the high frequency after the elapse of the predetermined time is detected by the clock circuit.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram for explaining a drive circuit for a solid-state image sensor according to a first embodiment of the present invention. Such a drive circuit is used, for example, in an electronic camera. In FIG. 1, the drive circuit has a basic clock generation circuit 1, a vertical drive pulse generation circuit 2, a horizontal drive pulse generation circuit 3, a vertical driver circuit 4, and a horizontal driver circuit 5. The solid-state image sensor 6 is, for example,
It is composed of a CCD image sensor and is driven by vertical drive pulse signals φV1 to φV4 and horizontal drive pulse signals φH1 and φH2 supplied from a drive circuit.
A counter setting value is set in the horizontal drive pulse generating circuit 3 from the counter setting unit of the CPU 7. The counter set value will be described later.

The accumulated charges accumulated corresponding to each pixel of the solid-state image sensor 6 are vertically transferred once by the vertical drive pulse signals φV1 to φV4, and then the horizontal drive pulse signal φ.
H1 and φH2 are horizontally transferred according to the number of pixels forming one horizontal line. The number of pixels that form a horizontal line is, for example, 1000 or more, and may exceed 3000. The number of pixels in the vertical direction (the number of horizontal lines) is, for example, 600 or more, and even more than 2000. The vertical transfer and the horizontal transfer are alternately performed until the accumulated charges corresponding to all the pixels forming the image are output from the solid-state image sensor 6. The signal charge output through such a transfer process is processed as an image pickup signal by a signal processing circuit (not shown).

The solid-state image pickup device 6 and its drive circuit include
Electric power is supplied from the power supply circuit 8. Power supply circuit 8
Performs DC / DC conversion of a voltage input from a battery (not shown) into a voltage required by each circuit, and turns on / off power supply to each circuit by a control signal (not shown) output from the CPU 7. . In the electronic camera of the present embodiment, when the image pickup signal is taken in from the solid-state image pickup device 6, that is, when the solid-state image pickup device 6 outputs the accumulated signal charge, the power supply by the power supply circuit 8 is started to display an image. When the output of all the constituent signal charges is completed, the power supply is stopped. The power supply circuit 8 and the CPU
7 is configured so that power is supplied from a battery when a main switch (not shown) of the electronic camera is turned on.

The present invention is characterized in that the voltage drop that occurs at the start of power supply to the solid-state image pickup device 6 and its drive circuit is suppressed.

In FIG. 1, the basic clock generation circuit 1 is
For example, a basic clock signal having a frequency of 60 MHz is generated. The basic clock signal is the vertical drive pulse generation circuit 2
And the horizontal drive pulse generation circuit 3 respectively. The vertical drive pulse generation circuit 2 divides, delays, and logically synthesizes the basic clock signal to generate four vertical drive pulse signals V1 to V4 for driving a vertical transfer register (not shown) of the solid-state imaging device 6. Occur. The vertical drive pulse signals V1 to V4 have the same frequency but different phases. FIG. 2 is a diagram showing waveform examples of the basic clock signal and the vertical drive pulse signals V1 to V4. Note that the number of vertical drive pulse signals is determined according to the specifications of the solid-state image sensor 6 to be used.

The vertical driver circuit 4 has vertical drive pulse signals V1 to V4 output from the vertical drive pulse generation circuit 2.
Of the vertical drive pulse signals .phi.V1 to .phi.V4 after level conversion of the crest value of the .vertline.
Are output respectively.

The horizontal drive pulse generation circuit 3 uses the basic clock signal to generate two horizontal drive pulse signals H1 and H2 for driving a horizontal transfer register (not shown) of the solid-state image pickup device 6. Horizontal drive pulse signals H1 and H
2 is a signal with the same frequency but opposite polarity. FIG. 3 is a diagram showing a configuration example of the horizontal drive pulse generation circuit 3.

In FIG. 3, the above-mentioned C is displayed on the counter 31.
The counter set value is set from PU7. Counter 3
1 counts the rising edges of the basic clock signal, outputs an H level signal until the count value reaches the counter setting value, and outputs an L level signal after the count value reaches the counter setting value. Is configured to. The output signal of the counter 31 is input to the selection terminal S1 of the selector 35 and the selection terminal S2 of the selector 36 as selection signals of the selectors 35 and 36, respectively.

The inverter 34 converts the H level and the L level of the input basic clock signal and outputs a basic clock signal of opposite polarity. Each of the frequency dividers 32 and 33 divides the input clock signal by ½ and outputs a low speed clock signal of ½ of the input signal frequency (30 MHz in the above example). The basic clock signal is input to the input terminal A1 of the selector 35, and the low speed clock signal is input to the input terminal B1. The reverse polarity basic clock signal is input to the input terminal A2 of the selector 36, and the reverse polarity low-speed clock signal is input to the input terminal B2.

The selector 35 outputs the signal input to the input terminal A1 when the input signal of the selection terminal S1 is L level, and when the input signal of the selection terminal S1 is H level,
The signal input to the input terminal B1 is output. The signal output from the selector 35 is the horizontal drive pulse signal H1.
Is. In the selector 36, the input signal of the selection terminal S2 is L
When it is at the level, the signal input to the input terminal A2 is output, and when the input signal at the selection terminal S2 is at the H level, the signal input to the input terminal B2 is output. Selector 3
The signal output from 6 is the horizontal drive pulse signal H2.

FIG. 4 is a diagram showing waveforms of the basic clock signal and the horizontal drive pulse signal H1. In FIG.
Before the timing t1 when the count value of the counter 31 reaches the counter set value, the low speed clock signal is output as the horizontal drive pulse signal H1. Timing t1
After that, the basic clock signal is output as the horizontal drive pulse signal H1. Similarly, for the horizontal drive pulse signal H2 (not shown), the low-speed clock signal having the reverse polarity is output before the timing t1, and the basic clock signal having the reverse polarity is output after the timing t1.

The horizontal driver circuit 5 level-converts the peak values of the horizontal drive pulse signals H1 and H2 output from the horizontal drive pulse generation circuit 3 into the peak values required by the solid-state image pickup device 6, and after the level conversion. It outputs horizontal drive pulse signals φH1 and φH2.

For example, when a release switch (not shown) of the electronic camera is operated and a release operation signal is input to the CPU 7, the CPU 7 instructs the power supply circuit 8 to start power supply. As a result, the power supply circuit 8 starts supplying power to the solid-state image sensor 6 and the drive circuit for the solid-state image sensor 6. FIG. 5 is a diagram showing waveform examples of the power supply voltage of the drive circuit and the horizontal drive pulse signal φH1 at the start of power supply.
At timing t0 in FIG. 5, when the power supply circuit 8 starts supplying power, the voltage supplied to the drive circuit gradually starts to rise. When the supply voltage exceeds the voltage threshold value at the timing ts, the horizontal drive pulse signal φH1 is output.
Here, the voltage threshold is a minimum voltage required for each circuit to operate.

On the other hand, a rush current flows through the solid-state image pickup device 6 and each circuit constituting this drive circuit when power supply is started. Therefore, as a result of the load current of the power supply (battery) of the electronic camera rapidly increasing, the power supply voltage temporarily decreases as shown by the voltage waveform curve 52. On the other hand, CP
U7 presets the counter set value for the horizontal drive pulse generation circuit 3. The counter setting value is
The count time of the counter 31 is set to continue until the timing t1. That is, it is a value (Z) obtained by dividing the time from the timing ts when the counter 31 starts counting to the timing t1 by the cycle of the basic clock signal. Here, the period from timing ts to timing t1 will be referred to as a counting period.
When the supply voltage exceeds the voltage threshold, the counter 31 reads the counter set value and starts counting.
Therefore, the count start timing is timing t
s.

As described above, the frequencies of the horizontal drive pulse signals φH1 and φH2 are set to ½ of the basic clock signal during the counting period (φH1 waveform 53). If the frequency of the horizontal drive pulse signals φH1 and φH2 is halved, the current flowing through the circuits involved in horizontal transfer can be suppressed to about half. When the circuit current is suppressed, the load on the power supply (battery) due to the start of operation of the solid-state image sensor 6 and this drive circuit is reduced, and the temporary decrease in the power supply voltage is reduced. The voltage waveform curve 52 is a voltage waveform when the CPU 7 sets the counter set value Z and provides a count period. When the voltage supplied to the drive circuit decreases, the peak values of the horizontal drive pulse signals φH1 and φH2 decrease in accordance with the voltage decrease. In the example of FIG. 5, in the φH1 waveform 53, the first pulse crest value after the timing ts decreases slightly.

In order to compare with the case where the counting period is provided, the case where the CPU 7 sets the counter set value to 0 and the counting period is not provided will be described. In this case, the frequencies of the horizontal drive pulse signals φH1 and φH2 are always the frequency of the basic clock signal (φH1 waveform 54). Since the circuit current related to the horizontal transfer cannot be suppressed, the load of the power source (battery) due to the start of the operation of the solid-state imaging device 6 and this drive circuit is heavier than in the case where the above counting period is provided. As a result, the temporary decrease of the power supply voltage becomes large, and the time until the power supply voltage reaches the steady value becomes long. The voltage waveform curve 51 is a voltage waveform when the CPU 7 sets the counter set value to 0. In this case, φH
Timing ts to timing t1 in one waveform 54
From then on, the pulse crest value decreases in a wide range, and the degree of the decrease becomes larger than that of the φH1 waveform 53. Such a decrease in the pulse crest value leads to deterioration in image quality because the transfer operation of the accumulated charges becomes unstable.

The counting period is appropriately set according to the capacity of the power supply (battery) used in the electronic camera, the current consumption of the solid-state image sensor 6 and the drive circuit of the solid-state image sensor 6. When the power (battery) capacity is large and the solid-state image sensor 6 and the current consumption of this drive circuit are small, the count period is shortened (counter set value is reduced). On the contrary, when the power supply (battery) capacity is small and the current consumption of the solid-state imaging device 6 and this drive circuit is large, the counting period may be lengthened (the counter set value may be increased).

According to the first embodiment described above,
The following effects can be obtained. (1) When power supply to the solid-state imaging device 6 and the drive circuit of the solid-state imaging device 6 is started, until a timing t1 at which a temporary decrease in the power supply voltage due to a sudden increase in the load of the power supply (battery) is resolved. During this period, the frequencies of the horizontal drive pulse signals φH1 and φH2 are set to ½ of the frequency of the basic clock signal in the steady state. As a result, the circuit current related to horizontal transfer is suppressed and the load on the power supply (battery) is reduced, so that the temporary decrease in the power supply voltage is reduced and the time until the power supply voltage reaches the steady value is reduced. Shortened. As a result, the period in which the pulse crest values of the horizontal drive pulse signals φH1 and φH2 are reduced is shortened, and the reduction of the pulse crest values is suppressed, so that the deterioration of the image quality can be prevented. Note that the period (counting period) in which the frequencies of the horizontal drive pulse signals φH1 and φH2 are halved may be a predetermined number of pulses from the start of generation of the basic clock signal, which causes a decrease in the drive speed of the solid-state image sensor 6. There is no. (2) Since the rush current flowing through the solid-state image sensor 6 and the drive circuit is reduced, the stress associated with the rapid current change on the circuit component is reduced. As a result, the life of the circuit component can be extended as compared with the case where the stress due to the current change is large. (3) The rated output capacity of the battery and the power supply circuit can be reduced by suppressing the inrush current at the start of power supply and reducing the power supply load, so that the power supply can be downsized and the cost can be reduced.

(Second Embodiment) In the second embodiment, when power supply to the solid-state image pickup device 6 and this drive circuit is started, until the timing t1 at which the temporary decrease in the power supply voltage is resolved. , The frequencies of the horizontal drive pulse signals φH1 and φH2 are gradually changed. FIG. 6 shows a horizontal drive pulse generation circuit 3 according to the second embodiment.
It is a figure which shows the structural example by the side of the horizontal drive pulse signal H1.

In FIG. 6, the CPU 61 to the counter 61
The three counter set values Z1, Z2 and Z3 are set respectively in the. The counter 61 counts the rising edges of the basic clock signal, and outputs a binary signal 00 (BIN) until the count value reaches the counter set value Z1 (count period 1). Is configured. Further, the counter 61 keeps the count value from reaching the counter setting value Z1 until reaching the counter setting value Z2 (count period 2).
It is configured to output a signal of 01 (BIN) as a decimal value. Furthermore, the counter 61 uses a binary value of 10 from the time the count value reaches the counter set value Z2 until the counter set value Z3 is reached (count period 3).
It is configured to output a (BIN) signal. After the count value reaches the counter set value Z3, a binary value of 11 (BIN) is output. The output signal of the counter 61 is input to the selection terminal S3 as a selection signal of the selector 65.

When the input signal of the selection terminal S3 is 11 (BIN), the selector 65 outputs the signal input to the input terminal A3, and the input signal of the selection terminal S3 is 10 (BI).
In the case of N), the signal input to the input terminal B3 is output. Further, the input signal of the selection terminal S3 is 01 (BIN)
When the input signal of the selection terminal S3 is 00 (BIN), the signal input to the input terminal C3 is
The signals input to 3 are output respectively.

The frequency divider 62 frequency-divides the input basic clock signal by ½ to obtain ½ of the frequency of the basic clock signal.
A clock signal of (30 MHz in the above example) is output. The frequency divider 63 divides the input basic clock signal into 1 /
The frequency is divided by 4, and a clock signal having a frequency of 1/4 of the frequency of the basic clock signal (15 MHz in the above example) is output. The frequency divider 64 divides the input basic clock signal by 1/8,
1/8 of the frequency of the basic clock signal (7.
5 MHz) clock signal is output.

The basic clock signal is input to the input terminal A3 of the selector 65. Input terminal B3 of the selector 65
A clock signal with a frequency of 30 MHz is input to.
A clock signal having a frequency of 15 MHz is input to the input terminal C3 of the selector 65. Input terminal D of the selector 65
A clock signal having a frequency of 7.5 MHz is input to 3. The signal output from the selector 65 is the horizontal drive pulse signal H1. Although the circuit configuration on the horizontal drive pulse signal H2 side is not shown, the basic clock signal is converted into a basic clock signal having an opposite polarity by an inverter so that the output signal waveform has an opposite polarity to the horizontal drive pulse signal H1. You can do this.

FIG. 7 shows the basic clock signal (selector 65
Signal input to the terminal A3 of the selector), the terminal D of the selector 65
3 signal SigD3, terminal C of selector 65
3 signal SigC3 input to the terminal B of the selector 65
3 is a diagram showing waveforms of a signal SigB3 and a horizontal drive pulse signal H1 which are input to the H.3. In FIG. 7, in the counting period 1 by the counter 61, a clock signal having a frequency of 7.5 MHz is output. In the counting period 2, a clock signal with a frequency of 15 MHz is output. In counting period 3, frequency 30MHz
The clock signal of is output. After the counting period 3, the basic clock signal having a frequency of 60 MHz is output. Similarly, for the horizontal drive pulse signal H2 (not shown), clock signals of opposite polarities having different frequencies are output in the count period 1, the count period 2, the count period 3, and the count period 3 and thereafter.

According to the second embodiment described above,
Similar to the first embodiment, the horizontal drive pulse signal φH1
Also, since the period in which the pulse peak value of φH2 is reduced is shortened and the reduction of the pulse peak value is suppressed, it is possible to prevent deterioration of image quality. Further, since the change of the circuit current related to the horizontal transfer is changed in four steps by changing the clock frequency in four steps, the solid-state image sensor 6 is changed from the first embodiment in which the circuit current is changed in two steps. And the step of changing the circuit current flowing through this drive circuit can be reduced. This makes it possible to further reduce the temporary drop in the power supply voltage and further reduce the stress on the circuit components due to the current change.

Correspondence between each component in the claims and each component in the embodiment of the invention will be described. The clock signal generation circuit is composed of, for example, the basic clock generation circuit 1. The frequency conversion circuit is composed of, for example, the frequency divider 32 (33). The clock circuit is composed of, for example, a counter 31. The clock signal selection circuit is composed of, for example, the selector 35 (36). The control circuit includes, for example, the CPU 7, the counter 31, and the selector 35 (3
6). Note that each component is not limited to the above configuration as long as the characteristic function of the present invention is not impaired.

[0032]

According to the drive circuit of the solid-state image sensor according to the present invention, it is possible to suppress image quality deterioration that occurs immediately after the start of power supply to the solid-state image sensor.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a drive circuit of a solid-state image sensor according to a first embodiment.

FIG. 2 is a basic clock signal and a vertical drive pulse signal V
It is a figure which shows the waveform example of 1-V4.

FIG. 3 is a diagram showing a configuration example of a horizontal drive pulse generation circuit.

FIG. 4 is a diagram showing waveforms of a basic clock signal and a horizontal drive pulse signal.

FIG. 5 is a diagram showing waveform examples of a power supply voltage of a drive circuit and a horizontal drive pulse signal at the start of power supply.

FIG. 6 is a diagram showing a configuration example of a horizontal drive pulse signal side of a horizontal drive pulse generation circuit according to a second embodiment.

FIG. 7 is a diagram showing waveforms of a basic clock signal, a signal input to a terminal of a selector, and a horizontal drive pulse signal.

[Explanation of symbols]

1 ... Basic clock generation circuit, 2 ... Vertical drive pulse generation circuit, 3 ... Horizontal drive pulse generation circuit, 4 ...
Vertical driver circuit, 5 ... Horizontal driver circuit,
6 ... Solid-state image sensor, 7 ... CPU,
31, 61 ... Counter, 32, 33, 62 to 64 ... Divider, 35, 36, 65 ... Selector

Claims (7)

[Claims] 1. A clock signal generation circuit for generating a clock signal to be supplied to a solid-state imaging device, a frequency conversion circuit for converting the clock signal generated by the clock signal generation circuit to a low frequency, and a power supply. A clock circuit that detects that a predetermined time has elapsed from the start, and a low-frequency clock signal that has been converted by the frequency conversion circuit until the solid-state image sensor detects that the predetermined time has elapsed in the clock circuit. And a clock signal selection circuit that supplies a clock signal that has not been converted by the frequency conversion circuit to the solid-state imaging device after the elapse of the predetermined time is detected by the clock circuit. Driving circuit for solid-state image sensor. 2. The drive circuit for a solid-state image pickup device according to claim 1, wherein the frequency conversion circuit converts the frequency of the clock signal generated by the clock signal generation circuit into ½ lower units. Driving circuit for solid-state image sensor. 3. The drive circuit for the solid-state image pickup device according to claim 2, wherein the solid-state image pickup device constitutes an image pickup device of a camera, and the timekeeping circuit is constituted by a counter, and the counter counts a predetermined value. A drive circuit for a solid-state image pickup device, characterized in that the required time to perform is the predetermined time. 4. The drive circuit for a solid-state image pickup device according to claim 3, wherein the frequency conversion circuit is composed of a frequency dividing circuit, and the clock signal selection circuit is a clock signal generated by the clock signal generation circuit. And a drive circuit for a solid-state image pickup device, comprising a selector circuit for selecting any one of the clock signals divided by the divider circuit. 5. The drive circuit for a solid-state image sensor according to claim 1, wherein the clock signal includes a horizontal drive pulse signal supplied to the solid-state image sensor, and the frequency conversion circuit includes the horizontal drive pulse signal. A drive circuit for a solid-state imaging device, which is characterized by converting the frequency of a horizontal drive pulse signal. 6. A clock signal generation circuit for generating a clock signal to be supplied to the solid-state image pickup device, a frequency conversion circuit for converting the frequency of the clock signal generated by the clock signal generation circuit, and a supply to the solid-state image pickup device. And a control circuit for controlling the frequency conversion circuit so as to change the frequency of the clock signal from a low frequency to a high frequency. 7. The drive circuit for the solid-state image pickup device according to claim 6, wherein the solid-state image pickup device starts to supply electric power and the clock signal at the time of outputting the image pickup signal, and at the end of outputting the image pickup signal. The supply is stopped, further comprising a timing circuit that detects that a predetermined time has elapsed from the start of the supply, the control circuit, the frequency of the clock signal after the passage of the predetermined time is detected in the timing circuit A drive circuit for a solid-state imaging device, wherein the frequency conversion circuit is controlled so as to change the frequency from a low frequency to a high frequency.