JP2006319656A - Driving device for charge transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving device of a charge transfer device reducing current consumption in driving the charge transfer device. <P>SOLUTION: The driving device is provided with a switch 5 which connects a first transfer electrode (electrode to which driving pulse H1 is applied) included in a horizontal charge transfer device 100 and a second transfer electrode (electrode to which driving pulse H2 is applied) included in the horizontal charge transfer device 100, wherein the switch 5 is closed, driving circuits 3 and 4 are stopped, charging and discharging are performed between the first transfer electrode and the second transfer electrode, the switch 5 is subsequently opened to operate the driving circuits 3 and 4, and the driving circuits 3 and 4 perform the residual charging and discharging to/from the first transfer electrode and the second transfer electrode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a drive device for driving a charge transfer device including a CCD and a transfer electrode for transferring charges accumulated in the CCD with a two-phase pulse.

  The CCD type solid-state imaging device includes a large number of photodiodes, a vertical charge transfer device that transfers charges accumulated in each photodiode in the vertical direction, and a horizontal charge that transfers charges transferred in the vertical direction in the horizontal direction. It has a transfer device and an output amplifier that outputs a signal corresponding to the charges transferred in the horizontal direction (see, for example, Patent Document 1).

FIG. 7 is a diagram schematically showing a horizontal charge transfer device.
The horizontal charge transfer device 100 includes an n + region 102 formed on the surface of the n-type semiconductor substrate 101, and a plurality of transfer electrodes 103 for transferring charges accumulated in the n-type semiconductor substrate 101 and the n + region 102 in the horizontal direction. It consists of The n-type semiconductor substrate 101 and the n + region 102 constitute a CCD. Each transfer electrode 103 includes an electrode 103 a formed above the n + region 102 and an electrode 103 b formed above the n-type semiconductor substrate 101 between the n + regions 102. As shown in FIG. 7, the plurality of transfer electrodes 103 include a first transfer electrode to which the drive pulse H1 is applied and a second transfer electrode to which the drive pulse H2 is applied. The transfer electrodes and the second transfer electrodes are alternately arranged in the horizontal direction. Then, the charges accumulated in the CCD below the transfer electrode 103 can be transferred in the horizontal direction by applying transfer pulses H1 and H2 having opposite phases to each other as shown in FIG.

FIG. 9 is a block diagram showing a schematic configuration inside the driving device of the horizontal charge transfer device 100 shown in FIG.
As shown in FIG. 9, the driving apparatus 200 outputs a driving pulse H1 based on the timing pulse H1_1 output from the timing generating circuit 108 and applies the driving pulse H1 to the first transfer electrode, and the timing generating circuit 108. And a driving circuit 110 that outputs a driving pulse H2 based on the timing pulse H2_1 output from the first transferring electrode and applies the driving pulse H2 to the second transfer electrode. The drive circuit 109 and the drive circuit 110 set the drive pulses H1 and H2 to high level (H) by supplying charges from the power supply terminal to the transfer electrode 103, and discharge the charges from the transfer electrode 103 to the ground terminal. Drive pulses H1 and H2 are set to a low level (L).

FIG. 10 is a diagram showing a capacitive load model of the horizontal charge transfer device 100 shown in FIG.
Since the transfer electrode 103 can be regarded as a capacitor for accumulating charges, as shown in FIG. 10, the horizontal charge transfer device 100 includes a capacitor 105 having a capacitor C _H1 that is charged and discharged by a drive circuit 109, and a drive circuit. It can be regarded as equivalent to a circuit having a capacitor 106 having a capacity C _H2 charged and discharged by 110 and a capacitor 107 having a capacity C _HH connected between the capacitors 105 and 106. Therefore, if the frequency of the drive pulses H1 and H2 is f and the amplitude is V, the consumption current I _H1 of the drive circuit 109 is (2C _HH + C _H1 ) · f · V, and the consumption current I _H2 of the drive circuit 110 is ( 2C _HH + C _H2 ) · f · V, which increases according to the capacitance of the capacitor.

JP 2001-57653 A

In recent years, the number of transfer electrodes has increased due to an increase in the number of pixels of the solid-state imaging device, and accordingly, the capacities of C _H1 and C _H2 in FIG. 10 have increased. When the capacitance of C _H1 or C _H2 increases, the current consumption in the drive circuit that outputs the drive pulse also increases.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a drive device for a charge transfer device capable of reducing current consumption when driving the charge transfer device.

  The drive device of the present invention is a drive device for driving a charge transfer device including a CCD and a transfer electrode for transferring charges accumulated in the CCD with a two-phase pulse, wherein the transfer electrode is a first electrode. A switch for connecting the first transfer electrode and the second transfer electrode, and a first transfer electrode to which the second transfer electrode is applied; and a second transfer electrode to which the second pulse is applied; Switch opening / closing control means for controlling opening / closing of the switch.

  With this configuration, current consumption when driving the charge transfer device can be reduced.

  The drive device according to the present invention includes a first pulse output means for outputting the first pulse, a second pulse output means for outputting the second pulse, and the first pulse output while the switch is closed. Pulse output means and pulse output control means for stopping the operation of the second pulse output means.

  The drive device of the present invention includes a delay element whose delay time is controlled by a DLL circuit, and the switch opening / closing control means determines the closing time of the switch based on the delay time of the delay element.

  With this configuration, the switch closing time can be kept constant.

  In the driving device according to the present invention, the first pulse and the second pulse are in opposite phases to each other, and the switch opening / closing control means starts from a time point when the potentials of the first pulse and the second pulse change. The switch is closed until the first transfer electrode and the second transfer electrode have the same potential.

  The driving device according to the present invention includes a first driving mode in which the first pulse and the second pulse are out of phase with each other, and a second driving mode in which the first pulse and the second pulse are not out of phase with each other. In the first drive mode, the switch open / close control means is configured to switch the first transfer electrode and the second transfer electrode from the time when the potentials of the first pulse and the second pulse change. The switch is closed until the transfer electrodes are at the same potential. In the second drive mode, the switch opening / closing control means does not perform the control to close the switch.

  With this configuration, it can be used for a digital camera or the like having a special shooting mode.

  ADVANTAGE OF THE INVENTION According to this invention, the drive device of the charge transfer apparatus which can reduce the consumption current at the time of driving a charge transfer apparatus can be provided.

Embodiments of the present invention will be described below with reference to the drawings.
Since the horizontal charge transfer device to be driven by the drive device described in this embodiment is the same as the configuration shown in FIG. 7, this configuration will be described with reference to FIG.

FIG. 1 is a block diagram showing a schematic configuration of a drive device for explaining an embodiment of the present invention.
The driving device 6 includes a driving circuit 3 that generates and outputs a driving pulse H1 (corresponding to the first pulse in the claims) to be applied to the first transfer electrode of the horizontal charge transfer device 100, and a horizontal charge. A drive circuit 4 for generating and outputting a drive pulse H2 (corresponding to the second pulse in the claims) to be applied to the second transfer electrode of the transfer device 100; a first transfer electrode; A switch 5 that connects the transfer electrodes, and a drive control circuit 2 that performs drive control of the drive circuits 3 and 4 and open / close control of the switch 5 are included.

  The drive control circuit 2 performs control signals H1_2 and H2_2 for controlling the operation of the drive circuits 3 and 4 and the open / close control of the switch 5 based on the timing pulses H1_1 and H2_1 generated by the timing generation circuit 1. Control signal SW_CTL is generated and output.

  The drive circuit 3 generates and outputs a drive pulse H1 based on the control signal H1_2, or stops the output operation of the drive pulse H1. The drive circuit 4 generates and outputs a drive pulse H2 based on the control signal H2_2, or stops the output operation of the drive pulse H2. The driving device 6 uses the horizontal charge transfer device 100 in either the first driving mode in which the driving pulses H1 and H2 are pulses in reverse phase or the second driving mode in which the driving pulses H1 and H2 are pulses in non-reverse phase. The driving mode can be switched according to the photographing mode.

  The first drive mode is used in a normal shooting mode (such as still image shooting) in which charges for one line are transferred in the horizontal direction and output all. The second drive mode is used in, for example, a horizontal thinning shooting mode (low resolution shooting, moving image shooting, or the like) in which charges for one line are added in the horizontal direction to transfer the number of charges to ½.

  When the horizontal charge transfer device 100 is driven in the first drive mode, the drive control circuit 2 controls the switch 5 to stop the output operation of the drive circuits 3 and 4 when the potentials of the drive pulses H1 and H2 change. And the potentials of the drive pulses H1, H2 applied to the first transfer electrode and the second transfer electrode (equivalent to the potentials of the first transfer electrode and the second transfer electrode) are the same. At this point, control for resuming the output operation of the drive circuits 3 and 4 and control for opening the switch 5 are performed.

  For example, when switching from H1 = H and H2 = L to H1 = L and H2 = H, the operation of the drive circuits 3 and 4 is stopped and the switch 5 is closed to close the first transfer electrode and the second transfer electrode. Connect the transfer electrode. As a result, charge flows from the first transfer electrode to the second transfer electrode, and the first transfer electrode can be discharged and the second transfer electrode can be charged without using the drive circuits 3 and 4. Then, when the first transfer electrode and the second transfer electrode are at the same potential, and no more charge or discharge of charge via the switch 5 is performed, the switch 5 is opened and the drive circuits 3 and 4 are opened. , The drive pulses H1 and H2 are output, so that H1 = L and H2 = H. After the switch 5 is opened, the first transfer electrode is discharged by the drive circuit 3 and the second transfer electrode is charged by the drive circuit 4, but the current consumption does not close the switch 5. It can be halved compared to charging / discharging.

10, the consumption current I _H1 of the drive circuit 3 after opening the switch 5 is (C _HH + 1 / 2C _H1 ) · f · V, and the consumption current I _H2 of the drive circuit 4 is (C _HH + 1 / 2C _H2 ) · f · V, and it can be seen that the current consumption can be halved as compared with the case of charging / discharging without closing the switch 5.

FIG. 2 is a block diagram showing a schematic configuration inside the drive control circuit 2 shown in FIG.
The drive control circuit 2 includes a delay element 21 that outputs a signal H2_1del obtained by delaying the control signal H2_1 by a delay time Td, NOT circuits 22, 23, AND circuits 25, 27, OR circuits 26, 28, and an EXNOR circuit. 24, and these are connected as shown in the figure. The AND circuit 25 outputs a control signal H1_2 [1], and the OR circuit 26 outputs a control signal H1_2 [0]. The combination of the 2-bit control signal H1_2 can be switched between operation stop and operation restart of the drive circuit 3. The AND circuit 27 outputs a control signal H2_2 [1], and the OR circuit 28 outputs a control signal H2_2 [0]. The combination of the 2-bit control signal H2_2 can be switched between operation stop and operation restart of the drive circuit 4.

  A control signal SW_CTL is output from the EXNOR circuit 24. The control signal SW_CTL is a different signal depending on the drive mode. For example, in the first drive mode, when the potentials of the drive pulses H1 and H2 change, the control signal SW_CTL that becomes H for the same time as the delay time Td of the delay element 21 is output. The control signal SW_CTL is output.

  As the delay element 21, a circuit in which an even number of CMOS inverters are connected is generally used. However, since it is difficult to control the delay time Td to be constant, it is possible to control the delay time Td using a DLL circuit. preferable.

FIG. 3 is a block diagram showing a schematic configuration inside the DLL circuit for controlling the delay time Td of the delay element 21 shown in FIG.
The DLL circuit 7 includes K delay elements 71 connected in cascade. The reference clock ck is input to the first-stage delay element 71, which is sequentially delayed and output as the delayed clock ck_del from the last-stage delay element 71. . The DLL circuit 7 compares the phases of the delay clock ck_del and the reference clock ck, outputs a signal corresponding to the comparison result, and the delay element 71 based on the signal from the phase comparator 72. And a charge pump 73 and a loop filter 74 for generating a signal for controlling a delay time of the delay element 21, and a delay time Td of each delay element 71 and the delay element 21 is controlled by a signal output from the loop filter 74. Is done. The delay time Td is controlled to be a time that is 1 / K of the cycle of the reference clock ck. With such a configuration, the delay time Td of the delay element 21 can be controlled with high accuracy. The delay time Td may be a time from when the first transfer electrode and the second transfer electrode are connected to when both transfer electrodes are at the same potential.

4A is a block diagram showing a schematic configuration inside the drive circuit 3 shown in FIG. 1, and FIG. 4B is a block diagram showing a schematic configuration inside the drive circuit 4 shown in FIG.
The drive circuit 3 includes a NOT circuit 31 to which the control signal H1_2 [1] is input, an FET 33 connected to the output of the NOT circuit 31, a NOT circuit 32 to which the control signal H1_2 [0] is input, and a NOT circuit 32. FET 34 connected to the output of No. 34, and the source of FET 33 and the drain of FET 34 are connected. The drive circuit 3 outputs the drive pulse H1 using these circuits, or stops outputting it.

  The drive circuit 4 includes a NOT circuit 41 to which the control signal H2_2 [1] is input, an FET 43 connected to the output of the NOT circuit 41, a NOT circuit 42 to which the control signal H2_2 [0] is input, and a NOT circuit 42. The FET 44 is connected to the output of the FET 43, and the source of the FET 43 and the drain of the FET 44 are connected. The drive circuit 4 outputs the drive pulse H2 using these circuits, or stops outputting the drive pulse H2.

Next, the operation of the driving device 6 will be described.
FIG. 5 is a timing chart for explaining the operation when the horizontal charge transfer device 100 is driven in the first drive mode.
As shown in FIG. 5, in the first drive mode, timing pulses H1_1 and H2_1 having opposite phases are input to the drive control circuit 2. The drive control circuit 2 outputs control signals H1_2 and H2_2 and a control signal SW_CTL based on the input timing pulse. The drive circuits 3 and 4 generate and output drive pulses H1 and H2 having opposite phases based on the control signals H1_2 and H2_2, and stop the output. A pulse indicated by a thick line in FIG. 5 is the drive pulse H1.

  Here, when the potentials of the timing pulses H1_1 and H2_1 change and the potentials of the drive pulses H1 and H2 change from the period in which H1 = H and H2 = L, the control signals H1_2 and H2_2 are shown in FIG. 5, the operation of the drive circuits 3 and 4 is stopped. Further, the control signal SW_CTL becomes H for the delay time Td, and the switch 5 is closed for the delay time Td. Thereby, charging / discharging is performed between the 1st transfer electrode and the 2nd transfer electrode, and both become the same electric potential.

  When the delay time Td elapses, the control signal SW_CTL becomes L, and the control signals H1_2 and H2_2 are changed as shown in FIG. 5, and the operations of the drive circuits 3 and 4 are resumed. When the operation of the drive circuits 3 and 4 is resumed, the first transfer electrode is discharged by the drive circuit 3 and the second transfer electrode is charged by the drive circuit 4 so that H1 = L and H2 = H. Thus, every time the potentials of the drive pulses H1 and H2 change, the operation of the drive circuits 3 and 4 is stopped for the delay time Td, and the switch 5 is closed.

FIG. 6 is a timing chart for explaining the operation when the horizontal charge transfer device 100 is driven in the second drive mode.
As shown in FIG. 6, in the second drive mode, timing pulses H <b> 1 </ b> _ <b> 1 and H <b> 2 </ b> _ 1 that are not in opposite phases are input to the drive control circuit 2. The drive control circuit 2 outputs control signals H1_2 and H2_2 and a control signal SW_CTL based on the input timing pulse. The drive circuits 3 and 4 generate and output drive pulses H1 and H2 that are not in opposite phases based on the control signals H1_2 and H2_2. A pulse indicated by a thick line in FIG. 6 is the drive pulse H1.

  Here, when the potential of the timing pulse H1_1 changes and the potential of the drive pulse H1 changes from the period in which H1 = H and H2 = L, the control signal H1_2 changes as shown in FIG. However, the operations of the drive circuits 3 and 4 are continuously performed. Further, the control signal SW_CTL remains L and the switch 5 remains open. Then, the first transfer electrode is discharged by the driving circuit 3 so that H1 = L and H2 = L.

  Next, when the potential of the timing pulse H2_1 changes to enter a period in which the potential of the drive pulse H2 changes, the control signal H2_2 changes as shown in FIG. 6, but the operation of the drive circuits 3 and 4 continues. Is called. Further, the control signal SW_CTL remains L and the switch 5 remains open. Then, the second transfer electrode is discharged by the drive circuit 4 so that H1 = L and H2 = H.

  Thus, in the second drive mode, the drive circuits 3 and 4 do not stop or the switch 5 does not close when the potentials of the drive pulses H1 and H2 change. When the drive circuits 3 and 4 are stopped or the switch 5 is closed in the second drive mode, the other drive pulse for which the potential is not to be changed also changes. Absent.

  As described above, according to the driving device 6, the switch 5 that connects the first transfer electrode and the second transfer electrode included in the horizontal charge transfer device 100 is provided. The drive circuits 3 and 4 are stopped and the drive circuits 3 and 4 are stopped. After charging and discharging between the first transfer electrode and the second transfer electrode, the switch 5 is opened to operate the drive circuits 3 and 4. , 4 is used to charge / discharge the remaining first transfer electrode and second transfer electrode, so that the charge / discharge time performed by the drive circuits 3, 4 can be shortened and the current consumption is greatly reduced. can do.

  In the second drive mode, the drive control circuit 2 and the drive circuits 3 and 4 are configured so that the drive circuits 3 and 4 are not stopped and the switch 5 is not closed. It can also be applied to a digital camera having

  In the present embodiment, the driving device 6 can switch between the first driving mode and the second driving mode. However, the driving device 6 may be driven only in the first driving mode.

The block diagram which shows schematic structure of the drive device for describing embodiment of this invention 1 is a block diagram showing a schematic configuration inside the drive control circuit 2 shown in FIG. 2 is a block diagram showing a schematic configuration inside a DLL circuit that controls the delay time of the delay element 21 shown in FIG. 1A is a block diagram showing a schematic configuration inside the drive circuit 3 shown in FIG. 1, and FIG. 1B is a block diagram showing a schematic configuration inside the drive circuit 4 shown in FIG. Timing chart for explaining the operation when driving the horizontal charge transfer device 100 in the first drive mode Timing chart for explaining the operation when the horizontal charge transfer device 100 is driven in the second drive mode A diagram schematically showing a horizontal charge transfer device The figure which shows the drive pulse applied to the transfer electrode of the horizontal charge transfer apparatus shown in FIG. The block diagram which shows schematic structure inside the drive device of the horizontal charge transfer apparatus shown in FIG. The figure which shows the capacitive load model of the horizontal charge transfer apparatus shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Timing generating circuit 2 Control circuit drive circuit 5 Switch 6 Drive device 7 DLL circuit 100 Horizontal charge transfer device

Claims (5)

A drive device for driving a charge transfer device including a CCD and a transfer electrode for transferring charges accumulated in the CCD with a two-phase pulse,
The transfer electrode includes a first transfer electrode to which a first pulse is applied, and a second transfer electrode to which a second pulse is applied,
A switch connecting the first transfer electrode and the second transfer electrode;
A drive device comprising switch opening / closing control means for controlling opening / closing of the switch. The drive device according to claim 1,
First pulse output means for outputting the first pulse;
Second pulse output means for outputting the second pulse;
A drive device comprising: pulse output control means for stopping the operation of the first pulse output means and the second pulse output means while the switch is closed. The drive device according to claim 1 or 2,
A delay element whose delay time is controlled by a DLL circuit;
The switch opening / closing control means determines a closing time of the switch based on a delay time of the delay element. It is a drive device in any one of Claims 1-3, Comprising:
The first pulse and the second pulse are out of phase with each other;
The switch opening / closing control means switches the switch from the time when the potential of the first pulse and the second pulse changes until the time when the first transfer electrode and the second transfer electrode become the same potential. Drive device that performs close control. It is a drive device in any one of Claims 1-3, Comprising:
It is possible to switch between a first drive mode in which the first pulse and the second pulse are out of phase with each other, and a second drive mode in which the first pulse and the second pulse are not out of phase with each other,
In the first drive mode, the switch opening / closing control means sets the first transfer electrode and the second transfer electrode to the same potential from the time when the potentials of the first pulse and the second pulse change. Until that time, control to close the switch,
In the second drive mode, the switch opening / closing control means does not perform control to close the switch.

Images