JP2003297959A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can realize simplification of a process for providing an index mark, prevention of separation or the like, and a manufacturing method of the semiconductor device. <P>SOLUTION: The semiconductor device has a semiconductor substrate having a main surface wherein a circuit element with a prescribed function is formed; a plurality of electrode pads which are formed on the main surface of the semiconductor substrate and are electrically connected to a circuit element; a sealing resin for sealing an upper part of the main surface of the semiconductor substrate; and a plurality of outer connection terminals which are formed above the main surface to project from the surface of the sealing resin and are disposed practically regularly at a prescribed interval. The color of at least one side surface of the semiconductor device differs from the color of the other side surface. Since an index mark can be provided in a wafer level, it is possible to eliminate position adjustment of each semiconductor device, which was carried out for providing an index mark in its discrete state in a conventional method. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip size package (CS).
P) and the manufacturing method thereof, and in particular, the technology is characterized by the structure of information (hereinafter referred to as index mark) such as characters and symbols indicating the mounting direction with respect to the mounting board and the direction of the package itself.

[0002]

2. Description of the Related Art As a technique for realizing high-density mounting of a semiconductor device on a mounting board, the size of a semiconductor device package is set to be approximately the same as or slightly larger than a semiconductor chip (bare chip). Chip size package (Chip Size Package: CSP)
There is a technology called. By arranging the connection terminals (external connection terminals) for the mounting board on the main surface (circuit forming surface) of the substantially square semiconductor chip in a grid shape, the size of the packaged semiconductor device can be made almost equal to that of the semiconductor chip. It can be the same or slightly larger.
According to such a chip size package, the mounting area of the semiconductor device on the mounting board is reduced and
The wiring length connecting the electrode on the semiconductor chip and the external connection terminal is shortened, and the operation speed of the semiconductor device can be improved.

A technique for packaging a semiconductor device in a wafer state (hereinafter referred to as a wafer level CSP) has also been proposed. Wafer level CSP is a technique for packaging individual semiconductor chips at a stage before they are cut out from the wafer. According to the wafer level CSP, the packaging process can be integrated with the wafer process, so that there is an advantage that the manufacturing cost can be significantly reduced.

Index marks are provided to the semiconductor device. The index mark is a mark for indicating the mounting direction of the semiconductor device on the mounting board. In a semiconductor device such as a wafer level CSP, this index mark is generally arranged on the back surface (circuit non-forming surface) side of the semiconductor device, and when the semiconductor device is mounted on the mounting substrate, the mounting direction of the semiconductor substrate is visually recognized. It is possible to discriminate.

[0005]

However, the index mark display method according to the prior art has the following problems because the index mark is provided for each semiconductor device. It is necessary to adjust the positional relationship between the index mark and the semiconductor device for each semiconductor device. As a result, the processing capacity is limited and the step of providing the index mark is required. When the index mark is formed by using ink or laser light, for example, in the case of ink, it may come off and cannot be discriminated. In the case of laser light, the laser light is transmitted through the silicon layer and the internal circuit pattern is It deteriorates. As the size of the semiconductor device becomes smaller, it becomes difficult to adjust the relationship between the semiconductor device and the position of the index mark.
In addition, the index mark is also small, and the mounting direction cannot be easily determined when mounting on the mounting board.

The present invention has been made in view of the above problems of the conventional semiconductor device, and an object of the present invention is to:
It is an object of the present invention to provide a new and improved semiconductor device and a method for manufacturing the semiconductor device, which can simplify the step of providing the index mark.

Another object of the present invention is to provide a new and improved semiconductor device and a method for manufacturing the semiconductor device, which can prevent the separation of the index mark and the deterioration of the circuit pattern.

Another object of the present invention is to easily adjust the positional relationship between the external dimensions and the index marks even when the size of the semiconductor device is reduced, and to easily mount the semiconductor device on a mounting board. It is an object of the present invention to provide a new and improved semiconductor device capable of discriminating the mounting direction and a method for manufacturing the semiconductor device.

[0009]

In order to solve the above-mentioned problems, according to the present invention, a semiconductor substrate having a main surface on which a circuit element having a predetermined function is formed, and formed above the main surface of the semiconductor substrate. A plurality of electrode pads electrically connected to the circuit element, a sealing resin for sealing the upper part of the main surface of the semiconductor substrate, and formed above the main surface so as to protrude from the surface of the sealing resin. In a semiconductor device having a plurality of external connection terminals, the external connection terminals being substantially regularly arranged at a predetermined interval, at least one side surface of the semiconductor device has a color different from that of the other side surface. A semiconductor device is provided which is different from the above.

At present, one-layer surface mounting is mainstream, but
Even if the technology trend to increase the mounting density is changed and the multi-layered structure is mounted, since the index mark of each semiconductor device arranged vertically is on the side surface of the semiconductor device, it is mounted on the mounting board. At that time, the mounting direction can be easily confirmed.

Further, according to the present invention, in the method of manufacturing a semiconductor device, which is manufactured by cutting the semiconductor device from the wafer after sealing the semiconductor device in the wafer state, There is provided a method for manufacturing a semiconductor device, characterized in that information indicating the direction of the semiconductor device is applied to the back surface of the wafer before cutting out from the wafer.

Since the index marks can be provided at the wafer level, it is not necessary to adjust the position of each semiconductor device, which has been conventionally performed to provide the index marks in the individualized state. Then, after adjusting the inclination of the wiring pattern formed in the device and only one specific point, the index marks are collectively given at the wafer level while the pitch is moved according to the size of the semiconductor device. can do. Therefore, it is possible to greatly reduce the processing time in the step of providing the index mark.

In the above manufacturing method, it is preferable that two or more index marks are provided for one semiconductor device. If an index mark that is sufficiently smaller than the size of the semiconductor device is used and two or more index marks are given to one semiconductor device,
Index marks can be collectively applied at the wafer level regardless of the position concept of the semiconductor device.
Since it is not necessary to adjust the position of the semiconductor device and the index mark, the processing time can be further shortened.

Further, it is preferable that the index mark is a symbol indicating a direction when the semiconductor device is mounted on the mounting board. The index mark can be easily arranged even in a small-sized semiconductor device in which the index mark made of characters cannot be arranged, and the index mark can be easily recognized even when mounted on a mounting board.

According to the present invention, a semiconductor substrate having a main surface on which a circuit element is formed, a plurality of electrode pads formed above the main surface of the semiconductor substrate and electrically connected to the circuit element, and a semiconductor A sealing resin for sealing the upper part of the main surface of the substrate, and a plurality of external connection terminals formed above the main surface so as to project from the surface of the sealing resin, and arranged substantially regularly at predetermined intervals. A semiconductor device having a plurality of external connection terminals, wherein at least one of the plurality of external connection terminals has a shape different from that of the other external connection terminals. Provided.

According to such a semiconductor device, the shape of the external connection terminal can be used as an index mark. Therefore, there are the following excellent effects. Since the step of providing the index mark itself is unnecessary, the position adjustment work for aligning the index mark with the position of each semiconductor device is unnecessary. Since the shape of the external connection terminal is used as the index mark, it is possible to prevent the index mark from being separated from the semiconductor device, unlike the conventional technique in which the index mark is formed using ink. Further, unlike the prior art in which the index mark is formed by using laser light, it is possible to prevent the deterioration of the circuit pattern inside the device. The size of the external connection terminal is 400 μm on one side (diameter).
It is about (0.4 mm), and its shape can be recognized with the naked eye. Therefore, the mounting direction can be easily determined.

If the external connection terminals having different shapes are any of the external connection terminals located near the four corners of the semiconductor substrate, the mounting direction can be easily determined. However,
It is not strictly necessary to form the four corner portions, and external connection terminals having different shapes may be provided at positions where the mounting direction can be discriminated even around the four corner portions. That is, the external connection terminals having different shapes may be any of the external connection terminals that are substantially regularly arranged at predetermined intervals, other than the external connection terminals near the center. Even when the external connection terminals are not provided at the four corners in the terminal layout design, the external connection terminals having different shapes can be provided, which increases the degree of freedom in the terminal layout design.

In some cases, like the external connection terminal connected to the ground line, a plurality of external connection terminals have the same function. In such a case, the plurality of external connection terminals may be integrally formed to have a shape different from that of the other external connection terminals, and this may be used as an index mark.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Referring to the accompanying drawings,
Preferred embodiments of a semiconductor device and a method of manufacturing a semiconductor device according to the present invention will be described in detail. In the present specification and the drawings, components having substantially the same functional configuration are designated by the same reference numerals, and duplicate description will be omitted. First, general wafer level C
The SP technology will be described with reference to FIGS.

(A) Formation of Copper Post First, an electronic circuit (not shown) having a predetermined function is formed on the main surface (circuit forming surface) of the semiconductor wafer 1 by a normal wafer process. After that, an insulating film 13 having an opening (not shown) is formed on the main surface. Then, the electrode pad 14 and the wiring (not shown) which connects this electrode pad 14 and an electronic circuit are formed. The electrode pad 14 is formed on the insulating film 13. Next, the insulating film 15 is formed on the entire main surface of the semiconductor wafer 1. The electrode pad 14 is formed on the insulating film 15 by photolithography.
An opening is formed to expose a part of the surface of the. Next, the wiring 16 is formed on the exposed surface of the electrode pad 14 and the insulating film 15. Next, a resist is applied to the entire main surface of the semiconductor wafer 1. An opening having a predetermined shape is formed in the resist by the photolithography technique. This opening is located on the surface of the wiring 16. Then, electroplating is performed to form the copper posts 2 made of copper in the openings provided in the resist. The copper posts 2 are arranged in a grid (matrix) when viewed from above the semiconductor device. The copper post 2 functions as a wiring for electrically connecting the electrode pad 14 and the wiring 16 formed on the semiconductor wafer 1 to the external connection terminal 5 formed on the copper post 2 in a later step. . In addition, copper post 2
The resist pattern for forming the film will be described later. (FIG. 1 (A)).

(B) Resin Encapsulation Next, the encapsulating resin 3 is filled on the entire main surface of the semiconductor wafer 1 to a height to completely cover the copper posts 2 (FIG. 1).
(B)). The filling of the sealing resin 3 is performed by a transfer molding method, a potting method, a printing method, or the like.

(C) Resin grinding Next, the sealing resin 3 is polished with the abrasive 4 until the upper surface of each copper post 2 buried in the sealing resin 3 is exposed.
The surface is ground (FIG. 1 (C)).

(D) Formation of External Connection Terminals Next, the external connection terminals 5 are formed in a lattice shape (matrix shape) on the upper surface of the copper post 2 by performing the following steps. The external connection terminal 5 functions as a terminal that electrically connects the semiconductor device that is individually singulated and the wiring on the mounting board on which the semiconductor device is mounted. First, a metal mask for forming the external connection terminals 5 is prepared. This metal mask is used to connect the external connection terminals 5 to the upper surface of the copper post 2.
To have a plurality of openings corresponding to the arrangement of the copper posts 2. Next, a metal mask is placed on the surface of the sealing resin 3 so that the plurality of openings are located above the corresponding copper posts 2. After that, the external connection terminals 5 are formed by pouring the solder paste into the entire area of the metal mask (FIG. 1D). Since the solder paste is not fixed on the sealing resin 3, the external connection terminals 5 can be connected to the upper surface of the copper post 2 even if the opening of the metal mask and the upper surface of the copper post 2 are not precisely aligned. Can be formed. Therefore, the shape of the metal mask is not required to be as strict as the shape of the resist in the (A) copper post forming step. Through the above steps, a large number of packaged semiconductor devices are formed on the semiconductor wafer 1.

(E) Dividing into individual pieces Next, after the grinding tape 6 is attached to the back surface (the surface on which the circuit is not formed) of the semiconductor wafer 1, the individual semiconductor devices 8 are divided into individual pieces by the cutting blade 7 rotating at high speed ( FIG. 1E).

(F) Shipment The semiconductor device 8 still adhered on the grinding tape 6 is placed on the wafer carrier 9, and the pickup collet 10 is attached.
It is set so that it is located just below. Then, the semiconductor device 8 is separated from the grinding tape 6 by the suction force of the vacuum connected to the pickup collet 10 and the push-up force of the push-up mechanism (needle-shaped pin) 12 (FIG. 2).
(F)). Then, after the product test, the individual semiconductor devices 8 are loaded into the embossed adhesive holes 11a of the embossed carrier tape 11 and shipped as products (FIG. 2 (G)).

The general wafer level CSP technology has been described above. In each of the following embodiments, a process different from each process of the above-described general wafer level CSP technology will be mainly described, and duplicate description of other processes will be omitted.

(First Embodiment) A first embodiment of the present invention will be described. FIG. 3 is a plan view of the semiconductor device 81 manufactured by the manufacturing method according to the present embodiment as viewed from the main surface side. In the semiconductor device 81, among the external connection terminals 51 arranged in a grid (matrix), the shapes of the external connection terminals 51a at the four corners are different from the shapes of the other external connection terminals 51b. 51a is used as an index mark indicating the mounting direction of the semiconductor device 81.

A method of forming the external connection terminal 51 will be described. First, as a resist for forming the copper post 2 in the copper post forming step (A), as shown in FIG.
A resist having the pattern shown in is used. That is, as shown in FIG. 3, among the copper posts 2 arranged in a grid (matrix), the shapes of the copper posts at the four corners can be formed differently from the shapes of other copper posts. ，
The pattern shown in FIG. 3 is adopted as the resist pattern. Specifically, a resist pattern having a quadrangular cross-sectional shape of the opening at a location corresponding to the external connection terminal 51a is used.

Further, in the step (D) of forming external connection terminals, the metal mask having the pattern shown in FIG. 3 is used as a metal mask for forming the external connection terminals 5.
That is, as shown in FIG. 3, among the external connection terminals 51 arranged in a grid (matrix), the shapes of the external connection terminals 51a at the four corners are different from the shapes of the other copper posts 51b. As described above, the pattern shown in FIG. 3 is adopted as the metal mask pattern. More specifically, a metal mask pattern having a quadrangular cross-sectional shape of the opening at a location corresponding to the external connection terminal 51a is used.

Since the solder paste does not adhere to the sealing resin 3, the shape of the external connection terminal 51 does not change even if the opening position of the metal mask and the upper surface of the copper post 2 are not precisely aligned. , Determined by the shape of the upper surface of the copper post 2. Therefore, the shape of the opening of the metal mask in the step (D) of forming the external connection terminal is not required to be as strict as the shape of the opening of the resist in the step (A) of forming the copper post.

Further, the solder paste is deformed to some extent by the heat during reflow, but it suffices to be able to determine that the external connection terminals 51a at the four corners have different shapes when the semiconductor device 81 is viewed from above. Since the shape of the semiconductor device 81 viewed from the upper surface is determined by the shape of the bottom surface of the external connection terminal 51, that is, the shape of the upper surface of the copper post 2, some deformation of the solder paste during the reflow process may occur.
It does not affect the use of as an index mark.

Through the above steps, the shape of the external connection terminals 51a at the four corners of the external connection terminals 51 arranged in a grid (matrix) is made different from that of the other external connection terminals 51b. The semiconductor device 81 is manufactured.

As described above, according to this embodiment, the shape of the external connection terminal 51 can be used as an index mark. Therefore, there are the following excellent effects. Since a dedicated process for applying the index mark is unnecessary, position adjustment work for aligning the index mark with the position of each semiconductor device is unnecessary. Since the shape of the external connection terminal is used as the index mark, it is possible to prevent the index mark from coming off the semiconductor device, unlike the conventional technique in which the index mark is formed using ink. Further, unlike the prior art in which the index mark is formed by using laser light, it is possible to prevent the deterioration of the circuit pattern inside the device. The size of the external connection terminal 5 is 400μ on one side (diameter).
It is about m (0.4 mm), and its shape can be recognized with the naked eye. Therefore, the mounting direction can be easily determined.

(Second Embodiment) A second embodiment of the present invention will be described. FIG. 4 is a plan view of the semiconductor device 82 manufactured by the manufacturing method according to the present embodiment as viewed from the main surface side. In the semiconductor device 82, among the external connection terminals 52 arranged in a grid (matrix), the shape of the external connection terminals 52a other than the external connection terminals near the center (region C in the drawing) is changed to another external connection terminal 52b. Different from the shape of
This external connection terminal 52a is used as an index mark indicating the mounting direction of the semiconductor device 82.

In order to form the shape of the external connection terminal 52, (A) a point of using the resist having the pattern shown in FIG. 4 in the copper post forming step, and (D) in the external connection terminal forming step shown in FIG. The use of the metal mask having the shown pattern is the same as in the case of the first embodiment.

In order to use the external connection terminals having different shapes as the index mark, any one other than the external connection terminals in the vicinity of the center (region C in the figure) having no symmetry may be used. In this respect, according to the present embodiment, the first
Unlike the embodiment described above, the external terminals that function as index marks do not necessarily have to be provided at the four corners of the grid (matrix). Therefore, in the terminal layout design, even if the external connection terminals are not provided at the four corners of the lattice (matrix), the index marks can be provided, and the terminal layout design becomes flexible.

(Third Embodiment) A third embodiment of the present invention will be described. FIG. 5 is a plan view of the semiconductor device 83 manufactured by the manufacturing method according to the present embodiment as viewed from the main surface side. In the semiconductor device 83, the external connection terminals at the four corners of the external connection terminals 53 arranged in a lattice (matrix) are integrally formed with the external connection terminals adjacent thereto.
By using one external connection terminal 53a, the external connection terminal 53a is used as an index mark indicating the mounting direction of the semiconductor device 83.

The external connection terminal may be provided with a plurality of terminals for the same function, such as a terminal provided for connecting to the ground line. In such a case, the two external connection terminals can be combined to form one external connection terminal 53a. By forming the external connection terminals 53a having different shapes, the external connection terminals 53a can be used as index marks.

In order to form the shape of the external connection terminal 53, in the process shown in FIG. 1A, a plurality of electrode pads having the same function (for example, electrodes for supplying a ground potential to an electronic circuit) are formed. Pad), wiring 1 on insulating film 15
6 connect to each other. Then, the copper post 2 is formed using a resist having an opening having a cross-sectional shape shown in FIG. That is, the copper post 2 is formed using a resist as shown in FIG. 5 which exposes the upper surface of the wiring 16 corresponding to the external connection terminal 53a used as an index mark and the upper surface of the wiring 16 corresponding to the other external connection terminal 53b. To be done. After that, in the step of forming external connection terminals shown in FIG. 1D, the external connection terminals are formed by using the metal mask having the opening of the sectional shape shown in FIG.
That is, an external connection terminal is formed by using a metal mask as shown in FIG. 5 that exposes the upper surface of the post 3 corresponding to the external connection terminal 53a used as an index mark and the upper surface of the post 3 corresponding to another external connection terminal 53b. It is formed.

(Fourth Embodiment) A fourth embodiment of the present invention will be described. FIG. 6A is a perspective view of the semiconductor device 84 manufactured by the manufacturing method of the present embodiment. The semiconductor device 84 is characterized in that the color of one side surface 84a is different from the color of the other side surface 84b. Various information can be retained by combining the presence or absence of coloring and colors.

The side surface of the semiconductor device can be colored while the semiconductor device is sucked by the pickup collet 10 in the step (E) of shipping the semiconductor device shown in FIG.

As the mounting method of the chip size package, the surface mounting of one layer is the mainstream, but the technological trend of increasing the mounting density changes, and as shown in FIG. Even when it is performed, since the index marks of the semiconductor devices arranged vertically are on the side surface of the semiconductor device, it is possible to easily confirm the mounting direction when mounting on the mounting substrate.

(Fifth Embodiment) A fifth embodiment of the present invention will be described. FIG. 7A is a plan view of the semiconductor wafer 1 before being divided into individual pieces, viewed from the back surface (circuit non-forming surface) side in the manufacturing method of the present embodiment. Figure 7
In the example shown in (A), a region divided by a dotted line shows one semiconductor device. FIG. 7B shows the semiconductor device 85 after being divided into individual pieces. As described above, in the present embodiment, as shown in FIG. 7A, the index mark is provided on the back surface of the semiconductor wafer 1 at the wafer level, and as shown in FIG. An index mark is arranged on each semiconductor device 85 after being separated.

In the present embodiment, the character information (XXX ABCD) as the index mark and the black circle at the lower left of the figure of the character information are used to determine the type of semiconductor device, the mounting direction of the semiconductor device on the mounting substrate, It has information such as the direction of the device itself.

As shown in FIG. 7B, the size of each semiconductor device must be adjusted in order to properly add index marks to the semiconductor device after being divided into individual pieces without misalignment. It is necessary to add an index mark corresponding to. The shape (orientation flat) of the semiconductor wafer 1 is used to associate character information with individual semiconductor elements.
It is possible to employ a method of positioning by using, a method of positioning by seeing through the internal pattern from the back surface of the semiconductor wafer 1, and the like.

After adjusting the inclination of the wiring pattern formed inside the device and only one specific point,
Index marks can be collectively applied at the wafer level while performing pitch movement according to the size of each semiconductor device. As described above, according to the present embodiment, since the index mark formed on the semiconductor device can be provided at the wafer level, the conventional method has been performed to provide the index mark in an individualized state. The position adjustment between the individual semiconductor devices and the device for providing the index mark is not necessary. Therefore, it is possible to greatly reduce the processing time in the step of providing the index mark.

(Sixth Embodiment) A sixth embodiment of the present invention will be described. FIG. 8A is a plan view of the semiconductor wafer 1 before being diced into pieces, viewed from the back surface (circuit non-forming surface) side in the manufacturing method of the present embodiment. Figure 8
In the example shown in (A), a region divided by a dotted line shows one semiconductor device. FIG. 8B shows the semiconductor device 86 after being divided into individual pieces. As described above, in this embodiment, as shown in FIG. 8A, the index mark is provided on the back surface of the semiconductor wafer 1 at the wafer level, and as shown in FIG. An index mark is arranged on each semiconductor device 86 after being separated. This point is the same as that of the fifth embodiment.

A feature of this embodiment is that the index mark is sufficiently smaller than the size of each semiconductor device 87. That is, the case where the index mark is provided on the back surface of the semiconductor wafer 1 without adjusting the relative positions of the individual semiconductor devices 86 (areas defined by dotted lines in FIG. 8A) and the index marks. However, the size of the index mark is set so that at least one index mark is provided to each semiconductor device.

As described above, according to the present embodiment, 1
By providing a plurality of index marks to one semiconductor device 86, the index marks can be arranged without being restricted by the position concept of the semiconductor device. Further, after the semiconductor device is divided into individual pieces, at least one index mark is arranged on each semiconductor device, so that necessary information can be grasped.

(Seventh Embodiment) A seventh embodiment of the present invention will be described. FIG. 9A is a plan view of the semiconductor wafer 1 before being diced into pieces, viewed from the back surface (circuit non-forming surface) side in the manufacturing method of the present embodiment. Figure 9
In the example shown in (A), a region divided by a dotted line shows one semiconductor device. FIG. 9B shows the semiconductor device 87 after being divided into individual pieces. As described above, in this embodiment, as shown in FIG. 9A, the index mark is provided on the back surface of the semiconductor wafer 1 at the wafer level, and as shown in FIG. An index mark is arranged on each semiconductor device 87 after being separated. This point is the same as the sixth embodiment.

A feature of this embodiment is that the index mark is a symbol indicating the direction when the semiconductor device 87 is mounted on the mounting board. In the present embodiment, a line segment having a start point and an end point and an index mark provided with a mark indicating that the end point is used. Specifically, this index mark is
It is composed of arrows.

As the size of the semiconductor device becomes smaller, it becomes difficult to dispose the index mark formed on the semiconductor device. Therefore, an index mark that does not require a relatively large area is required. In order to realize this, as shown in FIG. 8, a method in which only black circles are given to individual semiconductor devices in a wafer state can be considered. However, in this method, although black circles are given to individual semiconductor devices, it is expected that the black circles given to individual semiconductor devices after being divided into individual pieces do not function as index marks. That is, in the index mark applying step, when the alignment between the position of each semiconductor device and the device for applying the index (for example, the nozzle portion of the inkjet device) is misaligned, the index marks of all the semiconductor devices are misaligned. It will be given in the state. There is a possibility that the index mark that should be originally given may be given to the adjacent semiconductor device. Therefore, although the first pin of the individualized semiconductor device originally exists at the lower left of the paper, it may be discriminated as if it exists at the upper right.

FIG. 10A shows a case where there is a misalignment between the position of each semiconductor device and the device for applying the index (for example, the nozzle portion of the ink jet device) in the index mark applying process. There is. FIG. 10B is a diagram showing individual semiconductor devices that are singulated from the semiconductor wafer shown in FIG. As can be seen from FIG. 10B, according to the present embodiment, even if the above-mentioned misalignment occurs, the individual semiconductor devices that are singulated have the first pins on the paper surface. It can be surely determined that it exists in the lower left of the. FIG. 10C shows a case where the outer dimensions of the individual semiconductor devices to be diced are larger than those of the semiconductor device shown in FIG. 10B. According to this embodiment,
Even if the external dimensions of the individual semiconductor devices to be separated are different, the
It is possible to reliably determine that the pin exists at the lower left of the paper.

As described above, according to the present embodiment, in addition to the effect described in the sixth embodiment, the index mark can be arranged also in the small size semiconductor device. Furthermore, according to the present embodiment, the index mark can be arranged without considering the misalignment between the position of each semiconductor device and the device for applying the index (for example, the nozzle portion of the inkjet device). Furthermore, according to the present embodiment, the index marks can be arranged without considering the outer dimensions of the individual semiconductor devices.

The preferred embodiments of the semiconductor device and the manufacturing method thereof according to the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to such examples.
It is obvious to those skilled in the art that various changes or modifications can be conceived within the scope of the technical idea described in the claims, and naturally, these are also within the technical scope of the present invention. It is understood that it belongs.

For example, in the above-described embodiment, the method of manufacturing a semiconductor device by the wafer level CSP has been described. However, the semiconductor device (FIGS. 3 to 5) described in the first to third embodiments is a wafer It is not limited to the case of being manufactured by the level CSP.

Further, although the external connection terminals are provided in all of the lattice shape (matrix shape) in FIGS. 3 to 5, the present invention is not limited to this. Even if the external connection terminals are not provided on a part of the grid (matrix), by changing the shape of a part of the external connection terminals provided, this can be used as an index mark. Is possible.

In the third embodiment, the external connection terminals at the four corners and the external connection terminals adjacent to the four corners are integrally formed to form one external connection terminal 53a (FIG. 5). ), The present invention is not limited to this. The external connection terminal formed by integrally forming a plurality of external connection terminals is not formed near the center of the semiconductor device, but may be formed at a position that can function as an index mark.

Further, in some of the above embodiments, the index mark is described as a mark for indicating the mounting direction of the semiconductor device on the mounting substrate. However, this index mark may be a mark indicating the direction of the semiconductor device itself. That is, the index mark may be a mark indicating the position where the 1-pin mark of the semiconductor device exists.

Further, in the above embodiment, the external connection terminal functioning as an index mark is described as a terminal electrically connected to an electronic circuit. However, this index mark may be a terminal that is not electrically connected to the electronic circuit, that is, a so-called non-connect pin.

Further, although it is assumed that the manufacturing steps shown in the above-mentioned embodiment are appropriately changed with the progress of the semiconductor manufacturing technology, the steps which are not directly related to the features of the present invention will be described. However, it is not limited to the steps of the above-described embodiment, and can be changed as appropriate.

[0062]

As described above, the main effects of the present invention are listed below. Since the step of providing the index mark itself is unnecessary, the position adjustment work for aligning the index mark with the position of each semiconductor device is unnecessary. Since the shape of the external connection terminal is used as the index mark, it is possible to prevent the index mark from being separated from the semiconductor device, unlike the conventional technique in which the index mark is formed using ink. Further, unlike the prior art in which the index mark is formed by using laser light, it is possible to prevent the deterioration of the circuit pattern inside the device. The size of the external connection terminal is 400 μm on one side (diameter).
It is about (0.4 mm), and its shape can be recognized with the naked eye. Therefore, the mounting direction can be easily determined.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a manufacturing process of a chip size package.

FIG. 2 is an explanatory view showing the manufacturing process following FIG.

FIG. 3 is a plan view of the semiconductor device according to the first embodiment.

FIG. 4 is a plan view of a semiconductor device according to a second embodiment.

FIG. 5 is a plan view of a semiconductor device according to a third embodiment.

FIG. 6 is a plan view of a semiconductor device according to a fourth embodiment.

FIG. 7 is a plan view of a semiconductor device according to a fifth embodiment.

FIG. 8 is a plan view of a semiconductor device according to a sixth embodiment.

FIG. 9 is a plan view of a semiconductor device according to a seventh embodiment.

FIG. 10 is a plan view of a semiconductor device according to a seventh embodiment.

[Explanation of symbols]

1 Semiconductor wafer 2 Copper post 3 Sealing resin 4 Abrasive 5 External connection terminal 6 grinding tape 7 cutting blade 8 Semiconductor device 9 Wafer carrier 10 Pickup collet 11 embossed carrier tape 12 Push-up mechanism (needle pin) 13 Insulating film 14 electrode pads 15 Insulating film 16 wiring

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kentaro Arai             1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric             Industry Co., Ltd.

Claims (14)

[Claims] 1. A semiconductor substrate having a main surface on which a circuit element having a predetermined function is formed, and a plurality of electrode pads formed above the main surface of the semiconductor substrate and electrically connected to the circuit element. A sealing resin for sealing the upper part of the main surface of the semiconductor substrate, and a plurality of external connection terminals formed above the main surface so as to protrude from the surface of the sealing resin, and substantially at predetermined intervals. A semiconductor device having the external connection terminals arranged regularly, wherein the color of at least one side surface of the semiconductor device is different from the color of other side surfaces. 2. A method for manufacturing a semiconductor device manufactured by cutting individual semiconductor devices from the wafer after sealing the semiconductor devices in a wafer state, in a step before cutting the individual semiconductor devices from the wafer. A method for manufacturing a semiconductor device, characterized in that information indicating the direction of the semiconductor device is given to the back surface of the wafer. 3. The information is 2 for one semiconductor device.
The method for manufacturing a semiconductor device according to claim 2, wherein the method is provided as described above. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the information is a symbol indicating a direction when the semiconductor device is mounted on a mounting board. 5. The manufacturing of a semiconductor device according to claim 4, wherein the symbol is composed of a line segment having a start point and an end point, and a mark indicating the end point added to the end point. Method. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the symbol is an arrow. 7. A first major surface having a circuit element formed thereon,
A semiconductor substrate having a second main surface substantially opposite to the first main surface; and a plurality of external terminals formed on the first main surface and electrically connected to the circuit element. A semiconductor device comprising: a line segment having a start point and an end point; and an end point mark added to the end point, and a direction determining mark formed on the second main surface. 8. The plurality of direction discrimination marks are formed on the second main surface.
The semiconductor device according to. 9. The semiconductor device according to claim 7, wherein the direction determination mark is an arrow. 10. A semiconductor wafer having a first main surface, a second main surface substantially opposite to the first main surface, and a plurality of semiconductor device forming portions partitioned by a plurality of scribe lines. A step of preparing, a step of forming a circuit element on the first main surface of the semiconductor device forming portion, and an electric connection with the circuit element on the upper part of the first main surface of the semiconductor device forming portion A step of forming a plurality of external terminals; a step of forming information indicating a direction of a semiconductor device on the second main surface; and a step of grinding the scribe line to divide the semiconductor device forming parts into individual pieces. And a step of obtaining a semiconductor device. 11. The information indicating the direction of the semiconductor device comprises:
The method for manufacturing a semiconductor device according to claim 10, wherein two or more are formed for one semiconductor device forming portion. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the information is a symbol indicating a direction when the semiconductor device is mounted on a mounting board. 13. The manufacturing of a semiconductor device according to claim 12, wherein the symbol is composed of a line segment having a start point and an end point, and a mark indicating the end point added to the end point. Method. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the symbol is an arrow.