JP2003297838A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To keep the planarity of the surface of a bonding pad wiring pattern unchanged. <P>SOLUTION: In a semiconductor device having a multi-layer wiring structure including a wiring layer 2 provided on a substrate 1 covered by an insulating film, two interlayer insulating layers 3, 5 provided on the wiring layer 2, and wiring layers 4, 8 provided on the respective interlayer insulating layers 3, 5, a bonding pad wiring pattern 6 having a semiconductor chip for its input and output is formed on only the metal wiring layer 8 provided on the uppermost layer insulating layer 5. The bonding pad wiring pattern 6 is connected with the one or more layers of the wiring layers 2, 4 through connection holes 7a, 7b. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multi-layer wiring structure, and more particularly to a semiconductor device having an interlayer insulating layer planarized.

[0002]

2. Description of the Related Art Higher performance of semiconductor integrated circuits (LSI),
With higher integration, the wiring pitch has been reduced, and at the same time, the number of wiring layers has been increased. This increase in the number of wiring layers causes unevenness in the interlayer insulating film.

On the other hand, a high NA stepper is adopted in order to cope with a finer wiring pitch. Since this high NA stepper has a shallow depth of focus, high flatness is required for the substrate when forming a pattern. As described above, unevenness is generated in the interlayer insulating film due to the multi-layered wiring layer, and therefore flattening is performed by various methods. recent years,
CMP (Chemical Mechanical P
There is an increasing number of examples of flattening by using the polishing (chemical mechanical polishing) technique.

However, in the case of a multilayer wiring structure having three or more layers with respect to a substrate flattened by CMP, a portion such as a bonding pad portion which opens a wide space is subjected to via hole etching. It was found that the following problems occur when mixed.

13 and 14 show a conventional wiring structure. 13 is a plan view and FIG. 14 is a sectional view taken along the line AA ′ of FIG. As shown in this figure, a first wiring layer 2 is formed on a silicon substrate 1 on which transistors and the like are formed, and an interlayer insulating film 3 such as BPSG is formed so as to cover the first wiring layer 2. Are formed and planarized by CMP or the like, and then via holes (connection holes) 7a are formed by via hole etching. The via hole 7a is a minimum size connection hole, and is used in a wiring portion for electrical connection within a circuit block within an LSI chip or between circuit blocks. Then, a second wiring layer 4 is formed on the interlayer insulating film 3, and a second interlayer insulating film 5 is formed so as to cover the second wiring layer 4 and flattened by CMP or the like. To be done.

Via holes 7b are formed in the interlayer insulating film 5 by via hole etching. In the wiring portion of the semiconductor device, generally, a wide wiring pattern portion 6 (6a, 6b) for bonding pad is provided for each wiring layer.
Is provided, and the insulating films 3 and 5 on the above are largely opened.

That is, at the time of forming the above-mentioned via hole 7a, as shown in FIG. 14, the bonding pad wiring pattern portion 6a is different from other via holes.
It is formed by opening a large area, and an upper layer bonding pad wiring pattern portion 6b is also formed in the same manner. This is basically not a problem when multilayer wiring is performed without flattening the interlayer insulating films. However, when the interlayer insulating films are flattened, there is no particular problem in etching the first via hole 7a, but there is a problem in forming the second via hole 7b.

This is because only the bonding pad wiring pattern portion 6 is not completely filled with the first via hole, so that the thickness of the interlayer insulating film 5 on the wide opening becomes large. As shown in FIG. 14, the thickness a of the interlayer insulating film 5 covering the second wiring layer 2 having a normal via hole size is smaller than the thickness b of the interlayer insulating film 5 on the bonding pad wiring pattern portion 6a. Become thin. For this reason, when the second via hole 7b is formed, a portion having a different etching depth occurs. In such a case, since the via hole 7b of a normal size has a shallower hole depth than the bonding pad wiring pattern portion 6b, as described above, in the portion of the film thickness a, until the etching of the deep portion is completed. Will be over-etched considerably. When the amount of over-etching increases, the holes widen, which imposes pressure on the wiring design rule and causes a problem such as generation of foreign matter.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a problem of over-etching at the time of via-hole etching which occurs when a multilayer wiring portion of a flattened semiconductor device is formed. The purpose is to solve.

Further, since the wiring pattern portion for the bonding pad is a portion for bonding the semiconductor chip, there is a problem that the bonding strength is reduced if the portion has irregularities. Therefore, in the present invention,
A second purpose is to maintain the flatness of the surface of the wiring pattern portion for the bonding pad.

[0011]

According to the present invention, a wiring layer provided on a substrate covered with an insulating film and n-1 (n is an integer of 3 or more) or more provided on the wiring layer are provided. In a semiconductor device having an n-layer multilayer wiring structure including a planarized interlayer insulating layer and a wiring layer provided on each interlayer insulating layer, a metal wiring layer provided on the uppermost insulating layer Is electrically connected to one or more wiring layers through a connection hole, and the wiring pattern portion for the bonding pad that the semiconductor chip has for its input / output is a metal provided on the uppermost insulating layer. It is characterized in that it is formed only on the wiring layer together with the metal wiring layer.

The bonding pad wiring pattern portion is arranged in a region where no connection hole exists.

With the above structure, the structure is simplified, and the flatness of the wiring pattern portion for the bonding pad can be further improved, so that the reliability is improved.

Further, according to the present invention, the connection hole between each wiring layer is not more than twice the minimum connection hole size in each interlayer insulating layer or the minimum connection hole size is 2.
Opened by a rectangular shape with a short side of less than twice the size,
It is characterized in that the connection hole is filled with a conductive material such as metal by a process different from that of the wiring layer.

By setting the size of the connection hole to the above size, a conductive material can be embedded in the connection hole. Further, by embedding the connection hole in a step different from that for forming the wiring layer, the surface of the wiring layer provided thereon can be made flat, and the reduction in bonding strength can be prevented.

The flatness of the interlayer insulating layer is preferably 0.3 μm or less.

By setting the flatness of the interlayer insulating layer to 0.3 μm or less, lithography can be surely performed even when patterning fine wiring such as 0.5 μm lines and spaces.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 1 is a plan view showing a first reference example of the present invention, and FIG. 2 is a sectional view taken along the line AA 'of FIG. In this embodiment, a structure of three-layer wiring will be described.

A first-layer metal wiring layer 2 is formed by depositing a first-layer wiring metal on a silicon substrate 1 on which transistors and the like are formed and covered with an insulating film, and by patterning the wiring metal. The first metal wiring layer 2 is provided with a bonding pad wiring pattern portion 6a. An interlayer insulating film 3 is deposited on the first metal wiring layer 2 so as to cover the metal wiring layer 2 and planarized. Here, the flatness of the first metal wiring layer 2 does not matter.

The planarization of the interlayer insulating film 3 is performed by CMP or the like until the step difference in the chip becomes 0.3 μm or less due to the requirement of lithography. This flatness is required, for example, when patterning fine wiring such as 0.5 μm line & space, the depth of focus of lithography becomes about 1.5 μm, and further, the positional accuracy on the device is the current stepper. However, since it is necessary to have a thickness of about 0.75 μm, the step difference of the wiring portion must be 0.75 μm or less in total.

Further, in the case of the three-layer wiring, the condition that the maximum level difference can be tolerated in the case of performing the planarization twice is such that the flatness of each layer is at least 0.325 μm or less, preferably 0.
It should be 30 μm or less.

Next, the interlayer insulating film 3 is formed by lithography.
Then, the resist of the via hole 7a is patterned.
At this time, in the bonding pad wiring pattern portion 6, as shown in FIGS. 1 and 2, the resist is patterned so that a plurality of via holes 7a are arranged in an array, and then the interlayer insulating film 3 is etched by dry etching. Then, the via hole 7a is formed. Then, after depositing tungsten (W) by CVD or the like, the via hole 7a is filled with the metal (tungsten) 9 by an embedded metal process such as a blanket tungsten method in which tungsten is left only in the hole by etch back, and interlayer insulation is performed. A second metal wiring layer 4 is formed on the film 3.

Regarding the hole filling of the first layer,
For example, an embedding process of only embedding holes and forming a metal wiring layer in one step by reflowing aluminum (Al) material or high temperature sputtering may be used.

Here, a plurality of via holes are arranged in an array in the wiring pattern portion 6 for the bonding pad, and the first metal wiring layer 2 and the second metal wiring layer 4 are planar. The important point is to eliminate the part that comes into contact with. The first-layer bonding pad wiring pattern portion 6a and the second-layer bonding pad wiring pattern portion 6b are connected by the metal 9 embedded in the via hole 7a.

Next, the above steps are repeated to form an interlayer insulating film 5 so as to cover the second metal wiring layer 4, and a via hole 7b is formed in this interlayer insulating film 5. In the first embodiment shown in FIGS. 1 and 2, the second via hole 7
The via holes at the positions of b and the depths a and b of the via holes of the bonding pad wiring pad portion 6 are configured to be 0.6 μm or less at maximum due to the flattening. Therefore, the hole diameter after the via hole etching is 0.05 μm or less with respect to the finished diameter of lithography. Specifically, the difference between the depths of a and b depends on the pattern of the underlying metal, but if it is suppressed to 0.6 μm or less, the conventional problem of spread of finished diameter of holes (CD loss) does not occur.

On the other hand, in the conventional example shown in FIG.
When the thickness of the metal wiring layer 4 is 0.6 μm and the film thickness of the interlayer insulating film 5 on the metal wiring layer 4 is 1.0 μm, the depth of b is 2.0 μm at the center value and the maximum value. Then, the CD loss after etching becomes 2.6 μm, and the CD loss after etching with respect to the finished diameter of the lithography becomes 2 to 3 times, which causes a problem that the design rule at the time of designing the wiring portion must be loosened. .

Table 1 shows the result of measuring the CD loss of the via hole by the first reference example and the conventional example shown in FIG.

[0028]

[Table 1]

When the wiring is a three-layer wiring, the via hole 7b here is filled with a via hole by tungsten (W) CVD or the like, and a blanket tungsten method is used in which tungsten is left only in the hole by etching back. It is preferable to fill the via holes with metal in the embedded metal process. This is done by a process of filling and forming a metal wiring layer in one step by reflowing an aluminum (Al) -based material or high temperature sputtering, and therefore, it is necessary to supply metal to the hole, so that the third layer above the hole is formed. This is because there is a problem that a concave portion as shown in FIG. 3 is formed on the metal wiring layer 8 of FIG. The bonding pad wiring pattern portion 6c is a portion for connecting the semiconductor chip to the frame by the bonding wire. Therefore, if there is unevenness in this portion, the bonding strength will be reduced, and thus it is desirable that the wiring pad portion 6c be flat. Figure 4
As shown in, when the via hole 7b is filled with metal by the buried metal process, it is possible to flatten by etching back or CMP, and the surface of the third metal wiring layer 8 provided thereon is flat. Can be

Further, when the embedded metal is used, it is best that the via holes have the same size everywhere, but the wiring portion for connecting the circuit blocks between the wiring layers and between the circuit blocks throughout the entire chip. According to the experiment, it is possible to fill the embedded metal into the via hole even if it is opened by a rectangular shape having a short side of less than twice the minimum via hole size used for It has been confirmed.

The etch back in the buried metal process gives a good result even by the dry etching, but the CMP process has a better result.
The flatness at the time of depositing the wiring metal of the layer is improved.

When a rectangular hole having a short side having a size not more than twice the minimum size or not more than twice the minimum size is filled with tungsten (W) or the like as in the present invention, metal protrusion is not always required. Although the amount is not constant, if the wiring is formed by a deposition method with a flow property such as high temperature sputtering in addition to the embedded metal process,
It has been confirmed that the flatness of this portion is further improved, and even if the protruding amount of the embedded metal in the hole of 1 μm is about ± 0.3 μm, the flatness is almost completely achieved and the bonding strength is not lowered.

After the above process, the third metal wiring layer 8 is formed. Thus, the first metal wiring layer 2, the second metal wiring layer 4 and the second metal wiring layer 4 are formed.
All the connections between the third metal wiring layer 8 and the third metal wiring layer 8 are made through the via holes 7a and 7b which can be embedded using the embedded metal 9.

Then, a passivation film is deposited on the third metal wiring layer 8 and the bonding pad wiring pattern portion 6 is opened large as usual to obtain this semiconductor device.

As shown in FIG. 2, in the first reference example, the bonding pad wiring pattern portion 6a provided on the first metal wiring layer 2 and the bonding pad provided on the second metal wiring layer 4 are provided. By connecting the wiring pattern portions 6b for use with a plurality of via holes 7a, the depth of the via holes 7b on the second metal wiring layer 4 is made constant. With this configuration, the amount of over-etching in all holes can be made constant, and the above-described problems during conventional etching can be avoided.

In the second reference example of the present invention, the inspection after the hole etching can be easily performed by adding the opening for inspection of the pattern etching of the via hole in the first reference example. It was done.

The basic configuration shown in the first reference example is the first
The connection between the metal wiring layer 2 of the second layer and the metal wiring layer 4 of the second layer is all performed through the via hole 7a which can be embedded using the embedded metal 9. That is, as shown in FIG. 2, a plurality of bonding pad portions 6a provided on the first-layer metal wiring layer 2 and bonding pad portions 6b provided on the second-layer metal wiring layer 4 are provided. By connecting with the via hole 7a, the depth of the via hole 7b on the second-layer metal wiring 4 and the opening of the bonding pad wiring pattern can be made constant,
This avoids the problem of widening the hole diameter during etching.

However, in this structure, the aperture ratio of the via hole is extremely reduced, and the aperture ratio may be about 10% of the conventional one. Therefore, the optical end point detection does not work well during etching, and it is necessary to fix the time by calculation and perform etching. The etching process is generally a simple method in which the time obtained by adding the over-etching time to the optical end point detection time is determined as the etching time. However, when the basic configuration shown in the first embodiment is used, since the time management is performed only,
It takes time to determine the conditions.

Since it is necessary to determine the etching conditions for each product, it is advantageous to arrange an inspection pattern opening as shown in the second reference example below in order to shorten the product trial time. is there. Further, the configuration of the second reference example also has an effect that in-line inspection during mass production can be performed by a simple method.

In the second reference example of the present invention shown in FIG. 5, the wiring metals 2 and 4 are arranged immediately below the inspection openings 12 and 13 for via hole etching which are not used for electrical connection. It is intended to provide a pattern for inspecting that holes are surely opened by using a metallurgical microscope. When the inspection openings 12 and 13 are not opened by etching, the portions are colored due to light interference.

Twelve reference examples will be described with reference to FIG. First, a transistor is formed on the silicon substrate 1, the gate wiring 14 and the like are arranged on the field oxide film 11, and the insulating film 16 is formed on the silicon substrate 1.
Coated with. A first-layer metal wiring layer 2 is formed by depositing a first-layer wiring metal on the silicon substrate 1 and patterning it. Here, the insulating film 16
May or may not be flattened. The first wiring metal layer 2 is provided with a bonding pad wiring pattern portion 6a. Interlayer insulation film 3
Is deposited and the interlayer insulating film 3 is planarized by CMP.

Subsequently, the resist is patterned to form the first via hole 7a. At this time, at least 1 is formed in the semiconductor chip or in the dicing line portion.
A pattern of via etching inspection openings 12 is provided at more than one place. Further, in the bonding pad wiring pattern portion 6, the resist is patterned so that a plurality of via holes 7a are arranged in an array, as in the first embodiment described above. After that, the interlayer insulating film 3 is etched by dry etching to provide the via hole 7a and the opening 12 for inspection of the via etching.

By the way, when CMP is used only on the interlayer insulating film 3, that is, when the planarization on the gate is not performed, the height of the underlying metal wiring layer 2 from the silicon substrate 1 varies, and therefore, In the via hole 7a of No. 1, the depth differs depending on the step difference of each pattern of the base. Therefore, in this embodiment, in order to make the inspection method of via etching more reliable, the deepest hole 7a is formed.
In order to make the inspection opening 12 and the inspection opening 12 have the same depth, the height of the metal wiring layer 2 provided directly below the inspection opening 12 for via etching from the substrate 1 is at the bottom of all wiring patterns. I am trying to do it.

Inspection opening 1 used in this second reference example
No. 2 can be inspected with an opening of 1 μm square or more by increasing the magnification when inspecting using a metallurgical microscope. However, since a magnifying power of 50 to 150 times is practically used, it is desirable that the opening is 10 μm square or more. If the insulating film 3 remains on the metal wiring layer 2 due to insufficient etching time, the inspection opening 12 looks brown depending on the remaining film thickness.

By etching the interlayer insulating film 3 and inspecting the inspection opening 12, it is confirmed that the via hole 7a is surely opened. Then, after depositing tungsten (W) by CVD or the like, the via hole 7a is filled with the metal (tungsten) 9 by an embedded metal process such as a blanket tungsten method in which the tungsten is left only in the hole by etch back. The metal wiring layer 4 of the first layer is formed on the interlayer insulating film 3.

Next, the above steps are repeated to provide an interlayer insulating film 5 so as to cover the second metal wiring layer 4, and the via hole 7b and the inspection opening 13 are formed in the interlayer insulating film 5.
To form. At this time, the inspection opening 13 for via etching is at a position different from the same inspection opening 12 in the lower layer,
That is, it is formed at a position where it is not laminated with the inspection opening 12.

Inspection opening 1 used in this second reference example
As for 2 and 13, those of 80 × 80 μm were adopted. If the insulating film remains on the wiring metal due to insufficient etching time, the inspection opening 12 or 13 looks brown.

With such a structure, even if there is a problem in etching and the insulating film remains, sieving can be performed by in-line inspection, so that etching conditions can be set in a short time. Such an opening did not change the effect whether it was arranged in the pattern or in the dicing part.

Further, by disposing the first and second etching patterns at different positions, it is possible to avoid the problem of etching in the second via hole as shown in the first embodiment.

The structure shown in FIG. 6 is provided with an opening for monitoring the film thickness before and after etching using an optical film thickness meter. That is, the inspection opening 12a is provided on the metal wiring layer 2, and the inspection opening 12b in which the metal wiring pattern is not arranged is provided below. When this pattern is used, it is necessary to perform the above-described etching state inspection step twice, but the etching amount can be reliably monitored.

In this case, the size of the inspection opening 12b is the same as that of the inspection opening 12a having the metal wiring layer 2 directly below, and the size of 80 × 80 μm is adopted and arranged.
When the film thickness is measured using an optical measuring device, the size may be 5 μm square or more, but an opening of 10 μm square or more is desirable.

With such a structure, when there is a problem at the time of etching, in addition to the effect shown in the reference example shown in FIG. It can be improved and higher yield can be achieved.

Further, with such a configuration, since monitoring can be performed when the etching conditions are set out, the inspection cannot be performed, the overetching time is extended, and the safety of the configuration shown in the first embodiment is considered. The etching time can be shortened by about 15% compared to the conventional one, which also leads to improvement in throughput.

In FIGS. 7 and 8, the via hole inspection opening 12 is provided at the deepest place where the elevation from the substrate 1 is surrounded by the wiring pattern 2 located at the highest position of all the patterns. It is a thing. When the line width of the peripheral pattern of this pattern was set to 5 μm, it was found that the film thickness after CMP was 0.05 to 0.1 nm thicker than that of the pattern having no pattern in the peripheral portion.

This thickness is 1-2 in terms of etching time.
If possible, such a pattern should be adopted because it corresponds to seconds. However, this makes the area large, which is disadvantageous when arranging in a chip pattern.

Further, although CMP is capable of global flattening, a slight difference in elevation remains depending on the pattern because of pattern dependence. The configurations shown in FIGS. 7 and 8 ensure that the deepest pattern is provided. With this structure, a deep opening is formed, so that the reliability of the inspection is improved.

9 and 10 show a first embodiment of the present invention, FIG. 9 is a plan view, and FIG. 10 is a sectional view taken along the line AA 'of FIG. The first embodiment is a semiconductor device in which a bonding pad wiring pattern portion 6 which a semiconductor chip has for its input / output is formed only on the uppermost part of a multilayer metal wiring layer.

The first embodiment will be described with an example of three-layer wiring. First, a transistor is formed, a first-layer wiring metal is deposited on a silicon substrate 1 covered with an insulating film, and patterned to form a first-layer metal wiring layer 2. The insulating film here may or may not be planarized. No pad portion is formed in the first-layer wiring pattern. That is, the wiring pattern portion for the bonding pad is not provided in the first metal wiring layer 2. An interlayer insulating film 3 is deposited on this,
The interlayer insulating film 3 is flattened by CMP.

After that, the via hole 7a is formed in the interlayer insulating film 3.
Then, the second metal wiring layer 4 is deposited and patterned. The wiring pattern portion 6 for bonding pad is not formed in the second metal wiring layer 4 either. After this,
The second interlayer insulating film 5 is deposited and planarized, and the second via hole 7b is opened. A third metal wiring layer 8 is deposited on this and patterned. The bonding pad wiring pattern portion 6 is formed only on the third metal wiring layer 8.

As described above, in the configuration of the first embodiment, the configuration shown in the first reference example is unnecessary. In this case, the lower metal wiring layer is the via hole 7a.
By (7b), the wirings up to the third layer are connected, and the wiring patterns for bonding pads 6 are connected on the third layer.

However, in this case, connecting to the wiring of the third layer by the via hole 7a (7b) at any place in the chip causes the wiring of the third layer to be overcrowded. It is necessary to connect to the upper layer using a via hole near the pattern part. Therefore, compared with the configuration of the first reference example, there is a drawback that wiring cannot be arranged near the bonding pad wiring pattern portion 6 and the chip size is slightly increased, but the structure is simple and the bonding The reliability is improved because the flatness of the pad wiring pattern portion can be further improved.

11 and 12 show a third reference example of the present invention, FIG. 11 is a plan view, and FIG. 12 is BB 'of FIG.
It is a line sectional view. The metal wiring layer on the silicon substrate 1 side of the (n-1) th layer has a structure in which the wiring pattern portion for the bonding pad is not provided, and the bonding pad described in the third embodiment shown in FIGS. 9 and 10 is used. The wiring pattern portion 6 for use has the same structure as the structure of the semiconductor device formed only on the uppermost part of the multilayer metal wiring layer.

This reference example will be described using an example of three-layer wiring. First, a transistor is formed, a first-layer wiring metal is deposited on a silicon substrate 1 covered with an insulating film, and patterned to form a first-layer metal wiring layer 2. Here, the insulating film 16 may or may not be planarized. No bonding pad wiring pattern portion is formed in the first layer wiring pattern.
An interlayer insulating film 3 is deposited on this, and the interlayer insulating film 3 is subjected to CMP.
To flatten.

After that, the via hole 7a is formed in the interlayer insulating film 3.
Then, the second metal wiring layer 4 is deposited and patterned. On the second metal wiring layer 4, a bonding pad wiring pattern portion 6a is formed. Therefore, in the first metal wiring layer 2, the wiring that needs to be connected to the bonding pad wiring pattern portion is the bonding pad wiring pattern portion 6a of the second metal wiring layer 4 through the metal 9 embedded in the via hole 7a. Connected with. After that, the second interlayer insulating film 5 is deposited and planarized, and the second via hole 7b is opened. At this time, the wiring pattern portion for the bonding pad has a large opening as in the usual method. At this time, since the depth of the via hole 7b and the opening of the pad portion have the same depth a, it is not necessary to consider the above-mentioned problem regarding hole etching. A third metal wiring layer 8 is deposited on this and patterned. The bonding pad wiring pattern portion 6b here is used only for the third metal wiring layer 8.

Further, a passivation film 10 is formed on this.
Is deposited, and the opening 15 is formed by etching only the wiring pattern portion for the bonding pad. Here, since the passivation film 10 is conformally formed because it is not flattened, the bonding pad wiring pattern portion can be etched without any problem.

[0066]

As described above, according to the present invention, the wiring pattern portion for the bonding pad which the semiconductor chip has for its input / output is formed only on the uppermost part of the multilayer wiring layer, so that the structure is simplified. At the same time, since the flatness of the bonding pad wiring pattern portion can be further improved, the reliability is improved.

[Brief description of drawings]

FIG. 1 is a plan view showing a first reference example of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ of FIG.

FIG. 3 is a cross-sectional view showing a state in which a wiring layer is connected via a via hole.

FIG. 4 is a cross-sectional view showing a state in which a wiring layer is connected via a via hole.

FIG. 5 is a sectional view showing a second reference example of the present invention.

FIG. 6 is a sectional view showing a second reference example of the present invention.

FIG. 7 is a sectional view showing a second reference example of the present invention.

FIG. 8 is a plan view showing a second reference example of the present invention.

FIG. 9 is a plan view showing the first embodiment of the present invention.

10 is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 11 is a plan view showing a third reference example of the present invention.

12 is a cross-sectional view taken along the line BB ′ of FIG.

FIG. 13 is a plan view showing a conventional wiring structure.

14 is a cross-sectional view taken along the line AA ′ of FIG.

[Explanation of symbols]

1 Silicon substrate 2 First metal wiring layer 3 Interlayer insulation film 4 Second metal wiring layer 5 Interlayer insulation film 6 Wiring pattern part for bonding pad 7a, 7b via hole 8 Third metal wiring layer 9 Embedded metal

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Mitsuru Irinoda             1-3-3 Nakamagome, Ota-ku, Tokyo Stocks             Company Ricoh (72) Inventor Yoshikazu Ueno             1-3-3 Nakamagome, Ota-ku, Tokyo Stocks             Company Ricoh (72) Inventor Takahiko Kuroda             1-3-3 Nakamagome, Ota-ku, Tokyo Stocks             Company Ricoh F term (reference) 5F033 JJ08 JJ19 NN34 PP06 PP15                       QQ08 QQ31 QQ48 QQ73 QQ75                       UU05 VV07 WW01 XX01                 5F044 EE00

Claims (4)

[Claims] 1. A wiring layer provided on a substrate covered with an insulating film, and a flattened interlayer insulating layer of n-1 (n is an integer of 3 or more) provided on the wiring layer. , A wiring layer provided on each interlayer insulating layer, and a semiconductor device having an n-layer multi-layer wiring structure, the metal wiring layer provided on the uppermost insulating layer has one or more wiring layers. The wiring pattern portion for the bonding pad, which is electrically connected to the layer through the connection hole and which the semiconductor chip has for its input / output, is formed only on the metal wiring layer provided in the uppermost insulating layer. A semiconductor device formed together with the semiconductor device. 2. The semiconductor device according to claim 1, wherein the bonding pad wiring pattern portion is arranged in a region where a connection hole does not exist. 3. The connecting hole between each wiring layer is formed in a rectangular shape having a short side of a size not more than twice the minimum connecting hole size of each interlayer insulating layer or a size not more than twice the minimum connecting hole size. 3. The semiconductor device according to claim 1, wherein the semiconductor device is opened, and the connection hole is filled with a conductive material such as metal by a process different from that of the wiring layer. 4. The semiconductor device according to claim 1, wherein the flatness of the interlayer insulating layer is 0.3 μm or less.