JP2003297082A - Semiconductor memory device and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can be replaced by a SRAM completely, has simple constitution, and is easy to use, and its control method. <P>SOLUTION: As control and structure technology of large capacity SRAM interchangeable module using a DRAM, write-back by FIFO is performed for a DRAM of a refresh-period by switching alternately a work period and a refresh-period in two DRAM chips, and long time access exceeding access time limit tRAS of a DRAM is realized by using succession cache controlling smoothly access at switching write-back and work/refresh using cache by extension or shortening control. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of controlling the same, and is effective by utilizing a dynamic RAM while allowing an operation equivalent to that of a static RAM from the outside. It is about.

[0002]

2. Description of the Related Art As a semiconductor memory device aiming at a large storage capacity of a dynamic random access memory (hereinafter simply referred to as DRAM) and ease of use of a static random access memory (hereinafter simply referred to as SRAM). , A pseudo SRAM or a virtual SRAM has been proposed. Japanese Unexamined Patent Application Publication No. 2001-93277 has been proposed as a technique for completely obscuring the control of the refresh operation in such a pseudo SRAM or virtual SRAM from the outside of the chip. According to the technique described in this publication,
At least a pair of memory cores having a plurality of memory cells each composed of a capacitor, to which the same data is written,
The refresh generation circuit, the refresh control circuit, and the read control circuit are formed on one semiconductor chip, and are controlled as a refresh core that executes a refresh operation and a read core that executes a read operation every predetermined period.

[0003]

An SRAM is used for the data area of the memory for the mobile phone, but the capacity shortage of the data area has become a problem with the enhancement of the function as the mobile information terminal. In the technique described in the above publication, S
It lacks consideration for the operation corresponding to the long cycle in the RAM and the write operation to the memory core during the refresh period, and it is necessary to complicate the control of the memory control circuit or to provide a limitation on the write operation. . Further, since it is formed in one semiconductor integrated circuit, enormous cost and time are required to develop the product.

Therefore, in the present inventors, the SRA
Two existing DRs to realize an inexpensive large-capacity memory module while maintaining compatibility with the M interface
Data can be stored by combining a simple control chip with an AM chip.
A circuit configuration and a control method for replacing the SRAM with the refresh operation being completely hidden from the outside of the semiconductor memory device by overlapping and storing were studied.
That is, in the DRAM, the memory cell cannot be kept in the selected state for a long time, and it is necessary to execute the precharge command within a certain time. For this reason, it is necessary to limit the long-time access permitted to the static RAM as it is, and to perform complicated control such as internally issuing a precharge command. As described above, in order to completely realize the replacement as the SRAM while using the DRAM, there is a problem that in addition to consideration of the refresh operation, the restriction corresponding to the long-time access must be avoided.

An object of the present invention is to provide a semiconductor memory device which can be more completely replaced with SRAM and a control method thereof. Another object of the present invention is to provide a semiconductor memory device having a simple structure and easy to use, and a control method thereof. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. SRAM with respect to two DRAMs having the same address space and having a refresh control circuit
And an input / output interface circuit compatible with
A memory control circuit provided with a cache memory corresponding to each of the first and second DRAMs and a commonly used FIFO memory, enabling normal operation of writing / reading to one of the two DRAMs, The time allocation control for instructing the refresh operation is alternately performed for the other DRAM, and when the write / read operation is performed for the one DRAM, the data is written in the FIFO memory between the refresh operations of the other DRAM. The write operation is performed according to the write information to the one DRAM.

When a write operation is performed on one of the first and second DRAMs for a certain period before the refresh operation is shifted to the normal operation, the refresh indicates the write information. The read operation to the address stored in the cache memory in the normal operation after the switching is performed by the data stored in the cache memory instead of the other DRAM. Is output, and when writing to the address stored in the cache memory is instructed, data is written to the other DRAM to invalidate the contents of the cache memory, otherwise the next refresh of the other DRAM is performed. Between refresh operations during the period The write operation of the data corresponding to the write information of the cache memory.

[0008]

1 is a block diagram of an embodiment of a semiconductor memory device according to the present invention. The semiconductor memory device of this embodiment is configured by combining the following three semiconductor chips CHIP1 to CHIP3. CHI
P1 (CTL # LOGIC) receives the SRAM interface signal as input and CHIP2 (DRAM1), CHI
This is a circuit for controlling DRAM access to P3 (DRAM2), and this circuit performs all control when implementing an SRAM compatible memory using DRAM. CHIP
2 (DRAM1) and CHIP3 (DRAM2) are SR
It is a DRAM that can be replaced by AM.

The external interface signal in this embodiment will be described. S- / CE1, S-CE2, S
-/ WE, S- / OE, S- / UB, S- / LB are general SRAM interface signals. SRAM
The interface signals will be briefly described. S- /
CE1 and S-CE2 are chip enable signals, S- / W
E is a write enable signal, S- / OE is an output signal, S- / UB is an upper byte selection signal, S- / L
B is a lower byte selection signal. SRAM from the outside
CHIP1 accessed through the interface
(CTL # LOGIC) is converted into a command signal necessary for accessing the DRAM and input to the DRAM.

CHIP2 (DRAM1), CHIP3
The refresh operation peculiar to the DRAM is hidden by duplicating and holding the data in the (DRAM 2). That is, the memory control operation by CHIP1 is basically C
CHIP2 (DRAM1) and CHIP by HIP1
3 (DRAM 2) are alternately accessed, and when writing or reading is performed in one DRAM, the refresh operation is executed in the other DRAM.

FIG. 2 shows CHIP1 (CTL # L of FIG.
A block diagram of one embodiment of an OGIC) is shown. In the figure, the part surrounded by the broken line is a characteristic part of the present invention. SDCTL is an access control circuit that controls DRAM access. WRBREG has 2 data
A holding circuit (register) for temporarily holding the write-back data when the data is redundantly held. TIMECNT is
It is a time control circuit that controls writing of the WORK / REF period and write-back hold data.

The ATD is an address signal change detection circuit that detects a change in an address signal and a command signal and outputs a pulse, and the DTD is a signal change detection that detects a change in a data signal and a command signal and outputs a pulse. The R / W BUFFER is a circuit, and is a read / write buffer circuit that temporarily holds data for reading and writing of DRAM. The INT is an initialization circuit for initializing the DRAM when power supply to the DRAM is started.

The TMP is a temperature measuring module that detects a temperature and outputs a signal according to the detected temperature to the RC and SDCTL. The RC is a refresh counter that generates an address for refreshing at the refresh interval of the DRAM. Circuit, temperature measurement module TMP
The refresh interval is changed according to the temperature by the output signal of. PM is a power supply circuit for supplying power to the DRAM and controlling the power supply. CLK # GEN generates a clock to generate all clocks in the DRAM and the control circuit (CTL # LOGI
It is a clock generation circuit to be supplied to C).

FIG. 3 is a block diagram showing an embodiment of the CTL # LOGIC shown in FIG. In this example,
SDCTL1 / SDCTL2 as an access control circuit and a register WRBREG as a write-back data holding circuit for the two DRAM1 / DRAM2 respectively.
The cache memories CACHE1 / CACHE2 are prepared in the cache memory CACHE2, and each cache memory CACHE has the functions of a normal cache CACHE and a takeover cache DUT # CACHE.

This CACHE and DUT # CACHE are
The circuits may be duplicated or may have different configurations. The capacity of CACHE is only for one access, so the circuit scale can be small. That is, the address signal necessary for the write operation, its write data, and the mask signal are included. C
When overlapping the circuit configuration of ACHE with DUT # CACHE, the normal CACHE control signal and DUT # CACHE are used.
CAC for performing CACHE operation by narrowing down control signals
Since the operating speed of the HE tends to be slow, when the operating speed of the DRAM is high, the normal CACHE and DUT # CAC are used.
It is advisable to use HE as a separate circuit configuration to reduce the burden of CACHE control. The important thing here is that the two DRAMs 1 and 2
When data is held in duplicate by using each DRAM 1 and 2
Is to configure a dedicated CACHE function for, and to have a normal CACHE function and a DUT # CACHE (takeover) function as its function.

The control signals input to and output from CACHE will be described below. WORK1 / REF1 (WORK2
/ REF2) is a signal indicating whether each DRAM is in a WORK (write / read normal operation = corresponding to external access) period or a REF (refresh operation) period. CACPRD1 (CACP
RD2) is a signal indicating a normal CACHE write period.

DUTPRD1 (DUTPRD2) is a signal indicating a DUT # CACHE write period corresponding to a long-time access (access that extends over the WORK / REF period). These are generated by TIMECNT. W
TS1 (WTS2) is a write pulse signal obtained by sampling the rising edge (determination of write data) of the S- / WE signal of the external SRAM interface signal and synchronizing it in SDCTL. CAXRD1 (CACRD2) is
This is a read pulse signal when the access control circuit reads CACHE.

CACV1 (CACV2) is CACHE
Is a valid (VALID) signal indicating that is valid. CACHIT1 (CACHIT2) is CACH
CACHEHIT when external access is made to the same address as the CACHE holding address while E is valid
(Cache hit) signal. CACDATA1
(CACDATA2) is the above-mentioned CACRD1 (CA
C read by the read pulse signal of CRD2)
It is the content (address / data) of ACHE.

A block diagram of one embodiment of CACHE of FIG. 3 is shown in FIG. A feature of this embodiment is that the CACHE control is divided according to the external upper byte signal (S- / UB) and the lower byte selection signal (S- / LB). UB # CNT controls the upper byte, and LB # CNT independently controls the lower byte. Although the details of the operation will be described later, the VALID signal and the CACHITHIT signal indicating that the above-mentioned CACHE is valid are UB # CNT side and LB # C
It is output by the logical sum on the NT side.

In FIG. 5, WORK / R for duplicating data and concealing refresh by using two DRAMs.
A timing diagram is shown to explain the concept of switching EF periods. The basic principle will be described below. Generally, DRAM must perform a refresh operation to retain data. So two DRAMs
WORK period (for external access) and REF
The period (refresh) is repeated alternately.

The DRAM normally needs to be refreshed within 64 ms.
Refresh must be completed for all DRAM memory cells during the period. But the data 2
Since the duplicated data is held, it is necessary to write back the same data in the REF period side for the write access generated in the WORK period side. Therefore, a holding circuit for holding the write data temporarily is required. One W
During the ORK / REF period, WORK side is tWKP, REF
If the side is tRFP, then tWKP = tRFP must be satisfied.

The time tWKP = tRFP is equal to the characteristic tRAS (Active to Pre) in the DRAMs 1 and 2 to be used.
charge command period) will be set to a shorter period. This corresponds to long-time external write access, and external write access is WORK / RE
DRAM that was in the WORK period when straddling F switching
Has already executed the ACT command. Therefore, REF
When shifting to the period, the PRE command must be executed for the address, but this is a device for not violating the tRAS characteristic of the DRAM at this time. Conversely, if the time tWKP = tRFP is set longer than tRAS, the PRE command must be executed during one WORK / REF period, which increases the load on the memory control circuit.

FIG. 6 shows a timing diagram for explaining the holding of the write back data. In the normal case, the data to be written back is performed in response to the external write access generated on the WORK side, so the DRAM on the REF side writes back the data temporarily held in the FIFO. The relationship between the external write access and the write back access by the FIFO is that the write data at that time is written in the FIFO when the external write access is completed. After that, the DRAM on the REF side reads the data held in the FIFO and writes it back to the DRAM.
According to this relationship, in the write access that occurs immediately before the WORK / REF switching, the DRAM on the REF side shifts to the WORK side without time to write back. As a result, coherency occurs between the two DRAMs.

In order to avoid this, in the present invention, a tCWCS (standard CACHE write period) is provided immediately before the WORK / REF switching, and when external access is completed during this period, the write data is transferred to the CACH instead of the FIFO.
E was made to hold. If a read access to the address occurs during the WORK period, DRA
By reading the data from CACHE instead of M, the consistency of the data when viewed from the outside is maintained.
The actual write back to the DRAM is performed at the beginning of the next REF period, so that the WOR is performed by the write back.
K (external access) is prevented from being restricted.

Further, the external write access is the above-mentioned tC.
Two DRs if continued over the WCS period
In the AM, WORK / REF switching is performed, and the DRAM that was the target of write back (REF side) becomes external access compatible (WORK side), and external access compatible (WORK side).
The DRAM that was on the K side is subject to write back (REF
Side). In such a case, the external write access write processing is performed by the DUT instead of the DRAM on the WORK side.
Transfer the processing target to #CACHE (takeover). Therefore, the DRAM in the WORK period also has a data holding circuit for writing back. If the access ends during this WORK period, the write data is D
The data is written in UT # CACHE, and the write-back is performed at the beginning of the next REF period as in the case of normal CACHE.

FIG. 7 shows a timing chart for explaining the holding of the write back data. This figure illustrates that two DRAMs must each have a CACHE that is a write-back data holding circuit, and the external write access (1) that started when the DRAM 1 was in the WORK period is the DRAM.
When the tCWCS period of 2 elapses, the DRAM 1 becomes WO
From RK period to REF period DRAM2 switches from REF period to WORK period.

As a result, the target of this external write access (1) shifts from DRAM1 to DUT # CACHE2. External write access (1) is then DRAM
DU at this point because it was completed during the 2 WORK period
T # CACHE2 becomes valid. Then, external write access (2) occurs, and this access is the next WORK / R.
If it ends immediately before the EF switch (tCWCS period),
CACHE1 becomes valid. At this time DUT # CACH
E2 writeback has not been done yet, so DUT #
CACH2 is the period until the write back ends, CACH
The valid periods of E will overlap. Therefore, CACHE
It can be seen that the same write data holding circuit must be provided in each of the DRAM 1 and the DRAM 2 unlike the FIFO.

FIG. 8 shows a timing diagram for explaining a problem at the time of switching WORK / REF. An external write access occurs in the DRAM 1 during the WORK period, and the WORK period of the DRAM 1 is maintained for a certain period tC.
Consider the case of D extension. CACHE at this time
The write period tCWC is the standard CACHE write period tC.
It becomes WCS + tCD. When an external write access is to be processed by extending the WORK period for a certain period, the external write access does not access the DRAM 2 but writes to the CACHE 2. The problem here is the overlap of the WORK periods shown in the figure (OVER).
LAPPING period). Since the DRAM access control circuits have different processing contents in the WORK period and the REF period, the access control circuits of the DRAM 1 and the DRAM 2 try to execute the processing as the WORK period during the overlapping period of the WORK periods.

The WORK / REF switching process is the most important consideration in the principle of realizing data duplication retention using two DRAMs. WORK period tW, which is basically the processing period of two DRAMs,
RP and REF period tRFP are constantly opposite and tWR
It must be P = tRFP. This is WOR
This is especially important when external access occurs continuously during K / REF switching.

FIG. 9 shows a WORK / RE according to the present invention.
A timing diagram is shown for explaining a command generation pulse of a DRAM for an external access which is a basis of F switching extension / shortening control.

FIG. 9A shows the external write access, and the DRAM access control circuit is S
RAM interface signal S- / CE1, S-CE
An assert change of 2 and a change of S-A [24: 0] are detected, and an internally synchronized ATS pulse signal is generated. This A
An ACT command is issued to the DRAM at the falling edge of the TS pulse. DRAM column access is S- /
A rising edge of WE is detected, an internally synchronized WTS pulse signal is generated, a WR command is issued to the DRAM at the same timing, and write access is performed. In the case of write access, a write command with auto precharge is issued and precharge is automatically started after the write operation is completed.

FIG. 9B shows the external read access. Until the ACT command is issued, it is the same as the external write access described above, but the feature of the SRAM interface is that the chip is selected by S- / CE1 and S-CE2, and after the address of A [24: 0] is confirmed, S
If − / WE is at “H” level, it means that a read access is made even if S− / OE is not asserted. Therefore, after issuing the ACT command, S- / W for a certain period
If E is observed and it is at "H" level, it is determined to be a read access and an RDS pulse signal is generated. An RD command is issued to the DRAM at a timing synchronized with this RDS to perform read access. After that, if S- / WE is at "H" level, a PRS pulse signal is generated after a certain period of time, a PRE command is issued to the DRAM at the same timing, and the DRAM is issued.
Is precharged and the access to the DRAM is completed.

SRAM interface signal and DRAM
The relationship with the command is as shown in FIG. 9, and S- / C
The ACT command of the SDRAM interface is issued by detecting the change of E1, S-CE2, and SA [24: 0]. Similarly, the WRA command (write command with auto-precharge) is issued by detecting the rising edge of S- / WE. Generally, the ACT command and the PRE command are used, but in the above embodiment, the write command with auto precharge is used, and the precharge operation is automatically performed after the write operation is completed.

In the present application, tRAS (Active to Pre
The charge command period) refers to a period during which the PRA command is issued after the ACT command is issued. ACT command to start access and PRE to end access
Thinking of it as a command, it is considered to be the upper limit of the access time that this standard is generally called. Above ACT (Ro
w address strobe and bank active) command selects and activates the specified bank and row address. The PRE (Precharge select bank) command ends the operation for the bank and row address selected by the ACT command, and puts it in a state (idle state) in which the operation for another bank and row address can be started. WRA (Write with auto precharg)
The e) command is a write command with auto precharge, which automatically starts precharge after the write operation is completed and returns to the idle state.

FIG. 10 shows the WORK / R according to the present invention.
A timing diagram for explaining extension control during EF switching is shown. In this embodiment, the AT described in FIG.
The S pulse signal controls the extension of the tCWC period. Standard CACHE write period tCWCS (minimum access time according to external specifications + FIFO read / write back time) −
An example in which an ATS pulse is generated one cycle before is shown. This timing is the maximum of tCD (CACHE write period extension). Therefore, the extension cycle differs depending on the timing of the tCWCS period when the ATS pulse is asserted. Also, tC is to be noted in the figure.
The extension of D is to extend the switching of the WORK period and the REF period at the same time. WORK / REF
The problem described with reference to FIG. 8 is solved by synchronizing the switching timing of the period with the CACHE write period.
The maximum extension of the tCWCS period is defined by the external access minimum access time.

FIG. 11 shows a WORK / R according to the present invention.
A timing diagram for explaining the shortening control at the time of switching the EF is shown. In this embodiment, the standard CACHE write period tCWCS is shortened to switch the WORK / REF period. As a factor of extension, the AT indicating the start of external access as shown in FIG.
Although it was the S pulse signal, when shortened as in this embodiment, it is performed by a WTS pulse (write) and a PRS pulse (read) indicating the end of access to the DRAM. The timing when it is shortened to the maximum is when the WTS pulse or the RTS pulse is asserted at the same timing as the assertion of the tCWCS period. At this time, if the external access is write, data is written to CACHE and WOR
Change K / REF to CACHE write period tCWC
It will be synchronized with the end of the period.

In the shortening control as in this embodiment, when external access occurs continuously, the access is completed during the CACHE write period and the external access is supported at that time (WOR
This is for handing over the DRAM processing division on the (K side) and subsequent successive accesses to the DRAM which has newly become the WORK side. By this control, smooth processing can be realized for continuous access from the outside in the vicinity of WORK / REF switching.

FIG. 12 shows a WORK / RE according to the present invention.
A timing diagram for explaining extension control during F switching is shown. In this embodiment, an external write access that occurs before the standard CACHE write period tCWCS is written to DUT # CACHE after the CACHE write period tCWC extended by the maximum tCD [max] has elapsed. In the figure, an external write access occurs in the DRAM 1 during the WORK period, an ATS pulse is generated, and an ACT command is issued to the DRAM 1. Thereafter, this external write access enters the tCWCS period, and the tCWC period in which the maximum extension tCD [max] is further elapsed, and WORK / REF switching is occurring.

In this case, the write target of the external write access is DUT # CACH of the DRAM 2 on the WORK side.
Although the process shifts to E2, since the ACT command is issued in the DRAM 1 described above, the DRAM 1 side performs PR to the address immediately after switching from WORK to REF.
The E command is executed to end the processing on the DRAM 1 side. After that, this external write access is performed by WO of DRAM2.
Processing is completed during the RK period, and data is written to DUT # CACHE2 by the WTS pulse on the DRAM2 side.

FIG. 13 is a timing chart for explaining the outline of the operation of CACHE in the semiconductor memory device according to the present invention. If an external write access (W1) occurs during the WORK period of the DRAM1 and the REF period and the tCWC period of the DRAM2, the normal FIFO is used.
The data of the write access is held in the memory, but since it occurred during the tCWC period, it is not the FIFO but the DRAM 2
Held in CACHE2. After that, this CACHE data is executed by the first access which is switched to the REF period again after the DRAM 2 shifts to the WORK period.

Similarly, when an external write access (W2) occurs in the DRAM 2 in the WORK period and the DRAM 1 in the REF period and the tCWC period, the write access data is held in the CACHE 1 of the DRAM 1 as described above. Thereafter, when an external read access (R2) occurs in the address of the DRAM 1 during the WORK period, data is read from CACHE 1. At this time C
The valid bit of ACHE is not cleared, writeback to DRAM1 is executed at the beginning of the next REF period, and CAC
The valid bit in HE is cleared.

In the case of the external write access (W3), DR is written when the external write access (W3) again occurs at the relevant address after being written in CACHE2 in the same manner as described above.
Writing to AM2 is performed normally and at the same time CACHE2
Valid bit is cleared and CACHE2 becomes invalid.

FIG. 14 is a timing chart for explaining an example of the operation of DUT # CACHE. D
External write access (W
1) occurs and tC immediately before WORK / REF switching
After WC (tCWCS + tCD), WORK / RE
Long-term access that straddles F switching (S- / WE
(When crossing the WORK / REF switching), the DRAM 1 issues a PRE command to the address and ends the DRAM access in the DRAM 1.

Then, DUT # CACHE of the DRAM 2
Take over processing to 2. When the above-mentioned write access (W1) is completed in the DRAM2 during the WORK period, the write access data is held in the DUT # CACHE2 of the DRAM2 at that time. After that, when an external read access (R1) is generated at the address in the DRAM 2 during the WORK period, C is the same as described in the normal CACHE operation.
Data is read from ACHE2. Then this C
The ACHE data is executed by the first access which is switched to the REF period again after the DRAM 2 shifts to the WORK period.

FIG. 15 is a timing chart for explaining another example of the operation of DUT # CACHE. In the figure, the access for DUT # CACHE that extends over the WORK / REF period multiple times is shown. The case where the external write access (W1) occurs in the DRAM 1 during the WORK period and crosses the next WORK / REF switching is as described in FIG. 14, but the long-time access in which the WORK period of the DRAM 2 also passes. In this case, the DUT # CACHE target is taken over from DUT # CACHE2 to DUT # CACHE1. By performing this every time the work / ref is switched, virtually unlimited long-time access can be supported. The operation after the end of the access is as described above.

FIG. 16 is a flow chart for explaining the outline of the CACHE write operation. As shown in FIG. 4, the internal block of CACHE is divided into UB # CNT that controls the upper byte and LB # CNT that controls the lower byte. Here, CACH
The mask control technique for the upper byte / lower byte when E is used will also be described.

When an access occurs from outside the semiconductor memory device in STEP (step) 1, STEP (step)
At 2, it is determined whether or not it is the REF period. here,
Since the DRAM 1 or the DRAM 2 is in the mirror-related position, either CACHE always performs the operation shown in the flowchart.

In STEP (step) 3, it is determined whether or not it is the CACHE write period. Where C
When it is determined that it is the ACHE write period, the process branches by noting the byte selection signal of the access. By this, CAC from the outside in units of upper byte / lower byte
The HE control is subdivided, and data read at the time of CACHE read to the address in the WORK period and control of the CACHE valid bit at the time of writing are all performed in high byte / low byte units.

When it is judged in STEP (step) 4 that the byte is selected, the WTS pulse signal indicating the write state is asserted, and each write data is CA.
Write to CHE. Also, the CACHE valid bit is provided in units of upper byte and lower byte,
The logical sum is output to the DRAM access control circuit.

FIG. 17 is a flow chart for explaining another outline of the CACHE write operation. When an access is made from outside the semiconductor memory device in STEP1, it is determined in STEP2 whether or not it is the WORK period. In STEP 3, it is judged whether CACHE is valid or not, and in STEP 4, the process branches to upper byte / lower byte processing, and if the byte is selected, S
Address comparison and matching is performed at TEP5. Where C
When ACHE hits, WT showing write state
The valid bit of CACHE is cleared after the assertion of the S pulse signal. In STEP8, the effective bit of the upper byte and the lower byte is ORed, and this is DRA
Output to the M access control circuit.

Further, the case where the upper byte and the lower byte of CACHE are operated independently will be described. It is assumed that the state when writing to CACHE during the CACHE write period of the REF period has selected both the upper byte and the lower byte. If a write access occurs at the address in the next WORK period and only the upper byte or the lower byte is selected for this access, the selected byte side is written in the DRAM at this time. The valid bit of CACHE is cleared, but the byte that has not been selected is not written, so the valid bit remains unchanged. Result CACHE
The entire valid bit is not cleared and only the first unselected byte side of the next REF period is written back.

FIG. 18 shows the CACH during the WORK period.
A flow chart diagram for explaining the concept of the read operation to E is shown. If an access is generated from outside the semiconductor memory device in STEP 1, WORK is performed in STEP 2.
Determine whether it is a period. CAC in STEP3
It is judged whether HE is effective or not.

If the byte is selected in STEP 4, the process is branched to the upper byte and the lower byte, and if the byte is selected, STEP 5 is executed.
The address is compared and matched at. CACHE here
When a hit occurs, the data output (CACDATA) of CACHE and CACHIT which is the read hit signal of CACHE are output to the DRAM access control circuit after the assertion of CACRD indicating the read state of CACHE. At this time, the access control circuit of the DRAM itself is also operating and issues a read command to the DRAM, but the read data from CACHE is selected or DR
C for the selection signal to select the read data from AM
CACHIT which is an ACHE read hit signal is used.

Further, let us consider a case where the valid bit of CACHE is only one of the upper byte and the lower byte and the byte selection signal for read access is selected for both the upper byte and the lower byte. In this case, CACH
For byte data on the side where the valid bit of E is cleared, read from DRAM is selected and byte data on the side where the valid bit of CACHE is set is CAC.
The read data from the HE is selected and output to the outside.

FIG. 19 is a flow chart for explaining the concept of the write back operation of CACHE. When WORK / REF switching occurs in STEP1, the CACHE in STEP2 is the DRA that it is in charge of.
It is determined whether the M side is in the REF period. STE
At P3, it is determined whether or not a valid bit is set. At this time, the valid bit (CAC
The DRAM access control circuit also makes a similar determination based on V), and if CACHE is valid, CACHE
CACRD which is a read signal is asserted.

In STEP 4, CACHE is the DR described above.
CACHE read signal CA from AM access control circuit
Wait for CRD. In STEP 5, CACHE read signal CA
Output CACHE data to CRD, and STEP
At 6, the valid bit of CACHE is cleared. The DRAM access control circuit uses D based on the output data of CACHE.
Write back access to the RAM.

The basic operation of DUT CACHE is similar to that of normal CACHE, but the signal indicating the write period is different. (CACHE write period = CACPRD) /
(DUT # CACHE write period signal = DUTPRD)
.

DRAM1 and DRAM2 are CACs, respectively.
Although HE and DUT CACHE are provided, both do not have the valid bit set at the same time during the WORK period. This is because the period in which the data is written is different in both, and CACHE is written in the REF period, whereas DUT CACHE is written in the WORK period. Therefore, the CA of DRAM1
DUT CACH of DRAM 2 when CHE is enabled
It is possible that E will be valid. Naturally DRAM1 and DR
There is also a case where AM2 is reversed. However, C of DRAM1
ACHE and DUT CACHE, similarly DRAM2
CACHE and DUT CACHE cannot be valid for the same period.

CACHE and DUT CACH described above
According to the control method of E, when the access from the outside of the semiconductor device is made, the existing SRAM interface remains unchanged and the DRA
In a semiconductor memory device using M, a control method compatible with long-time access is realized. This is a general-purpose DR
AM and general-purpose SDRAM, DRAM such as embedded DRAM
It is an effective means for all SRAM compatible memories realized by using elements. As for this control method, it has been confirmed that the control method described by constructing an actual circuit with an FPGA and a prototype chip is effective.

FIG. 20 is a plan view of an embodiment of the semiconductor memory device according to the present invention, and FIG.
A sectional view taken along the line A'is shown. Semiconductor chips CHIP2 (DRAM1) and CHIP2 (D
RAM2) and semiconductor chip CHIP1 (CTL_LO
GIC) is installed. These semiconductor chips CHIP
The electrodes 1 to CHIP3 are bonded to the electrodes of the wiring provided on the mounting board by bonding wires PAHT1 and PATH.
It is connected by 2 etc. These semiconductor chips CHIP
1 to 3 are formed by the sealing body COVER and are regarded as one semiconductor integrated memory device in appearance. Although not particularly limited, a ball-shaped external electrode is provided on the back surface side of the mounting substrate, and an external terminal for an interface corresponding to the SRAM and an external terminal for power supply are provided.

FIG. 22 is a plan view of another embodiment of the semiconductor memory device according to the present invention, and FIG.
The -A 'line sectional view is shown. On the mounting board PCB,
Semiconductor chips CHIP2 (DRAM1) and CHIP3
(DRAM2) is mounted. Then, on these two semiconductor chips CHIP2 and CHIP3, the semiconductor chip CHIP1 (CTL_LOG) is arranged so as to straddle them.
IC) is mounted in a laminated structure. Corresponding electrodes of these semiconductor chips CHIP1 and 2 and CHIP3 are connected by a bonding wire PAHT4, and an electrode of an interface corresponding to the SRAM of CHIP1 is connected to an electrode of a mounting board by a bonding wire PATH2. Other configurations are similar to those in FIGS. 20 and 21.

When the above multi-chip structure is adopted, it is convenient for mounting on a small portable electronic device. Since the small portable terminal has a limited mounting space, it is completely equivalent to the SRAM as described above, and about 10
A memory circuit having about double the storage capacity can be constructed. For example, SRAM is about 16M by one memory chip.
The DRAM chip can realize a storage capacity of about 256 Mbits, while the memory capacity of only about a bit can be realized. Even if two memory chips store data in duplicate, the storage capacity is about 10 times. Can be realized.

Two DRAMs are used as a control and structure technology for making a large-capacity SRAM-compatible module using DRAMs.
Work tip (WORK) period and refresh (RE
F) The work / refresh using the cache (CACHE) can be extended or shortened when switching to the period, and smooth access control at the time of switching can be performed. DR
A long-time access exceeding the access time limit tRAS of AM can be realized by cache control realized by using a takeover cache DUT CACHE. Further, it becomes possible to perform mask control of the upper byte and the lower byte when using the cache.

According to the present invention, a large capacity SRAM compatible memory module can be realized by using a DRAM, particularly an existing or general-purpose DRAM, and adding a simple control chip thereto. In other words, the SRAM compatibility can be ensured by facilitating the work / refresh switching, and the functions of the SRAM compatible module without access time limitation and the SRAM compatible module by controlling the upper byte / lower byte can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, DR
The AM refresh control may be realized by issuing a refresh command that activates the refresh control circuit of the DRAM itself. That is,
In the REF period, the memory control circuit CTL_L
The OGIC may issue the refresh command at a constant cycle. Between the refresh commands, the write back operation may be performed according to the storage information stored in the FIFO or CACHE.

Each of the DRAMs 1 and 2 may be one chip or a plurality of chips. DR
The AM1 and the DRAM2 may be one DRAM chip. In other words, when one DRAM chip has a plurality of banks that can be independently accessed for memory, the control chip divides the bank into two groups, and one of the banks is set to the D
The RAM 1 may be used and the other may be controlled like the DRAM 2. A DRAM chip having such a plurality of banks may have the function of a control chip built therein.

In the above embodiment, the DRAM is operated by a command, that is, a so-called synchronous DRAM, but the present invention is not limited to this, and RAS, CAS, W are provided.
The memory may be controlled by a control signal such as E. INDUSTRIAL APPLICABILITY The present invention can be widely used for an SRAM compatible semiconductor memory device using a DRAM and a control method thereof.

[0068]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. Two DRs as control and structure technology for modularization of a large-capacity SRAM compatible module using DRAM
The AM chip is alternately switched between the work (WORK) period and the refresh (REF) period, and the write-back by the FIFO is performed to the DRAM in the refresh period, and when the switching is performed, the write-back using the cache and the work / refresh are extended or The takeover cache can be used for long-time access exceeding the access time limit tRAS of the DRAM while smoothing the access at the time of switching by the shortening control.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a semiconductor memory device according to the present invention.

2 is a block diagram showing an embodiment of CHIP1 (CTL # LOGIC) of FIG. 1. FIG.

3 is a block diagram showing an embodiment of CTL # LOGIC of FIG. 2. FIG.

FIG. 4 is a block diagram showing an embodiment of CACHE in FIG.

FIG. 5 is a timing diagram for explaining the concept of WORK / REF period switching for duplicating data and concealing refresh using two DRAMs.

FIG. 6 is a timing chart for explaining holding of write back data.

FIG. 7 is a timing chart for explaining holding of write back data.

FIG. 8 is a timing chart for explaining a problem at the time of switching WORK / REF.

FIG. 9 is a DRAM for external access, which is the basis of WORK / REF switching extension / shortening control according to the present invention.
5 is a timing diagram for explaining the command generation pulse of FIG.

FIG. 10 is a timing chart for explaining extension control at the time of WORK / REF switching according to the present invention.

FIG. 11 is a timing chart for explaining shortening control at the time of WORK / REF switching according to the present invention.

FIG. 12 is a timing chart for explaining extension control at the time of WORK / REF switching according to the present invention.

FIG. 13 is a diagram showing a CA in the semiconductor memory device according to the present invention.
It is a timing diagram for explaining an outline of the operation of CHE.

FIG. 14 is a timing chart for explaining an example of the operation of DUT # CACHE according to the present invention.

FIG. 15 is a timing chart for explaining another example of the operation of DUT # CACHE according to the present invention.

FIG. 16 is a flow chart diagram for explaining an outline of a write operation of CACHE according to the present invention.

FIG. 17 is a flow chart diagram for explaining another outline of the write operation of CACHE according to the present invention.

FIG. 18: CACH in the WORK period according to the present invention
FIG. 7 is a flowchart diagram for explaining the concept of a read operation to E.

FIG. 19 is a flow chart diagram for explaining the concept of the write back operation of CACHE according to the present invention.

FIG. 20 is a plan view showing an embodiment of a semiconductor memory device according to the present invention.

FIG. 21 is a structural cross-sectional view of an example corresponding to the line AA ′ in FIG. 20.

FIG. 22 is a plan view showing another embodiment of the semiconductor memory device according to the present invention.

FIG. 23 is a structural cross-sectional view of one example corresponding to the line AA ′ in FIG. 22.

[Explanation of symbols]

CHIP2 (DRAM1), CHIP3 (DRAM2)
... DRAM chip, CHP3 (CTL_LOGIC) ...
Control chip, SDCTL ... Access control circuit, WRBR
EG ... Register, TIMECNT ... Time control circuit, AT
D ... Address signal change detection circuit, DTD ... Signal change detection circuit, R / W BUFFER ... Read / write buffer, INT ... Initial circuit circuit, TMP ... Temperature measurement module, RC ... Refresh counter circuit, PM ... Power supply circuit, CLK # GEN ... Clock generation circuit, PATH1 to
4 ... Bonding wire, COVER ... Sealing body.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G11C 11/401 G11C 11/34 371Z (72) Inventor Tetsuya Iwamura 5-22, Kamimizumotocho, Kodaira-shi, Tokyo No. 1 within Hitachi Super L.S.I.Systems Co., Ltd. (72) Inventor Koichi Hoshi 5-22-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Super L.S.I.Systems Co., Ltd. (72) Inventor Miura 1-280, Higashi Koikeku, Kokubunji, Tokyo, Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Aikawa, 1-280, Higashi Koikeku, Kokubunji, Tokyo F-Term, Hitachi, Ltd. Reference) 5B005 JJ11 MM01 NN02 NN71 UU24 5B060 CA10 5M024 AA49 AA50 AA90 BB22 BB26 BB27 BB30 BB35 BB36 BB39 DD85 EE10 EE12 EE30 JJ22 KK22 KK40 LL01 PP01 PP05 PP07 PP10

Claims (16)

[Claims] 1. A first memory device and a first memory device, each of which has a storage unit configured to store the same data and has the same address space composed of dynamic memory cells, each of which is independently writable / readable. 2 memory circuits and a memory control circuit for controlling write / read and refresh operations for the first and second memory circuits, wherein the memory control circuit is an input / output device compatible with a static RAM. An interface circuit, a cache memory provided corresponding to each of the first and second memory circuits, and an FIF commonly used for the first and second memory circuits
O memory, and time allocation for enabling normal operation of writing / reading to one of the first and second memory circuits and instructing refresh operation to the other memory circuit. When the memory operation is instructed by the input / output interface circuit by performing the control alternately, the write / read operation is performed on the one memory circuit to store the write information for the one memory circuit in the FIFO memory. , F between the refreshes of the other memory circuit
When the write operation is performed according to the write information of the IFO memory, and the write operation is instructed by the input / output interface circuit during a certain period before transition from the refresh operation to the normal operation in each of the first and second memory circuits. , A write operation is performed on the one memory circuit, write information for the one memory circuit is stored in the cache memory corresponding to the other memory circuit for which the refresh is instructed, and the normal operation after the switching is performed. When there is a read operation for the address stored in the cache memory in, the data stored in the cache memory is output instead of the other memory circuit, and another data is written to the address stored in the cache memory. When is instructed Data is written to the other memory circuit, the write information in the cache memory is invalidated, and the memory access is not performed to the address stored in the cache memory for the other memory circuit. In some cases, the semiconductor memory device is characterized in that a data write operation is performed corresponding to write information of the cache memory between refresh operations in the next refresh period of the other memory circuit. 2. The semiconductor memory device according to claim 1, wherein the refresh period is set shorter than the longest active period in the first and second memory circuits. 3. The first and second memories according to claim 2, wherein the memory control circuit uses the switching time at which the refresh operation in each of the first and second memory circuits shifts to a normal operation as a reference. When the start of the write operation is instructed by the input / output interface circuit before a fixed time shorter than the minimum write time of the circuit, the switching time is extended corresponding to the minimum write time of the first and second memory circuits. A semiconductor memory device characterized by: 4. The memory control circuit according to claim 2, wherein the memory control circuit uses the switching time at which the refresh operation in each of the first and second memory circuits shifts to a normal operation as a reference. When the end of the memory operation by the input / output interface circuit is instructed before a fixed time shorter than the minimum write time of the circuit, the switching time is shortened corresponding to the minimum write time of the first and second memory circuits. A semiconductor memory device characterized by: 5. The cache memory according to claim 2, wherein the cache memory provided corresponding to each of the first and second memory circuits includes a takeover memory section, and one of the first and second memory circuits is a memory. When the write operation written in the cache memory is not confirmed during the refresh period for the circuit, the write information is transferred to the inherited memory unit corresponding to the other memory circuit at the next switching. apparatus. 6. The memory device according to claim 2, wherein the first and second memory circuits are composed of semiconductor chips that compose an existing dynamic RAM, and the memory control circuit is composed of one semiconductor chip. A semiconductor memory device, wherein semiconductor chips are housed in a single package by a multi-chip technology. 7. The semiconductor memory device according to claim 2, wherein the cache memory is provided with a storage portion for a control signal for operating the upper byte and the lower byte independently. 8. A first section and a first section, each of which has a storage unit configured to store the same data and has the same address space composed of dynamic memory cells, each of which is independently writable / readable. A second memory circuit, an input / output interface circuit corresponding to a static RAM, a cache memory provided corresponding to each of the first and second memory circuits, and the first and second memory circuits. A commonly used FIFO memory is provided for writing / writing to the first and second memory circuits.
A memory control circuit for controlling read and refresh operations is used to enable write / read normal operation for one of the first and second memory circuits and for the other memory circuit. The time allocation control for instructing the refresh operation is alternately performed, and when the memory operation is instructed by the input / output interface circuit, the write / read operation is performed for the one memory circuit and the memory circuit for the one memory circuit is performed. The write information is stored in the FIFO memory, and the F information is stored between the refresh operations of the other memory circuit.
When the write operation is performed according to the write information of the IFO memory, and the write operation is instructed by the input / output interface circuit during a certain period before transition from the refresh operation to the normal operation in each of the first and second memory circuits. , A write operation is performed on the one memory circuit, write information for the one memory circuit is stored in the cache memory corresponding to the other memory circuit for which the refresh is instructed, and the normal operation after the switching is performed. When there is a read operation for the address stored in the cache memory in, the data stored in the cache memory is output instead of the other memory circuit, and another data is written to the address stored in the cache memory. When is instructed Data is written to the other memory circuit, the write information in the cache memory is invalidated, and the memory access is not performed to the address stored in the cache memory for the other memory circuit. Sometimes, a method of controlling a semiconductor memory device is characterized in that a data write operation is performed corresponding to write information of the cache memory between refresh operations in the next refresh period of the other memory circuit. 9. The method for controlling a semiconductor memory device according to claim 8, wherein the refresh period is set shorter than a longest active period in the first and second memory circuits. 10. The first and second memories according to claim 9, wherein the memory control circuit is based on a switching time at which the refresh operation in each of the first and second memory circuits shifts to a normal operation. When the start of the write operation is instructed by the input / output interface circuit before a fixed time shorter than the minimum write time of the circuit, the switching time is extended corresponding to the minimum write time of the first and second memory circuits. A method for controlling a semiconductor memory device, comprising: 11. The memory control circuit according to claim 9, wherein the memory control circuit uses the switching time at which the refresh operation in each of the first and second memory circuits shifts to a normal operation as a reference. When the end of the memory operation by the input / output interface circuit is instructed before a fixed time shorter than the minimum write time of the circuit, the switching time is shortened corresponding to the minimum write time of the first and second memory circuits. A method for controlling a semiconductor memory device, comprising: 12. The cache memory provided corresponding to each of the first and second memory circuits is provided with a takeover memory section, and one of the first and second memory circuits is provided. When the write operation written in the cache memory is not confirmed in the refresh period for the semiconductor memory device, the write information is transferred to the inherited memory unit corresponding to the other memory circuit at the next switching. Control method. 13. A semiconductor memory device having a plurality of dynamic memory cells and a control circuit for controlling a refresh operation, wherein a tRAS period is longer than a refresh cycle of the memory cells. 14. The semiconductor memory device according to claim 13, further comprising a cache memory, wherein the cache memory holds data to be written back to the plurality of dynamic memory cells. 15. A first memory having a plurality of dynamic type memory cells, a second memory having a plurality of dynamic type memory cells, and a control circuit, wherein: A refresh operation is performed, a write / read operation is performed on the second memory, and in a second state, a refresh operation is performed on the second memory and a write / read operation is performed on the first memory, A semiconductor memory device capable of changing a cycle of switching between the first state and the second state by the control circuit. 16. The semiconductor memory device according to claim 15, wherein the first memory and the second memory are respectively formed in first and second semiconductor chips having the same capacity.