JP2015079293A - Memory control device, memory control method, and information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory control device and others which can control a memory at high speed.SOLUTION: A memory control device 101 comprises a request control unit 102 which, in response to a request 105 to execute processing, executes the processing in a first memory which is in a first state neither executing refresh processing nor executing write-back processing, among a plurality of redundant memories.

Description

  The present invention relates to a memory control device and the like for controlling a memory having redundancy.

  The performance of transmitting and receiving information between the main storage device (hereinafter referred to as “memory”) and the processor affects the performance related to the computer (information processing device).

  On the other hand, the memory is often a Dynamic Random Access Memory (hereinafter referred to as “DRAM”). Since DRAM stores information by holding electric charge in a capacitor, refreshing that periodically replenishes electric charge is necessary to continue storing information.

  However, as the memory capacity increases, the processing time for refreshing the memory increases. A device such as a processor cannot access information in the memory while refreshing the memory. As a result, as the memory capacity increases, the time during which information in the memory cannot be accessed increases.

  On the other hand, there is memory mirroring as one means for providing fault tolerance. Memory mirroring is a technique for improving the reliability of a memory by allowing an information processing apparatus to store one piece of information redundantly in a plurality of memories.

  For this reason, when storing information, the computer executes a lock step for executing the same processing on a plurality of memories. The computer detects that the memory is abnormal when the operation is different even though the same processing is executed for a plurality of memories. The computer refreshes the plurality of memories at the same time when executing the lock step for the plurality of memories.

  Patent Document 1 discloses a mirroring control device that realizes mirroring using a lock step. The mirroring control device refreshes a plurality of memories at the same time by executing a lock step.

  On the other hand, the data control method disclosed in Patent Document 2 is a method of reading information from a memory that is not being refreshed among a plurality of memories in a mirroring state in response to a read request for reading information.

JP 2011-048742 A JP 2012-022754 A

  The computer cannot access information in the memory while refreshing the memory.

  This situation also occurs when the computer has multiple memories. For example, since the mirroring control device disclosed in Patent Document 1 refreshes a plurality of memories at the same time as described above, information in the memories cannot be accessed. For this reason, the information processing apparatus cannot access information in the memory even when it has a plurality of memories.

  On the other hand, since the data control method disclosed in Patent Document 2 is the control method as described above, information in the memory can be read during refresh. However, the data control method stores information in the memory after the refresh is completed. For this reason, in this method, information cannot be stored in the memory during refresh.

  Therefore, the techniques disclosed in Patent Document 1 and Patent Document 2 do not always bring out the performance of the memory.

  Accordingly, a main object of the present invention is to provide a memory control device and the like for controlling the memory at high speed.

  In order to achieve the above object, a memory control device according to the present invention comprises the following arrangement.

That is, the memory control device according to the present invention is
In response to a request for processing, a request for executing the processing in a first memory in a first state in which refresh is not being executed and write back is not being executed among a plurality of memories having redundancy A control unit is provided.

As another aspect of the present invention, a memory control method according to the present invention includes:
In response to a request for processing using an information processing device, in a first memory in a first state in which refresh is not being executed and write back is not being executed among a plurality of memories having redundancy The above process is executed.

  The memory control device and the like according to the present invention can control the memory at high speed.

It is a block diagram which shows the structure which the memory control apparatus which concerns on the 1st Embodiment of this invention has. It is a flowchart which shows the flow of a process in the memory control apparatus which concerns on 1st Embodiment. It is a block diagram which shows the structure which a memory control apparatus has. It is a block diagram which shows the structure which the memory control apparatus which concerns on the 2nd Embodiment of this invention has. It is a flowchart which shows the flow of a process in the memory control apparatus which concerns on 2nd Embodiment. It is a block diagram which shows the structure which the memory control apparatus which concerns on the 3rd Embodiment of this invention has. 14 is a flowchart illustrating a flow of processing in the memory control device according to the third embodiment. It is a sequence diagram which shows the flow of a process in the memory control apparatus which concerns on 3rd Embodiment.

  Next, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

<First Embodiment>
The configuration of the memory control device 101 according to the first embodiment of the present invention and the processing performed by the memory control device will be described in detail with reference to FIG. 1 and FIG. FIG. 1 is a block diagram showing the configuration of the memory control apparatus 101 according to the first embodiment of the present invention. FIG. 2 is a flowchart showing the flow of processing in the memory control apparatus 101 according to the first embodiment.

  The memory control device 101 according to the first embodiment includes a request control unit 102.

  For convenience of explanation, it is assumed that the memory control device 101 controls the memory 103 and the memory 104. However, the memory control device 101 may control three or more memories.

  Further, the memory 103 and the memory 104 are assumed to have redundancy. In this case, the memory 103 and the memory 104 may be mirrored based on the lock step as described in “Background Art”, or the memory 103 and the memory 104 may be mirrored based on the method disclosed in Patent Document 2. 104 may be mirrored. That is, the means for achieving redundancy is not limited to the processing described above.

  First, the request control unit 102 receives a request 105 for requesting processing, and in response to the received request 105, the memory 103 and the memory 104 are not performing refreshing, and updated information is displayed. It is checked whether or not the first state in which the write-back stored in the memory is not being executed (step S201). The request control unit 102 may select the first state memory. A plurality of memories (in this example, the memory 103 and the memory 104) recover redundancy by write back. The request 105 is a request for reading information from the memory (the memory 103 and the memory 104) (hereinafter, referred to as “read request”), and a request for storing information in the memory (hereinafter, “write request”). ) Etc.

  For convenience of explanation, the memory in the first state is hereinafter referred to as a first memory.

  Next, the request control unit 102 executes processing corresponding to the request in the first memory among the memory 103 and the memory 104 (step S202).

  That is, if the request is a read request, the request control unit 102 reads information from the first memory. Alternatively, if the request is a write request, the request control unit 102 stores information in the first memory.

  As described above, the memory control device 101 executes processing such as reading information or storing information in the first memory in the first state from among the plurality of memories. Even if refresh or write-back is being executed in the memory 103, the memory control device 101 accesses information with the memory 104. That is, according to the memory control device 101, access to information in the memory is not hindered by processing such as refresh.

  On the other hand, as described above, in the technologies disclosed in Patent Documents 1 and 2, access to information in the memory is hindered by refreshing or the like as shown in “Problems to be Solved by the Invention”.

  That is, according to the memory control device 101 according to the first embodiment, the memory can be controlled at high speed.

  In the above description, the request control unit 102 controls the memory 103 and the memory 104, but the mode shown in FIG. FIG. 3 is a block diagram illustrating a configuration of the memory control device 304.

  That is, the memory control device 304 may include the request control unit 102, the channel control unit 301, and the channel control unit 302. The channel control unit 301 controls the memory 103. The channel control unit 302 controls the memory 104.

  Further, the information processing device 303 includes a memory control device 304, a memory 103, and a memory 104. The request 105 does not need to be a request requested in the information processing apparatus 303, and may be a request received from a different information processing apparatus (not shown).

  In this case, the memory control device 304 instructs the channel control unit 301 and the channel control unit 302 to perform the processing as described above.

<Second Embodiment>
Next, a second embodiment of the present invention based on the first embodiment described above will be described.

  In the following description, the characteristic part according to the present embodiment will be mainly described, and the same components as those in the first embodiment described above will be denoted by the same reference numerals, and redundant description will be omitted. To do.

  With reference to FIGS. 4 and 5, the configuration of the memory control device 401 according to the second embodiment and the processing performed by the memory control device 401 will be described. FIG. 4 is a block diagram showing a configuration of the memory control device 401 according to the second embodiment of the present invention. FIG. 5 is a flowchart showing the flow of processing in the memory control device 401 according to the second embodiment.

  The memory control device 401 includes a request control unit 402.

  After executing the process in the first memory (step S202), the request control unit 402 changes the second memory according to the second memory being a memory other than the first memory among the plurality of memories being in the first state. In step S503, a process corresponding to the request 105 is executed.

  When the request control unit 402 processes step S201, the second memory is refreshing or writing back. The request control unit 402 executes the process executed in the first memory in the second memory in response to the end of the refresh or write back in the second memory.

  Since the memory control device 401 according to the second embodiment includes the same configuration as that of the first embodiment, the second embodiment can enjoy the same effects as those of the first embodiment. That is, the memory control device 401 according to the second embodiment can control the memory at high speed.

  Further, after the memory control device 401 executes step S503, the same information is stored in a plurality of memories. That is, the plurality of memories have redundancy. As a result, the memory control device 401 according to the present embodiment can read information from other memories when a part of the memory fails. Therefore, according to the memory control device 401 according to the present embodiment, the reliability of the information processing device (not shown) is further increased.

<Third Embodiment>
Next, a third embodiment of the present invention based on the first embodiment described above will be described.

  In the following description, the characteristic part according to the present embodiment will be mainly described, and the same components as those in the first embodiment described above will be denoted by the same reference numerals, and redundant description will be omitted. To do.

  The configuration of the memory control device 606 according to the third embodiment and the processing performed by the memory control device will be described with reference to FIG. FIG. 6 is a block diagram showing a configuration of the memory control device 606 according to the third embodiment of the present invention.

  The memory control device 606 according to the third embodiment includes a request control unit 601. The request control unit 601 includes a monitoring unit 602, an issuing unit 603, a reply unit 604, and a buffer 605.

  The memory control device 606 may further include a channel control unit 301 and a channel control unit 302.

  The monitoring unit 602 monitors the state in the memory 103 and the memory 104. That is, the monitoring unit 602 monitors whether the memory 103 and the memory 104 are performing refresh, write back, or the first state.

  In response to the request 105, the issuing unit 603 selects the first memory in the first state based on the state monitored by the monitoring unit 602, and executes the process according to the request 105 in the selected first memory. At the same time, the issuing unit 603 stores the request 105 in the buffer 605.

  Next, the issuing unit 603 detects that the state in the second memory becomes the first state by referring to the state monitored by the monitoring unit 602. The issuing unit 603 reads the request 105 from the buffer 605 in response to the state in the second memory being changed to the first state, and executes processing corresponding to the read request 105 in the second memory.

  The reply unit 604 receives a read reply related to the information read from the memory 103 and the memory 104 by the channel control unit 301 or the channel control unit 302, and compares the received information, thereby generating an error related to the memory 103 and the memory 104. Detect. The reply unit 604 determines that there is an error when the information does not match, and determines that there is no error when the information matches.

  When the reply unit 604 determines that an error has occurred, the reply unit 604 transmits error information regarding the error to the issuing unit 603. The issuing unit 603 receives the error information and identifies a read request related to the error based on the received error information. Next, the issuing unit 603 reads the read request specified from the buffer 605 and requests the read read request to the channel control unit 301 or the channel control unit 302 again.

  Next, in the case of “case 1” to “case 3”, processing executed by the memory control device 606 will be described with reference to FIG. FIG. 8 is a sequence diagram showing a flow of processing in the memory control device 606 according to the third embodiment.

Case 1: The memory 103 and the memory 104 are in the first state.
Case 2: Refresh (or write back) is being executed in the memory 103. The memory 104 is in the first state.
Case 3: Refresh is being executed in the memory 103. A write back is being executed in the memory 104.

  Since the memory 103 and the memory 104 can be handled in the same manner, for example, when “write back is being executed in the memory 104. The memory 103 is in the first state”, case 2 This is the same processing as in FIG. That is, the processing in the memory control device 606 is not limited to the case classification described above.

(In case 1)
The issuing unit 603 executes processing according to the request in the memory 103 and the memory 104. If the request is a write request (write request 3), the issuing unit 603 stores information in the memory 103 and the memory 104 (steps S807 and S813). When the request is a read request, the issuing unit 603 reads information from at least one of the memory 103 and the memory 104. For this reason, the memory 103 and the memory 104 have redundancy.

(Case 2)
Since the memory 104 is in the first state, the issuing unit 603 executes processing according to the request in the memory 104 and stores the request in the buffer 605. When the request is a write request (write request 1), the issuing unit 603 stores information in the memory 104 (step S809) and stores the write request in the buffer 605 (step S801).

  Next, the issuing unit 603 reads a write request from the buffer 605 in response to completion of the refresh in the memory 103 (step S803), and stores information in the memory 103 in response to the write request. That is, the issuing unit 603 executes write back in the memory 103 (step S804).

  If the issuing unit 603 receives another request before executing the write back in the memory 103, the issuing unit 603 postpones the process until the write back is completed.

  When the request is a read request (read request 1 and read request 3), the issuing unit 603 reads information from the memory 104 (steps S808 and S810).

(Case 3)
Since the information in the memory 103 and the memory 104 cannot be accessed, the issuing unit 603 postpones processing according to the request until a specific memory among the plurality of memories is in the first state (not illustrated in FIG. 8).

  In the case 2, the memory 104 is in the first state, but the same processing is performed when the memory 103 is in the first state.

  That is, since the memory 103 is in the first state, the issuing unit 603 executes processing according to the request in the memory 103 and stores the request in the buffer 605. When the request is a write request (write request 2), the issuing unit 603 stores information in the memory 103 (step S805) and stores the write request in the buffer 605 (step S802).

  Next, the issuing unit 603 reads a write request from the buffer 605 in response to completion of the refresh in the memory 104 (step S811), and stores information in the memory 103 in response to the write request. That is, the issuing unit 603 performs write back in the memory 103 (step S812).

  If the issuing unit 603 receives another request before executing the write back in the memory 103, the issuing unit 603 postpones the process until the write back is completed.

  If the request is a read request (read request 2), the issuing unit 603 reads information from the memory 104 (step S806).

  Next, processing in write back will be described with reference to FIG. FIG. 7 is a flowchart showing a flow of processing in the memory control device 606 according to the third embodiment.

  In the memory, after executing refresh, write back is executed. The issuing unit 603 determines whether there is a request in the buffer 605 (step S901). When determining that there is a request (YES in step S901), the issuing unit 603 performs processing according to the request in the second memory based on the state in the second memory (step S902).

  The issuance unit 603 stores the request in the buffer 605 when there is another request while processing steps S901 and S902.

  If the issuing unit 603 determines that there is no request (NO in step S901), the issuing unit 603 does not execute the process in step S902.

  Since the memory control device according to the third embodiment includes the same configuration as that of the first embodiment, the third embodiment can enjoy the same effects as those of the first embodiment. That is, according to the memory control device according to the third embodiment, the memory can be controlled at high speed.

  Further, when the request is a read request, the memory control device 606 reads information from the memory in the first state among the plurality of memories. In this case, according to the memory control device according to the present embodiment, the write back process is not necessary as described above, and therefore the memory can be controlled at higher speed.

  The buffer 605 may include a read buffer that can store a read request and a write buffer that can store a write request. In this case, the memory control device 606 stores the read request in the read buffer when receiving the read request, and stores the read request in the write buffer when receiving the write request. Furthermore, the memory control device 606 executes processing corresponding to the write request and the read request in the write buffer and the read buffer, respectively.

DESCRIPTION OF SYMBOLS 101 Memory control apparatus 102 Request control part 103 Memory 104 Memory 105 Request 301 Channel control part 302 Channel control part 303 Information processing apparatus 304 Memory control apparatus 401 Memory control apparatus 402 Request control part 601 Request control part 602 Monitoring part 603 Issuing part 604 Reply Unit 605 Buffer 606 Memory control device

Claims (10)

In response to a request for processing, a request for executing the processing in a first memory in a first state in which refresh is not being executed and write back is not being executed among a plurality of memories having redundancy A memory control device comprising a control unit. The request control unit executes the processing in the second memory in response to a second memory being a memory other than the first memory among the plurality of memories being in the first state. 2. The memory control device according to 1. The request control unit
A buffer capable of storing the request;
A monitoring unit for monitoring a memory state in the plurality of memories;
In response to the request, the first memory is selected based on the state, the process is executed in the first memory, the request is stored in the buffer, and the second memory is in the first state. 3. The memory control device according to claim 1, further comprising: an issuing unit that reads the request from the buffer according to and executes the process according to the read request in the second memory. . The buffer is
A read buffer capable of storing a read request requesting a reading process for the plurality of memories;
A write buffer capable of storing a write request for requesting processing to be stored in the plurality of memories, and
The issuing unit
If the request is the read request, store the read request in the read buffer;
If the request is the write request, store the write request in the write buffer;
When reading from the read buffer, execute the process according to the read process,
The memory control device according to claim 3, wherein when reading from the write buffer, the processing according to the processing to be stored is executed. 5. The memory control device according to claim 3, wherein, in the plurality of memories, when the first memory is not present, the issuing unit performs the processing according to the first state. 6.   An information processing apparatus comprising the memory control apparatus according to claim 1.   In response to a request for processing using an information processing device, in a first memory in a first state in which refresh is not being executed and write back is not being executed among a plurality of memories having redundancy A memory control method for executing the processing. The memory control according to claim 7, wherein the processing is executed in the second memory in response to a second memory being a memory other than the first memory being in the first state among the plurality of memories. Method. The information processing apparatus includes a buffer capable of storing the request,
The memory states of the plurality of memories are monitored, and the first memory is selected based on the state according to the request, and the processing is executed in the first memory, and the request is stored in the buffer. 8. The request is read from the buffer in response to the second memory being in the first state, and the processing according to the read request is executed in the second memory. 9. The memory control method according to 8. The buffer is
A read buffer capable of storing a read request requesting a reading process for the plurality of memories;
A write buffer capable of storing a write request for requesting processing to be stored in the plurality of memories, and
When the request is the read request, the read request is stored in the read buffer, and when the request is the write request, the write request is stored in the write buffer and read from the read buffer. The memory control method according to claim 9, wherein the processing according to the reading process is executed, and the processing according to the storing process is executed when reading from the write buffer.

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