JP2003289222A - Inversion amplifier with mute function, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide superior mute characteristics in a simple circuit constitution, and to prevent an increase in power consumption. <P>SOLUTION: When a mute control signal MCNT is shifted from L to H for instructing the change from a signal output state to a mute state, a second switch SW2 is turned off, according to two switch control signals generated from a timing control circuit 10, and then a first switch SW1 is turned off. When the mute control signal MCNT is shifted, from H to L for instructing the change from the mute state to a signal output state, the first switch SW1 is turned on at first, so that the potential at a point B is returned to an analog ground potential through an input resistor R1, and then the second switch SW2 is turned on. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverting amplifier with a mute function and a semiconductor device. More specifically, the present invention provides a MOS on a semiconductor substrate, for example.
The present invention relates to an inverting amplifier with a mute function formed as an LSI circuit, and a semiconductor device including the inverting amplifier.

[0002]

2. Description of the Related Art FIG. 1 shows an example of a conventionally known inverting amplifier with a mute function. In the circuit shown in the figure, the first resistor R1 and the first switch S connected in series are connected.
The input signal V _IN is input to an inverting input terminal of an operational amplifier (hereinafter referred to as an operational amplifier) via W1. The second resistor R2 as a feedback resistor is connected between the output terminal and the inverting input terminal of the operational amplifier OP. Then, the opening / closing of the first switch SW1 is controlled in response to the level change of the mute control signal MCNT.

When the circuit shown in FIG. 1 is formed on a semiconductor substrate, when the first switch SW1 is formed of a MOS transistor, the source / drain are points A and C, and the gate is a mute control signal MCNT. Will be entered.

FIG. 2 is a timing chart showing the operation of the inverting amplifier with a mute function shown in FIG. In the figure, the mute control signal MCNT is at a low level (hereinafter,
L), the first switch SW1 is turned on, and high level (hereinafter, referred to as H), the first switch SW1 is turned on.
FF.

When the mute control signal MCNT is L, the points A and C are analog ground potentials due to the feedback action of the operational amplifier OP, and the input signal V _IN is defined by the ratio of the first resistor R1 and the second resistor R2. The output signal which is amplified and inverted by the amplification factor is obtained.

When the mute control signal MCNT is H, the point A follows the input signal V _IN , and the point C and the output signal V _IN.
OUT has an analog ground potential.

In the conventional example shown in FIGS. 1 and 2,
In order to completely mute the input signal V _IN and keep the output signal V _OUT in the no signal state (that is, the no signal state equal to the analog ground potential), the mute control signal MCNT is transited to H, but the actual MOS In the LSI circuit, the first switch SW that is propagated to the operation amplifier OP or turned off due to a minute current leak between the source / drain of the MOS switch.
1 propagates to the gate biased with finite impedance through the parasitic capacitance between the source and the gate of 1 and further propagates to the inverting input terminal of the operational amplifier OP through the parasitic capacitance between the gate and the drain. Appeared as the output signal V _OUT of the operational amplifier OP.

3 and 4 show another conventional example for achieving a better mute state as compared with the above-mentioned conventional example.

In the conventional example shown in FIG. 3, the first and second
2 switches SW1 and SW2 are connected in series, and a third switch SW3 is further provided. Then, in the signal output state, both the first switch SW1 and the second switch are ON, and the third switch SW3 is OFF, so that the input signal V
_It outputs an inverted amplified signal of _IN . On the other hand, in the mute state, both the first switch SW1 and the second switch are turned off, and the third switch SW3 is turned on to keep the point B between the first and second switches at a constant potential. That is, in the mute state, the leakage of the input signal V _{IN to} the output side due to the signal leakage through the source / drain of the MOS switch and the signal propagation through the parasitic capacitance of the source / gate / drain is prevented. .

In the conventional example shown in FIG. 4, the first resistor R1 is turned on by turning on the third switch SW3 during mute.
The terminal voltage (potential at the point A) is kept constant and the voltage amplitude at the point A is suppressed to prevent the input signal flowing into the operational amplifier side via the first switch SW1 from leaking.

However, in the conventional example shown in FIG. 3, it is necessary to connect a voltage follower VF having a low output impedance to the node (point B) between the first switch SW1 and the second switch SW2. . Further, in the conventional example shown in FIG. 4, a similar active element such as a voltage follower is required to keep the potential at the point A constant.

[0012]

As described above, the conventional example shown in FIG. 1 has a problem that the mute cannot be performed sufficiently.

Further, in the conventional example shown in FIGS. 3 and 4, an active element such as an operational amplifier or a voltage follower is separately required, and when formed by a semiconductor circuit, not only does the circuit area increase. However, there is a problem that power consumption increases. In particular, in portable audio equipment, the increase in power consumption is a fatal problem.

Therefore, in view of the above points, an object of the present invention is to
An object of the present invention is to provide an inverting amplifier with a mute function and a semiconductor device that exhibit good mute characteristics despite a simple circuit configuration and prevent an increase in power consumption.

[0015]

In order to achieve the above object, the present invention according to claim 1 is an inverting amplifier with a mute function for muting an analog output signal in response to a mute control signal. A serial input circuit having a first resistor for introducing an input signal, a first switch connected to the latter stage of the first resistor, and a second switch connected to the latter stage of the first switch, and the serial input circuit And an operational amplifier having an inverting input terminal connected to the second switch and the first MOS switch when an instruction to change the state from the signal output state to the mute state is generated by the mute control signal. The switches are turned off in order, and when the state change instruction from the mute state to the signal output state is generated by the mute control signal, the first switch, the 2 to turn on the switches in the order of the switch.

According to a second aspect of the present invention, in the inverting amplifier with a mute function according to the first aspect, the first switch and the second switch are MOS switches.

According to a third aspect of the present invention, the inverting amplifier with a mute function according to the first or second aspect is formed on a semiconductor substrate.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 5 shows a circuit configuration of an inverting amplifier with a mute function to which the present invention is applied. The present embodiment includes a timing control circuit 10, and a first switch control signal SCNT1 for controlling the opening / closing timing of the first switch SW1 and a first switch control signal for controlling the opening / closing timing of the second switch SW2. The signal SCNT2 is output.

FIG. 6 is a timing chart showing the operation of the circuit shown in FIG. As is apparent from FIGS. 5 and 6, when the mute control signal MCNT is L and in the signal output state, the first switch SW1 and the second switch are ON, and the input signal V _IN is inverted and amplified and output. To be done.

On the other hand, when the mute control signal MCNT is H and in the mute state, the first switch SW1 and the second switch are OFF. As described above with reference to FIG. 1 as a problem of the conventional technique, even when the MOS switch is in the OFF state, signal propagation is caused via a minute current leak generated between the source / drain and a parasitic capacitance between the source / gate / drain. Therefore, in the present embodiment, O
Two switches in the FF state are connected in series. As a result, when viewed from the input signal side, the signal leakage is limited to some extent by the first switch SW1 and further limited by the second switch SW2. , Shows much better barrier properties.

Assuming now that one switch in the OFF state can attenuate a signal to 1/1000 (-60 dB), two of them will be in series, and the attenuation characteristic will be linear.
An attenuation characteristic of 1 /, 000,000 (-120 dB) is obtained.
For example, a digital audio device often expresses a signal as a 16-bit signal, but in this case, 1 LSB is −
It is equivalent to 98 dB, and the above-120 dB is 1 LS.
Since it corresponds to a signal of B or less, a sufficient mute state can be obtained. In other words, even if the attenuation characteristic in the OFF state changes remarkably depending on the structure of the switch, the necessary and sufficient mute state can be easily realized by connecting two switches in the OFF state in series as in the present embodiment. become.

In addition, in this embodiment, the order of turning on and off these two switches SW1 and SW2 is also an important factor. The switch control will be described below.

As shown in FIG. 6, the mute control signal MC
When NT transitions from L to H and changes from the signal output state to the mute state, two switch control signals SCNT1, SCNT1 generated by the timing control circuit 10 are generated.
According to SCNT2, first the second switch SW2 is turned off, and then the first switch SW1 is turned off.

When the second switch SW2 is turned off, feedthrough noise is generated and pop noise is generated on the output side. When the first switch SW1 is turned off, the second switch SW2 is turned off.
Since the switch SW2 has already been turned off, feedthrough noise due to the turning off of the first switch SW1 does not appear on the output side. In this way, the two switches SW
Compared to the case where 1 and SW2 are turned off at the same time, in the present embodiment, pop noise when only one switch is turned off appears on the output side, so that the pop noise can be reduced.

First switch SW1 and second switch SW2
When both are OFF, point B is in a floating state. At this time, focusing on the propagation of the signal leaking from the A point to the C point, first, the propagation from the A point to the B point is attenuated,
Furthermore, since it is sufficiently attenuated by the propagation from the point B to the point C, it is much smaller than that of the conventional technique shown in FIG. 1, and a sufficiently good mute can be realized.

When both the first switch SW1 and the second switch SW2 are OFF, the point B is in a floating state, so that a minute leak current from the source / drain made of the diffusion layer of the MOS transistor to the semiconductor substrate may occur. As a result, the electric charge held in the parasitic capacitance at the point B flows out, and the potential thereof drifts. However, this potential drift itself does not affect the output at all, so no problem occurs.

When the mute control signal MCNT changes from H to L and changes from the mute state to the signal output state, the first switch SW1 and the second switch SW2 are simultaneously turned on.
When set to N or the second switch SW2 is turned on first,
Since the electric charge at the point B that has drifted into the point C, the output potential changes greatly and pop noise is generated. Therefore, in the present embodiment, considering this point,
First, by turning on the first switch SW1 first, B
The potential at the point is returned to the analog ground potential via the input resistor R1, and then the second switch SW2 is turned on. That is, when the second switch SW2 is turned on, B
The electric potential at the point is the same as the electric potential at the point C, so that charge inrush does not occur and pop noise does not occur.

Further, when the second switch SW2 is turned on, feedthrough noise is generated and pop noise is generated on the output side, but the feedthrough noise when the first switch SW1 is turned on is that the second switch SW2 is still off. It does not appear on the output side because it is performed in the state where As described above, compared with the case where the two switches SW1 and SW2 are turned on at the same time, only pop noise when only one switch is turned on appears on the output side in the present embodiment, so that the pop noise can be reduced. it can.

The delay function of the timing control circuit 10 shown in FIG. 5 can be realized by using a device delay as shown in FIG. Further, as shown in FIG. 8, it can be realized by a timer circuit using a clock signal supplied separately.

The first obtained by the circuits of FIGS. 7 and 8.
The switch control signal SCNT1 and the second switch control signal SCNT2 can be directly input to the gate terminal when the first switch SW1 and the second switch SW2 are composed of NMOS transistors. Further, in any case, since it is not necessary to add an operational amplifier or the like, the current consumption does not increase significantly.

[0032]

As described above, according to the present invention, a good mute characteristic is exhibited despite a simple circuit configuration,
In addition, it is possible to realize an inverting amplifier with a mute function and a semiconductor device that prevent an increase in power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a conventionally known inverting amplifier with a mute function.

FIG. 2 is a timing chart showing the operation of FIG.

FIG. 3 is a circuit diagram showing another conventionally known inverting amplifier with a mute function.

FIG. 4 is a circuit diagram showing another conventionally known inverting amplifier with a mute function.

FIG. 5 is a circuit diagram showing an inverting amplifier with a mute function to which the present invention is applied.

FIG. 6 is a timing chart showing the operation of FIG.

7 is a circuit diagram showing a specific configuration example of the timing control circuit shown in FIG.

FIG. 8 is a circuit diagram showing another timing control circuit shown in FIG.

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Claims (3)

[Claims] 1. An inverting amplifier with a mute function for muting an analog output signal in response to a mute control signal, comprising: a first resistor for introducing an analog input signal; and a first resistor connected after the first resistor. A serial input circuit having a switch and a second switch connected to the latter stage of the first switch; and an operational amplifier having an inverting input terminal to which the serial input circuit is connected. When an instruction to change the state from the signal output state to the mute state is generated, each switch of the second switch and the first MOS switch is turned off in order, and the state change from the mute state to the signal output state is performed by the mute control signal. When an instruction is issued, each switch is turned on in the order of the first switch and the second switch, and the mute device is characterized in that Per inverting amplifier. 2. The inverting amplifier with a mute function according to claim 1, wherein the first switch and the second switch are MOS switches. 3. A semiconductor device, wherein the inverting amplifier with a mute function according to claim 1 or 2 is formed on a semiconductor substrate.