JP2003288048A - Display device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that in a display device, the after image of the luminance data of a previous frame is generated when luminance data are rewritten. <P>SOLUTION: A display device 10 has a plurality of pixel circuits constituting a display screen, a first preceding data line DL1a and a first following data line DL1b for carrying luminance data to be written in the pixel circuits and a display control circuit 100. The control circuit 100 writes luminance data for a next frame in the pixel circuits connected to the first preceding data line DL1a whilst it is writing luminance data for a current frame in the pixel circuits connected to the first following data line DL1b. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a driving method thereof. The present invention particularly relates to an active matrix type display device and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, organic ELs functioning as light emitting devices
(OLED: Organic Light Emitt
ing diode) display device is a CRT
It is drawing attention as a display device that replaces LCDs and LCDs. In particular, active research and development of an active matrix type display device in which a plurality of pixels are arranged in a matrix in the vertical and horizontal directions has been actively pursued.

The practical design of an active matrix type display device using such an organic EL element is in its infancy, and various pixel circuits have been proposed. FIG. 9 shows an example of such a circuit.

This circuit is a thin film transistor (Thin).
Film Transistor: hereinafter simply referred to as transistors), a transistor Tr10 and a transistor Tr20, a capacitor C, and an organic EL element OLE.
Including D10. The transistor Tr10 is for switching, and the transistor Tr20 is the organic EL element OLED10.
Is for driving. In the transistor Tr10, the gate electrode is connected to the selection line 110, the drain electrode (or source electrode) is connected to the data line 112,
The source electrode (or drain electrode) is the transistor Tr
It is connected to the gate electrode of 20 and one electrode of the capacitor C. The other electrode of the capacitor C is connected to the source electrode of the transistor Tr20. The data line 112 is connected to a constant voltage source (not shown) and transmits brightness data that determines the current flowing through the organic EL element OLED10.

In the transistor Tr20, the source electrode is connected to the anode of the organic EL element OLED10,
The drain electrode is connected to the power supply line 114. Power line 11
Reference numeral 4 is connected to a power supply Vdd provided outside the pixel region, and a voltage for actually causing the organic EL element OLED10 to emit light is applied.

The organic EL element OLED10 includes a light emitting element layer sandwiched between an anode and a cathode. Organic EL
The anode of the element OLED10 is connected to the source electrode of the transistor Tr2, and the cathode is grounded.

The operation of the display device having the above configuration will be described. First, the selection line 110 is selected to select the transistor Tr1.
After turning 0 on, a data potential is applied to the data line 112. At this time, the potential of the electrode of the capacitor C rises. At the same time, the potential of the gate electrode of the transistor Tr20 also changes to the capacitance C
Changes to the same as the potential of the electrode.

When the potential of the gate electrode of the transistor Tr20 exceeds a predetermined value, a current corresponding to the voltage flows from the power source line 114 to the organic EL element OLED10, and the organic EL element.
The element OLED10 emits light. Even if the selection line 110 is not selected, the gate potential of the transistor Tr20 is maintained, so that the organic EL element OLED10 has the transistor T20.
It continues to emit light with a brightness according to the data potential applied to the gate electrode of r20.

[0009]

In such an active matrix type display device, video data is displayed on the display screen by sequentially selecting the selection lines and writing the brightness data for each pixel in each row. It When the writing of the luminance data of a certain frame to all the pixels forming the display screen is performed, the writing of the luminance data of a new frame is started by the same procedure.

However, when the value of the brightness data written in the previous frame is large, even if an attempt is made to set brightness data with a small value in the next frame, the charges corresponding to the previous brightness data will not escape from the optical element. In some cases, the afterimage phenomenon may be observed because accurate luminance data cannot be set. In particular, when displaying a moving image that changes drastically, the visibility may decrease. Due to such an afterimage phenomenon, variations in luminance may occur.

In the case of fast-forwarding a moving image, a method of writing the luminance data by skipping a part of the frame used during normal playback is used. For example, usually 6 per second
When displaying 0-frame image and displaying video data, 30-frame image is displayed per second by skipping frames when reproducing at double speed. However, with this method, it is difficult to perform fast-forward playback smoothly because some frames are not displayed at all. Further, when using a display device using an organic EL element in a small device such as a mobile phone, it is an important issue to suppress power consumption.

The present invention has been made in view of such a situation, and an object thereof is to reduce an afterimage phenomenon.
Another object of the present invention is to reduce variations in brightness. Another object of the present invention is to facilitate smooth fast-forward playback of moving images. Still another object of the present invention is to reduce power consumption.

[0013]

One aspect of the present invention relates to a driving method of a display device including a plurality of pixel circuits forming a display screen. According to this method, the writing of the luminance data for the next frame is started in the pixel circuit before the writing of the luminance data for the current frame is finished in all of the plurality of pixel circuits.

The "pixel circuit" includes an optical element, a drive circuit for driving the optical element, and a switch circuit for switching on / off of writing of brightness data to the optical element. The "luminance data" is data relating to the luminance information set in the drive circuit, and is distinguished from the light intensity emitted by the optical element. An organic EL element is mainly assumed as the optical element. A metal oxide film (MOS: Me) is used for the drive circuit and the switch circuit.
Tal Oxide Semiconductor) transistors and thin film transistors are mainly assumed.

By simultaneously writing the luminance data for the current frame and the luminance data for the next frame, it is possible to lengthen the writing time of the luminance data for one pixel, and to prevent the afterimage phenomenon of the luminance data of the previous frame. It can be reduced.

Another aspect of the present invention also relates to a driving method of a display device including a plurality of pixel circuits forming a display screen. In this method, when n is a natural number of 2 or more, when the writing of the luminance data for the current frame into the plurality of pixel circuits reaches 1 / n of the display screen from the edge of the display screen, The writing of the luminance data for the next frame is started from the edge of the display screen, and thereafter, if the writing of the luminance data for a certain frame reaches 1 / n of the display screen, the writing of the luminance data for the next frame is displayed. Start at the edge of the screen.

By simultaneously writing the luminance data for the current frame and the luminance data for the next frame, the writing time of the luminance data for one pixel can be lengthened, and the afterimage phenomenon of the luminance data of the previous frame can be prevented. It can be reduced.

According to this method, the writing of the luminance data to each of the plurality of pixel circuits may be carried out for a longer time than when n is 1. According to this method, the writing time of the brightness data for one pixel can be lengthened,
Since the operation clock frequency for displaying the brightness data can be reduced, power consumption can be reduced. In this method, for example, the writing of the brightness data to each of the plurality of pixel circuits may be performed in a time that is n times as long as when n is 1.

According to this method, the writing of the brightness data to the plurality of pixel circuits may be carried out for the same time as when n is 1. According to this method, the time for displaying the luminance data of a certain frame can be shortened, so that the moving image can be played back fast. Moreover, since the brightness data of all the frames are displayed, it is possible to facilitate smooth fast-forward reproduction of a moving image.

In this method, the writing of the luminance data to each of the plurality of pixel circuits may be carried out for the same time as when n is 1. According to this method, the time for displaying the luminance data of a certain frame can be increased by 1 / n times, so that the moving image can be reproduced at n times speed.
Also, since the brightness data of all frames are displayed,
It can facilitate smooth fast-forward playback of videos.

Another aspect of the present invention relates to a display device.
This device relates to a plurality of pixel circuits that form a display screen, first and second data lines that propagate luminance data to be written in the pixel circuits, and pixel circuits connected to the first data lines. A display control circuit for writing the luminance data for the next frame to the pixel circuit connected to the second data line while writing the luminance data for the current frame.

Another aspect of the present invention also relates to a display device. This device is configured such that a plurality of pixel circuits arranged in a matrix and the pixel circuits included in one of the rows while writing the luminance data for the current frame into the pixel circuits included in another row. And a display control circuit for writing the luminance data for the next frame.

Another aspect of the present invention also relates to a display device. This device includes a plurality of pixel circuits that form one frame, a first data line that propagates luminance data to be written to a part of the pixel circuits, and a pixel of another part of the plurality of pixel circuits. The second data line that propagates the luminance data to be written to the circuit and the first data line while transmitting the luminance data for the current frame propagates the luminance data for the next frame to the second data line. A display in which the first data line and the second data line are selected at the same time and the luminance data for the current frame is written to one pixel circuit while the luminance data for the next frame is written to the other pixel circuit. And a control circuit.

The display control circuit may write the brightness data for a plurality of frames in each pixel circuit during the time required to sequentially write the brightness data in all of the plurality of pixel circuits. As a result, the writing time of the brightness data for one pixel can be lengthened and the operation clock frequency for displaying the brightness data can be lowered, so that the power consumption can be reduced.

Any combination or combination of the above components is also effective as an aspect of the present invention.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION In the embodiments, an active matrix type organic EL display is assumed as a display device.

(First Embodiment) FIG. 1 shows a circuit configuration of a part of pixels of a display device according to the present embodiment. The display device 10 includes pixels arranged in a matrix with 256 rows in the vertical direction and n columns in the horizontal direction. The display screen of the display device 10 is composed of a total of 256 × n pixels. In the figure,
Pixel circuits P ₁ , P ₂ , P ₃ , P ₁₂₉ , P of the first column
Only the configurations of ₁₃₀ , P ₁₃₁ and P ₂₅₆ are shown,
Pixels in the other columns are configured similarly to the pixels in the first column. Each pixel has a first transistor Tr1, a second transistor Tr2, and an organic EL element OLED1. The first transistor Tr1 is for switching and the second
The transistor Tr2 is for driving the organic EL element OLED1. In the present embodiment, the first transistor Tr1 and the second transistor Tr2 are n-channel type.

Here, the pixels from the first row to the 128th row, which constitute the upper half of the display screen, are connected to the first preceding data line DL1a. In addition, the pixels from the 129th row to the 256th row, which form the lower half of the display screen,
It is connected to the first succeeding data line DL1b.

Since each pixel has the same configuration, only the first pixel P ₁ will be described here. In the first transistor Tr1, the gate electrode is connected to the first selection line SL1, the drain electrode (or source electrode) is connected to the first preceding data line DL1a, and the source electrode (or drain electrode) is connected to the second It is connected to the gate electrode of the transistor Tr2. In the second transistor Tr2,
The drain electrode is connected to the power supply Vdd, and the source electrode is connected to the anode of the organic EL element OLED1. Organic E
The L element OLED1 includes a light emitting element layer sandwiched between an anode and a cathode. The cathode of the organic EL element OLED1 is grounded. The power supply Vdd supplies power for causing the organic EL element OLED1 of each pixel to emit light.

[0030] In the first pixel _{P 1} thus configured, an operation to emit light organic EL element OLED1. When the first selection line SL1 is selected, the first transistor Tr1 of the first pixel P ₁ is turned on, and the luminance data from the first preceding data line DL1a is held in the gate electrode of the second transistor Tr2. To be done. When the potential of the gate electrode of the second transistor Tr2 becomes equal to or higher than a predetermined value, a current corresponding to the voltage flows from the power supply Vdd to the organic EL element OLED1 and the organic EL element OLED1 emits light.

The display control circuit 100 includes a selection control circuit 10
2 and the data control circuit 104, and controls writing of luminance data to each pixel circuit. Selection control circuit 102
Controls the output of the selection signal to each pixel circuit. The data control circuit 104 controls the output of brightness data to each pixel circuit. The data control circuit 104 includes a first basic data line BDL1 and a second basic data line BDL.
2 is input, and while the data control circuit 104 and the selection control circuit 102 are writing the brightness data to the first pixel P ₁ via the first preceding data line DL1a, for example, The control is performed to write the luminance data to the pixel P _{129 of 129} via the first subsequent data line DL1b.

FIG. 2 is a diagram showing an example of the internal configuration of the selection control circuit 102. In the present embodiment, the selection control circuit 102 includes first to 256th selection shift registers SSR1 to SSR256 corresponding to the number of pixels, a first AND circuit AND1, a second AND circuit AND2, and a logical sum. It has a circuit OR and an inverting circuit NOT. First to 256th shift registers for selection SSR1 to SSR25
6 includes first to 256th selection lines SL1 to S, respectively.
L256 is connected. Shift register SSR for each selection
The clock signal CLK is input to 1 to SSR 256.

The set signal ST is input to the first AND circuit AND1 and the second AND circuit AND2. Since the set signal ST is input to the first AND circuit AND1 through the inverting circuit NOT, the first AND circuit AND1 is selected when the set signal ST is low, and the second AND circuit AND1 is selected when the set signal ST is high. The AND circuit AND2 is selected. Also,
The second AND circuit AND2 stores the clock data CD1
Is entered. The outputs from the first AND circuit AND1 and the second AND circuit AND2 are input to the OR circuit OR, and the second clock data CD2 is output.
The second clock data CD2 is input to the first selection shift register SSR1.

Initially, both the high set signal ST and the high first clock data CD1 are input to the second AND circuit AND2, and the high second clock data CD2 is output via the OR circuit OR. To be done. The first selection shift register SSR1 outputs high to the first selection line SL1 and the second selection shift register SSR2 according to the timing of inputting the clock signal CLK.
Similarly, the second to 128th selection shift registers S
Each of SR2 to SSR128 outputs high stepwise every time the clock signal CLK is input.

The 128th shift register for selection SSR1
28th to 129th shift registers for selection SSR129
When the high level is output to the second AND circuit A
The high set signal ST and the high first clock data CD1 are input to the ND2 again. The first selection shift register SSR1 and the 129th selection shift register SSR129 respectively have a first selection line SL1 and a twelfth selection line SLSR129 depending on the timing of input of a clock signal.
9 is output to the selection line SL129. At this time, the output from the first selection shift register SSR1 is input to the second selection shift register SSR2, and the output from the 129th selection shift register SSR129 is input to the 130th selection shift register SSR130. Similarly, the second to the 128th selection shift registers SSR2 to
The SSR128 and the 130th to 256th selection shift registers SSR130 to SSR256 output a high level stepwise each time the clock signal CLK is input.
The output of the 256th shift register for selection SSR256 is input to the first AND circuit AND1.

When the set signal ST is low, the first AND circuit AND1 is switched to output the second clock data CD2. The second AND circuit AND1
When high level is input from the selection shift register SSR256 of 56, the high second clock data CD2 is input to the first selection shift register SSR1 via the OR circuit OR.
Is output. At this time, since a high signal is input from the 128th selection shift register SSR128 to the 129th selection shift register SSR129, the first selection shift register SSR1 and the 129th selection shift register SSR129 are again input. Are selected at the same time. While the set signal ST is low, the output of the second clock data CD2 via the first AND circuit AND1 is periodically repeated.

FIG. 3 is a diagram showing an example of the internal configuration of the data control circuit 104. In the present embodiment, the data control circuit 104 uses the first to nth corresponding to the number of columns of pixels.
Data shift registers DSR1 to DSRn. The first to nth preceding data lines DL1a to DLna are connected to the first basic data line BDL1, and the first to nth succeeding data lines DL1b to DLnb are connected to the second basic data line BDL2. Connected. A third transistor Tr3 is provided between each data shift register and each preceding data line. In the third transistor Tr3, the output from the data shift register is applied to the gate electrode. A fourth transistor Tr4 is provided between each data shift register and each subsequent data line. In the fourth transistor Tr4, the output from the data shift register is applied to the gate electrode.

First to n-th data shift registers D
Clock signals are sequentially input to SR1 to DSRn, and the first to nth data shift registers DSR1 to DSR
n sequentially outputs a high signal every time a clock signal is input. Here, the first data shift register D
The case where a high signal is output from SR1 will be described. When the high signal is output from the first data shift register DSR1, the third transistor Tr3 and the fourth transistor Tr4 are turned on. At this time, the first basic data line BDL1 and the second basic data line BDL
Since the brightness data flows through DL2, the brightness data from the first basic data line BDL1 is supplied to the first preceding data line DL1a, and the brightness data from the second basic data line BDL1 is supplied to the first subsequent data line DL1b. Luminance data is propagated.

Further, the first data shift register DS
Since the high signal output from R1 is input to the second data shift register DSR2, a high signal is output from the second data shift register DSR2 at the timing when the next clock signal is input. A high signal is output from the third data shift register DSR3 to the nth data shift register DSRn. Nth
The output from the data shift register DSRn is
Input to the data shift register DSR1 of
The high signal is output again from the first data shift register DSR1.

FIG. 4 is a time chart showing the relationship between the states of signals flowing through the select line and the data line. The state of the selection signal of each selection line is shown by high and low. Each basic data line BD
The luminance data flowing through L1 and the second basic data line BDL2 is shown as 2 for the current frame, 1 for the previous frame, and 3 for the next frame.

In the present embodiment, each selection line is selected every writing of luminance data for one half frame. In other words, each pixel constitutes a display screen.
The luminance data of the next frame is written every time the luminance data is written to half of the 56 × n pixels. Therefore, for example, when the display device 10 according to the present embodiment is operated at the same clock frequency as the normal processing for displaying pixels of 60 frames per second, pixels of 120 frames can be displayed per second, and all the pixels can be displayed. Double-speed reproduction can be performed while displaying a frame. On the other hand, even if the display device 10 according to the present embodiment is operated at a clock frequency that is ½ of that of the above-described normal processing, pixels of 60 frames can be displayed per second, so the clock frequency should be lowered. It is possible to reproduce video data as usual while reducing power consumption.

Of the luminance data for one frame, the luminance data for the first half of the one-half frame sequentially flows to the first basic data line BDL1, and the luminance data for one frame flows to the second basic data line BDL2. Among them, the luminance data of the latter half frame sequentially flows. It should be noted that the luminance data of the frame immediately preceding the luminance data flowing through the first basic data line BDL1 flows through the second basic data line BDL2. That is, when the first half of the luminance data of the current frame is flowing in the first basic data line BDL1, the latter half of the luminance data of the previous frame is flowing in the second basic data line BDL2.

Next, the operation of the display device 10 in the present embodiment will be described with reference to FIGS. First, the first
Selection line SL1 and the 129th selection line SL129 are simultaneously selected. At this time, the first preceding data line DL1
The luminance data of the current frame 2 to be written to the _first pixel P ₁ is propagated to a, and the luminance data of the previous frame 1 to be written to the 129th pixel P ₁₂₉ is propagated to the first subsequent data line DL1b. . Accordingly, the luminance data of the current frame 2 is supplied to the gate electrode of the second transistor Tr2 of the first pixel P ₁ and the second transistor Tr2 of the 129th pixel P ₁₂₉ is supplied.
The luminance data of the previous frame 1 is held in the gate electrode of the. Since the power from the power source Vdd is applied to the drain electrode of each second transistor Tr2, the organic EL element OLED1 of each pixel emits light according to the brightness data.

Similarly, the pixels of the first row and the twelfth row
Luminance data is sequentially written to the pixels in the ninth row.
Then, from the pixels on the second row and the 130th row to the 12th row.
Luminance data is sequentially written into the pixels in the eighth row and the pixels in the 256th row. With the above operation, the luminance data of the current frame 2 is displayed in the upper half of the display screen of the display device 10, and the luminance data of the previous frame 1 is displayed in the lower half.

Next, the first select line SL1 and the first select line SL1 are again provided.
The 29 selection lines SL129 are simultaneously selected, and the writing of the luminance data to the pixels on the first row and the 129th row is started. At this time, the luminance data of the next frame 3 to be written in the first pixel P ₁ is written in the first preceding data line DL1a, and the 129th pixel P ₁ is written in the first subsequent data line DL1b.
The luminance data of the current frame 2 to be written in ₂₉ is propagated.

According to the above configuration, the upper half and lower half pixels of the display screen can be rewritten at the same time.
In the selection control circuit 102 and the data control circuit 104, the frequency of the clock signal input to each shift register is set to be the same as a normal frequency, so that double-speed moving image reproduction can be realized. In this case, since it is possible to fast-forward the moving image while displaying the pixels of all the frames, smooth display can be facilitated.

On the other hand, by setting the frequency of the clock signal to half the normal frequency, the writing time to each pixel can be doubled while maintaining the reproduction speed as usual. As a result, the residual charge on the organic EL element OLED1 is eliminated, and the afterimage phenomenon can be reduced. Moreover, since the frequency of the clock signal is set to one half of the normal frequency, power consumption can be reduced.

(Second Embodiment) FIG. 5 shows a circuit configuration of some pixels of a display device according to the second embodiment. The present embodiment differs from the first embodiment in that the first subsequent data line DL1b connected to the lower half pixel of the display screen extends from the lower side to the upper side of the display screen. . With such an arrangement, it is possible to obtain the same advantages as those of the first embodiment without specially providing a wiring installation area in the pixel display area.

(Third Embodiment) FIG. 6 shows a circuit configuration of some pixels of a display device according to the third embodiment. The display device 20 according to the present embodiment is different from the first embodiment in that pixels in odd rows are connected to the preceding data lines DL1a to DLna and pixels in even rows are connected to the succeeding data lines DL1b to DLnb. different. Data control circuit 1
The configuration of 04 is the same as that of the first embodiment. Further, in the present embodiment, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

FIG. 7 is a diagram showing an example of the internal configuration of the selection control circuit 102. In the present embodiment, the 256th
2 in that the output from the selection shift register SSR256 is connected to the delay circuit 22 and the output from the delay circuit 22 is connected to the first AND circuit AND1.
Different from the embodiment. In the present embodiment, the twelfth
At the timing when a high level is output from the ninth selection shift register SSR129 to the thirtieth selection shift register SSR130, the second AND circuit AND2 again sets the high set signal ST and the high first clock data CD1.
Is entered. As a result, the first selection shift register SSR1 and the 130th selection shift register SS
R130 outputs high to the first selection line SL1 and the 130th selection line SL130, respectively, according to the timing of inputting the clock signal. Similarly, the second to 129th shift registers for selection SSR2 to SSR12
The ninth and 131st to 256th selection shift registers SSR131 to SSR256 output a high level stepwise each time the clock signal CLK is input. The delay circuit 22 includes a 129th selection shift register SSR1.
29th to 130th selection shift registers SSR130
The first AND circuit AN at the timing when the high level is output to
It outputs a high signal to D1.

FIG. 8 is a time chart showing the relationship between the states of signals flowing through the select line and the data line. Similar to the first embodiment, the state of the selection signal of each selection line is indicated by high and low, and the luminance data flowing in each basic data line BDL1 and second basic data line BDL2 is the same as that of the current frame. , 1 for the previous frame and 3 for the next frame.

In the present embodiment, each selection line is selected every writing of luminance data for one half frame + 1 row. The luminance data of the current frame 2 and the luminance data of the previous frame 1 are propagated to the first basic data line BDL1 and the second basic data line BDL2 for each row of pixels.

The operation of the display device 20 in the present embodiment will be described with reference to FIGS. 6 to 8. First, the first selection line SL1 and the 130th selection line SL130 are simultaneously selected, the luminance data of the current frame 2 is stored in the pixels on the first row, and the luminance data of the previous frame 1 is stored in the pixels on the 130th row. Is written. Since the power from the power source Vdd is applied to the drain electrode of the second transistor Tr2 of each pixel, the organic EL element OLED1 of each pixel emits light according to the brightness data.

Next, the pixels on the second and 131st rows are simultaneously selected. At this time, the first basic data line B
The brightness data of the previous frame 1 flows through DL1, the brightness data of the current frame 2 flows through the second basic data line BDL2, and the brightness data of the current frame 2 enters the pixels of the second row by the 131st The luminance data of the previous frame 1 is written in the pixels in the row. In this way, the luminance data is sequentially written to the pixels on the 127th row and the pixels on the 256th row. After that, the pixels on the 128th row are selected. At this time, since the luminance data of the current frame 2 is flowing in the second basic data line BDL2, the luminance data of the current frame 2 is written in the 128th row pixel. Subsequently, the pixel on the 129th row is selected. At this time, since the luminance data of the current frame 2 is flowing through the first basic data line BDL1, the current frame 2 is stored in the pixel on the 129th row.
Luminance data of is written. By the above operation, the current frame 2 is displayed in about half of the upper part of the display screen of the display device 10.
Luminance data of the previous frame 1 is displayed in about half of the lower portion. During this time, 256th
The high output from the selection shift register SSR256 is delayed by the delay circuit and is again returned to the first output at the next timing.
The pixels in the row and the 130th row are selected, and the luminance data of the next frame is written in each pixel.

Also in this embodiment, the selection control circuit 1
02 and the data control circuit 104, by setting the frequency of the clock signal input to each shift register to be the same as usual, it is possible to realize reproduction of a moving image at almost double speed. Further, the frequency of the clock signal may be a frequency at which the writing time to all pixels becomes the same as usual. Accordingly, the moving image can be fast-forwarded while displaying the pixels of all the frames, and thus smooth display can be facilitated.

On the other hand, by setting the frequency of the clock signal to half the normal frequency, the write time to each pixel can be almost doubled while maintaining the reproduction speed as usual. Further, the frequency of the clock signal may be a frequency at which the writing time to all pixels is twice as long as the normal time. As a result, the residual charge on the organic EL element OLED1 is eliminated, and the afterimage phenomenon can be reduced. Further, since the frequency of the clock signal is set to about one half of the normal frequency, it is possible to reduce power consumption.

The present invention has been described above based on the embodiments. This embodiment is merely an example, and it will be understood by those skilled in the art that various modifications can be made to the combination of each constituent element and each processing process, and such modifications are also within the scope of the present invention. . Hereinafter, such an example will be described.

In the embodiment, two types of data lines, that is, a preceding data line and a succeeding data line are provided for the pixels in each column, but three or more types of data lines may be provided. For example, by providing three types of data lines for pixels in each column and selecting three select lines at the same time,
Double speed fast forward playback is possible. Further, in this case, the power consumption can be further reduced by reducing the frequency of the clock signal to ⅓.

In the second embodiment, the first succeeding data line DL1b is connected to the selection control circuit 102, but another second selection control circuit is provided below the display screen. The second selection control circuit may control the signal to the first succeeding data line DL1b.

In the third embodiment, a high signal is output to the first selection shift register SSR1 at the timing when a high level is output from the 129th selection shift register SSR129 to the 130th selection shift register SSR130. Although it has been input, this timing can be adjusted as appropriate. This makes it possible to start writing the luminance data of the next frame from the first row when the writing of the luminance data for three-fifth frames of the display screen is completed. As described above, according to the configuration of the third embodiment, the writing of the luminance data of the next frame is started at the time when the writing to the arbitrary pixel within ½ or more and 1 of the display screen is completed. You can As a result, reproduction can be performed at an arbitrary speed between 1 × speed and 2 × speed, while keeping the clock frequency as usual.

Further, in the embodiment, the first transistor Tr1 and the second transistor Tr2 are n-channel type, but these transistors may be p-channel type, and n-channel type and p-channel type. It may be a combination with.

Further, the driving second transistor Tr
Two or more switching first transistors Tr1 for setting the luminance data to 2 may be arranged in series.
At that time, the characteristics of these transistors such as the current amplification factor may be different. For example, the second transistor Tr
If the current amplification factor of the transistor close to 2 is set low, the effect of reducing the leakage current is great.

Further, the characteristics of the first switching transistor Tr1 and the second driving transistor Tr2 may be changed. For example, when the current amplification factor of the second transistor Tr2 is reduced, the range of setting data corresponding to the same brightness range is widened, so that the brightness can be easily controlled.

[0064]

According to the present invention, the afterimage phenomenon in the display device can be reduced and the variation in the luminance can be reduced. According to the present invention, the power consumption of the display device can be suppressed. Further, according to the present invention, smooth fast-forward reproduction of a moving image can be facilitated.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of some pixels of a display device according to a first embodiment.

FIG. 2 is a diagram showing an example of an internal configuration of a selection control circuit.

FIG. 3 is a diagram showing an example of an internal configuration of a data control circuit.

FIG. 4 is a time chart showing a relationship between states of signals flowing through a selection line and a data line.

FIG. 5 is a diagram showing a circuit configuration of some pixels of a display device according to a second embodiment.

FIG. 6 is a diagram showing a circuit configuration of some pixels of a display device according to a third embodiment.

FIG. 7 is a diagram showing an example of an internal configuration of a selection control circuit.

FIG. 8 is a time chart showing a relationship between states of signals flowing through a selection line and a data line.

FIG. 9 is a diagram showing a circuit configuration of some pixels of a conventional display device.

[Explanation of symbols]

10 display device, 20 display device, 22 delay circuit, 100 display control circuit, 102 selection control circuit, 104 data control circuit, BDL1 first basic data line, BDL2 second basic data line, DL
1a 1st preceding data line, DL1b 1st succeeding data line, OLED1 organic EL element, SL1-SL
n 1st to nth selection line, Tr1 1st transistor, Tr2 2nd transistor, Tr3 3rd transistor, Tr4 4th transistor, Vd
d power supply

Claims (6)

[Claims] 1. A method of driving a display device including a plurality of pixel circuits which form a display screen, wherein the pixel circuits are connected to the pixel circuits before writing the luminance data for the current frame to all of the plurality of pixel circuits. A driving method characterized by starting writing of luminance data for a frame. 2. A method of driving a display device including a plurality of pixel circuits forming a display screen, wherein when n is a natural number of 2 or more, writing of luminance data for the current frame into the plurality of pixel circuits is performed. When reaching 1 / n of the display screen from the edge of the display screen, writing the brightness data for the next frame into the plurality of pixel circuits is started from the edge of the display screen, and thereafter, the brightness for a certain frame is sequentially read. A driving method characterized in that, when the writing of data reaches 1 / n of the display screen, the writing of the luminance data for the next frame is started from the edge of the display screen. 3. The driving method according to claim 2, wherein the writing of the luminance data to each of the plurality of pixel circuits is performed for a longer time than when n is 1. 4. The driving method according to claim 2, wherein the writing of the brightness data to the plurality of pixel circuits is performed for the same time as when the n is 1. 5. A plurality of pixel circuits forming a display screen, first and second data lines for transmitting luminance data to be written in the pixel circuits, and a pixel circuit connected to the first data lines. A display control circuit for writing the luminance data for the next frame to the pixel circuit connected to the second data line while writing the luminance data for the current frame. Characteristic display device. 6. A plurality of pixel circuits arranged in a matrix and a pixel included in another row while the luminance data for the current frame is written to the pixel circuits included in any row. A display device, comprising: a display control circuit for writing luminance data for a next frame into the circuit.