JP2003283324A - Superconducting junction line - Google Patents

Superconducting junction line

Info

Publication number
JP2003283324A
JP2003283324A JP2002081538A JP2002081538A JP2003283324A JP 2003283324 A JP2003283324 A JP 2003283324A JP 2002081538 A JP2002081538 A JP 2002081538A JP 2002081538 A JP2002081538 A JP 2002081538A JP 2003283324 A JP2003283324 A JP 2003283324A
Authority
JP
Japan
Prior art keywords
superconducting
superconducting junction
inductor
flux quantum
junction line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002081538A
Other languages
Japanese (ja)
Other versions
JP3737980B2 (en
Inventor
Yoshinobu Taruya
良信 樽谷
Hideyuki Sugiyama
英行 杉山
Keiichi Tanabe
圭一 田辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
International Superconductivity Technology Center
Hitachi Ltd
Original Assignee
Toshiba Corp
International Superconductivity Technology Center
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, International Superconductivity Technology Center, Hitachi Ltd filed Critical Toshiba Corp
Priority to JP2002081538A priority Critical patent/JP3737980B2/en
Publication of JP2003283324A publication Critical patent/JP2003283324A/en
Application granted granted Critical
Publication of JP3737980B2 publication Critical patent/JP3737980B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)
  • Logic Circuits (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a superconducting junction line which damps oscillations after passing over flux quantum pulses, even using an oxide type junction, etc., for generating abrupt flux quantum pulses, and allows a desired delay time to be set up, thus providing characteristics for a delay line. <P>SOLUTION: The superconducting junction line is basically composed of superconducting junctions and superconducting line inductors with resistors connected between desired points of the inductors and the ground. One or a plurality of resistors may be connected between the inductors and the ground. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は広く超電導エレクト
ロニクスの分野に係り、とくに高速の信号処理が可能な
磁束量子を信号の担体とし、高速信号観察用の計測回
路、高速のアナログ信号処理用のアナログ・デジタル信
号変換回路あるいは高速のデジタルデータ処理回路等に
用いられる超電導磁束量子回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to the field of superconducting electronics, and in particular, a magnetic flux quantum capable of high-speed signal processing is used as a signal carrier, a measuring circuit for high-speed signal observation, and an analog for high-speed analog signal processing. The present invention relates to a superconducting flux quantum circuit used in a digital signal conversion circuit or a high speed digital data processing circuit.

【0002】[0002]

【従来の技術】図2に、従来の磁束量子を転送する超電
導接合線路の一例を示す。図に於いて、1はバイアス電
流源、2は超電導接合、3はインダクタであり、インダ
クタ3を直列に接続し、インダクタ3の接続点でバイア
ス電流源1と超電導接合2とを接続する。バイアス電流
源1と超電導接合2の他端は接地する。ここで、バイア
ス電流源1、超電導接合2およびインダクタ3よりなる
回路が超電導接合線路の最小単位となり、必要に応じ
て、図2に示すように、バイアス電流源1および超電導
接合2の直列回路を重複させながら繰り返し接続した長
い超電導接合線路を構成することができる。単位の超電
導接合線路も、長い超電導接合線路もそれぞれの超電導
接合線路が果たす役割は同じであるから、これを区別す
る意味は無いが最小単位の超電導接合線路に特に言及し
たいときは、これを便宜上、単位超電導接合線路と呼
ぶ。、インダクタ3のインダクタンスLと超電導接合2
の臨界電流Icの積、すなわちLIc値は磁束量子Φ0
の大きさ2×10-15Wb(ウェーバ)より小さくする
と、インダクタ3とその両側にある2個の超電導接合2
とからなる超電導ループには一つの磁束量子信号しか存
在しない。逆に、LIc値を磁束量子Φ0の大きさより
十分大きくすれば、前記超電導ループには2つ以上の磁
束量子信号を存在させることができる。いずれの場合で
も、磁束量子信号は消滅せずに、転送される。通常の磁
束量子回路では、このような基本的な構造の超電導接合
線路が用いられる。
2. Description of the Related Art FIG. 2 shows an example of a conventional superconducting junction line that transfers magnetic flux quanta. In the figure, 1 is a bias current source, 2 is a superconducting junction, 3 is an inductor, the inductor 3 is connected in series, and the bias current source 1 and the superconducting junction 2 are connected at the connection point of the inductor 3. The other ends of the bias current source 1 and the superconducting junction 2 are grounded. Here, the circuit composed of the bias current source 1, the superconducting junction 2 and the inductor 3 is the minimum unit of the superconducting junction line, and if necessary, a series circuit of the bias current source 1 and the superconducting junction 2 can be formed as shown in FIG. It is possible to form a long superconducting junction line that is repeatedly connected while overlapping. The role of each superconducting junction line and that of a long superconducting junction line are the same, so there is no point in distinguishing this. , Called a unit superconducting junction line. , Inductance L of inductor 3 and superconducting junction 2
Is the product of the critical current Ic, that is, the LIc value is the magnetic flux quantum Φ 0
If the size is smaller than 2 × 10 −15 Wb (weber), the inductor 3 and the two superconducting junctions 2 on both sides of the inductor 3
There is only one magnetic flux quantum signal in the superconducting loop consisting of and. Conversely, if the LIc value is made sufficiently larger than the size of the magnetic flux quantum Φ 0 , two or more magnetic flux quantum signals can exist in the superconducting loop. In either case, the flux quantum signal is transferred without disappearing. In a normal magnetic flux quantum circuit, a superconducting junction line having such a basic structure is used.

【0003】超電導磁束量子回路の中で超電導接合線路
の果たす役割は主として以下の2点である。すなわち (1)フリップ・フロップや分岐回路等、磁束量子信号
を処理する回路の間に挿入して、磁束量子信号の波形を
整形する。 (2)磁束量子信号を伝送する。 ことであり、とくに長距離の伝送において磁束量子信号
の振幅を減衰させずに、一定の振幅に保つことにある。
The role of the superconducting junction line in the superconducting flux quantum circuit is mainly the following two points. That is, (1) the magnetic flux quantum signal is inserted between circuits such as a flip-flop and a branch circuit that process the magnetic flux quantum signal to shape the waveform of the magnetic flux quantum signal. (2) A magnetic flux quantum signal is transmitted. That is, in particular, in long-distance transmission, the amplitude of the magnetic flux quantum signal is not attenuated but kept constant.

【0004】[0004]

【発明が解決しようとする課題】従来の超電導磁束量子
回路に用いられる超電導接合線路では以下に述べる問題
を有し、超伝導磁束量子回路の高周波動作を損なうとと
もに、回路動作領域が狭められる。
The superconducting junction line used in the conventional superconducting flux quantum circuit has the following problems, impairing the high frequency operation of the superconducting flux quantum circuit and narrowing the circuit operating region.

【0005】従来の超電導接合線路を金属系超電導回路
で構成し、磁束量子信号を転送しようとした場合、とく
に高周波動作でも問題を生じない。一方、動作周波数を
より高く取ることができる酸化物系超電導回路で、磁束
量子信号を転送しようとする場合、磁束量子パルスが通
り過ぎた後、超電導接合が零電圧に瞬時に戻らないとい
う問題を生じる。すなわち、磁束量子パルス自体は幅が
数ピコ秒で波形が鈍ることなく転送できるが、このパル
スの後に零電圧を中心とした振動が20ps以上にわた
って継続すると言う問題がある。
When the conventional superconducting junction line is formed of a metal-based superconducting circuit and a magnetic flux quantum signal is to be transferred, no problem occurs even at high frequency operation. On the other hand, when trying to transfer a flux quantum signal in an oxide-based superconducting circuit that allows a higher operating frequency, there is a problem that the superconducting junction does not return to zero voltage instantly after the flux quantum pulse has passed. . That is, the magnetic flux quantum pulse itself can be transferred with a width of several picoseconds and without blunting of the waveform, but there is a problem that after this pulse, the oscillation around the zero voltage continues for 20 ps or more.

【0006】図3は酸化物系の超電導接合線路で磁束量
子信号が伝搬する様子を示した。図から分かるように、
磁束量子パルス自体は幅が数ピコ秒で波形が鈍ることな
く転送できるが、このパルスの後に零電圧を中心とした
振動が20ps以上にわたって継続している。図3の波
形は超電導接合の臨界電流Icと常伝導抵抗Rnの積、
IcRn積を2mVとした場合である。このような振動
が納まらない状態で次の磁束量子信号が届いた場合、磁
束量子パルスと振動が重なってしまう。この結果、超電
導接合線路に対するバイアス電流条件によっては、伝え
られるべき磁束量子信号が伝搬されずに、誤動作となっ
てしまう。磁束量子パルス後の振動があるレベル以下に
納まるのを待つとすれば、転送するべき磁束量子信号の
転送間隔を20ps以上にする必要がある。これではI
cRn積の大きい超電導接合を用いることによって期待
される高速性能を発揮できない。
FIG. 3 shows how a magnetic flux quantum signal propagates in an oxide-based superconducting junction line. As you can see from the figure,
The magnetic flux quantum pulse itself has a width of several picoseconds and can be transferred without blunting the waveform, but after this pulse, the oscillation around the zero voltage continues for 20 ps or more. The waveform of FIG. 3 is the product of the critical current Ic of the superconducting junction and the normal resistance Rn,
This is the case where the IcRn product is 2 mV. When the next magnetic flux quantum signal arrives in a state where such vibration is not contained, the magnetic flux quantum pulse and vibration overlap. As a result, depending on the bias current condition for the superconducting junction line, the magnetic flux quantum signal to be transmitted is not propagated, resulting in malfunction. To wait until the vibration after the magnetic flux quantum pulse falls below a certain level, it is necessary to set the transfer interval of the magnetic flux quantum signal to be transferred to 20 ps or more. This is I
The expected high speed performance cannot be achieved by using a superconducting junction having a large cRn product.

【0007】ところで、超電導磁束量子回路の動作周波
数は超電導接合の臨界電流Icと常伝導抵抗Rnの積、
IcRnに比例する。酸化物系の超電導接合ではIcR
n積を容易に大きくし得る。これに対して、金属系超電
導接合のIcRn積は、通常、0.2mVから0.4m
Vにすぎないから、酸化物系の超電導接合による超電導
接合線路に期待するところが大きいが、そのためには、
上述するような、磁束量子パルス後の振動を抑制するこ
とが不可欠となる。
By the way, the operating frequency of the superconducting flux quantum circuit is the product of the critical current Ic of the superconducting junction and the normal resistance Rn,
Proportional to IcRn. IcR for oxide-based superconducting junctions
The n product can be easily increased. On the other hand, the IcRn product of a metal-based superconducting junction is usually 0.2 mV to 0.4 m.
Since it is only V, there are great expectations for a superconducting junction line with an oxide-based superconducting junction.
It is essential to suppress the vibration after the magnetic flux quantum pulse as described above.

【0008】そこで、本発明の目的はIcRn積が1m
Vから2mVで急峻な磁束量子パルスを発生する酸化物
系の超電導接合でも、磁束量子パルスが通り過ぎた後の
振動が速やかに納まる特性を有する超電導接合線路を得
ることにある。
Therefore, the object of the present invention is to obtain an IcRn product of 1 m.
Even in an oxide-based superconducting junction that generates a steep magnetic flux quantum pulse from V to 2 mV, it is intended to obtain a superconducting junction line having a characteristic that vibrations after the magnetic flux quantum pulse passes quickly are contained.

【0009】[0009]

【課題を解決するための手段】本発明の対象とする超電
導接合線路は磁束量子を信号の担体とする超電導磁束量
子回路の中に搭載され、回路中の超電導電極あるいは超
電導線が超電導状態になる低温で使用される。また超電
導接合線路においてはバイアス電流等回路パラメータに
よってその伝送速度が決まるとともに、高速の磁束量子
パルスが伝搬される。そこで、上記課題に対して本発明
においては、酸化物系超電導体による超電導接合と超電
導線のインダクタによって構成される超電導接合線路の
インダクタの任意の場所と接地の間に抵抗を配した超電
導接合線路とした。
The superconducting junction line which is the object of the present invention is mounted in a superconducting flux quantum circuit in which a flux quantum is used as a signal carrier, and a superconducting pole or a superconducting wire in the circuit is brought into a superconducting state. Used at low temperature. Further, in the superconducting junction line, its transmission speed is determined by circuit parameters such as bias current, and high-speed magnetic flux quantum pulses are propagated. In view of the above problems, the present invention is directed to a superconducting junction line in which a resistor is arranged between an arbitrary location of an inductor of a superconducting junction line composed of an oxide of a superconducting superconductor and an inductor of the superconducting wire and ground. And

【0010】図1は本発明における超電導接合線路の基
本的な構成を示す図である。バイアス電流源1、超電導
接合2およびインダクタ3よりなる単位超電導接合線路
がカスケードに接続されて超電導接合線路を構成してい
る。図1と図2とを対比して容易に分かるように、本発
明では、インダクタ3の任意の場所と接地の間に抵抗4
が接続される。ここで、インダクタ3の分割数と接地の
間で接続する抵抗の数は1個でも良く、複数個でも良
い。
FIG. 1 is a diagram showing the basic structure of a superconducting junction line according to the present invention. A unit superconducting junction line composed of a bias current source 1, a superconducting junction 2 and an inductor 3 is connected in a cascade to form a superconducting junction line. As can be easily seen by comparing FIG. 1 and FIG. 2, in the present invention, a resistor 4 is provided between an arbitrary place of the inductor 3 and the ground.
Are connected. Here, the number of resistors connected between the number of divisions of the inductor 3 and the ground may be one or more.

【0011】[0011]

【発明の実施の形態】(実施例1)図1に示される超電
導接合線路を作製した。超電導接合線路は酸化物からな
り、その単位超電導接合線路の断面構造を図4に示し
た。図4は二つに分割されたインダクタ3,3と、その
両側にある超電導接合2,2の部分に着目した単位超電
導接合線路であり、バイアス電流源1については省略し
た。(A)は平面図であり、(B)は(A)のB−B位
置において矢印方向に見た断面図、(C)は(A)のC
−C位置において矢印方向に見た断面図である。図にお
いて、11は基板であり、ランタン・ストロンチウム・
アルミニウム・タンタル酸化物の単結晶とした。12は
磁気遮蔽膜であり、接地を兼用するものとし、イットリ
ウム・バリウム銅酸化物薄膜を用いた。13は絶縁膜で
あり、ランタン・ストロンチウム・アルミニウム・タン
タル酸化物薄膜を用いた。14および17は超電導接合
を構成するための下部電極および上部電極であり、それ
ぞれ、イットリウム・バリウム銅酸化物薄膜である。1
5は層間絶縁膜であり、ランタン・ストロンチウム・ア
ルミニウム・タンタル酸化物薄膜を用いた。18は超電
導接合の障壁層であり、ランプエッジ型で、スロープを
形成した下部電極膜14の端部表面に、イオンビームを
照射することによって形成した表面損傷層とした。16
はAu膜であり、抵抗4として機能させるためのもので
ある。19は超電導薄膜であり、超電導接合2間を結ぶ
インダクタ3として機能するものである。20はコンタ
クトであり、絶縁膜13に設けられた貫通孔を介して下
部電極14と磁気遮蔽膜12とを接続する。超電導接合
2として機能する部分では、上部電極17と超電導薄膜
19とは同じものである。ここで、抵抗として機能する
Au膜16の一端は超電導薄膜19に接続され、他端は
超電導接合の上部電極17、超電導接合の障壁層18お
よび下部電極14を介して接地12と接続した。この理
由は、プロセス全体を考えると、Au膜16の一端を直
接コンタクト20により接地するよりも、有利であるか
らである。超電導接合2の障壁層18の幅に比し、Au
膜16の一端が接続される超電導接合の障壁層18の幅
を十分に大きく取れば、Au膜16の一端が直接コンタ
クト20により接地されたと同等の接地状態が実現でき
ることは良く知られたことである。
BEST MODE FOR CARRYING OUT THE INVENTION (Example 1) A superconducting junction line shown in FIG. 1 was produced. The superconducting junction line is made of oxide, and the cross-sectional structure of the unit superconducting junction line is shown in FIG. FIG. 4 shows a unit superconducting junction line focusing on the inductors 3 and 3 divided into two and the superconducting junctions 2 and 2 on both sides thereof, and the bias current source 1 is omitted. (A) is a plan view, (B) is a cross-sectional view as seen in the direction of the arrow at the BB position in (A), and (C) is C in (A).
It is sectional drawing seen in the arrow direction in the -C position. In the figure, 11 is a substrate, and lanthanum strontium
A single crystal of aluminum / tantalum oxide was used. Reference numeral 12 denotes a magnetic shielding film which also serves as a ground, and an yttrium / barium copper oxide thin film was used. Reference numeral 13 is an insulating film, and a lanthanum-strontium-aluminum-tantalum oxide thin film was used. Reference numerals 14 and 17 denote a lower electrode and an upper electrode for forming a superconducting junction, which are yttrium / barium copper oxide thin films, respectively. 1
An interlayer insulating film 5 is a lanthanum-strontium-aluminum-tantalum oxide thin film. Reference numeral 18 denotes a barrier layer of a superconducting junction, which is a ramp edge type and is a surface damage layer formed by irradiating an ion beam on the end surface of the lower electrode film 14 having a slope. 16
Is an Au film for functioning as the resistor 4. Reference numeral 19 denotes a superconducting thin film, which functions as an inductor 3 connecting the superconducting junctions 2. Reference numeral 20 denotes a contact, which connects the lower electrode 14 and the magnetic shield film 12 through a through hole provided in the insulating film 13. In the portion functioning as the superconducting junction 2, the upper electrode 17 and the superconducting thin film 19 are the same. Here, one end of the Au film 16 functioning as a resistor was connected to the superconducting thin film 19, and the other end was connected to the ground 12 through the superconducting junction upper electrode 17, the superconducting junction barrier layer 18 and the lower electrode 14. This is because, considering the entire process, it is more advantageous than directly grounding one end of the Au film 16 by the contact 20. Compared with the width of the barrier layer 18 of the superconducting junction 2,
It is well known that if the width of the barrier layer 18 of the superconducting junction to which one end of the film 16 is connected is made sufficiently large, a grounded state equivalent to that where one end of the Au film 16 is directly grounded by the contact 20 can be realized. is there.

【0012】このような回路構成で、超電導接合の臨界
電流と常伝導状態の抵抗の積、IcRn値は温度4.2
Kで2mVであった。超電導接合2間を結ぶインダクタ
19の線幅は1ミクロンとした。磁気遮蔽膜12と超電
導接合2間の絶縁層13をランタン・ストロンチウム・
アルミニウム・タンタル酸化物薄膜とした結果、この例
の比誘電率はほぼ25であった。
With such a circuit structure, the product of the critical current of the superconducting junction and the resistance in the normal conduction state, IcRn value, is a temperature of 4.2.
It was 2 mV in K. The line width of the inductor 19 connecting the superconducting junctions 2 was set to 1 micron. The insulating layer 13 between the magnetic shield film 12 and the superconducting junction 2 is formed of lanthanum-strontium-
As a result of forming an aluminum / tantalum oxide thin film, the relative dielectric constant of this example was about 25.

【0013】図5は、図4に示した超電導接合線路を伝
搬する磁束量子パルスの動作特性を説明する図である。
この例は、インダクタ3の長さはトータル(超電導接合
2−2間)で60ミクロンとし、抵抗4の値は1オーム
とした超電導接合線路である。30,31は、それぞ
れ、図1の接続点A、Bで観測されたパルスを示す。す
なわち、接続点Aで観測されたパルスが約20ps後に
接続点Bで観測された状態を示す。一方、図6に、イン
ダクタ3の寸法および超電導接合2の特性を同じくし
て、抵抗4を接続しなかった場合の、図2の接続点A、
Bで観測されたパルス40,41を示した。ここで、パ
ルス40がパルス30に対応し、パルス41がパルス3
1に対応する。
FIG. 5 is a diagram for explaining the operating characteristics of the magnetic flux quantum pulse propagating through the superconducting junction line shown in FIG.
This example is a superconducting junction line in which the total length of the inductor 3 (between the superconducting junctions 2-2) is 60 microns and the value of the resistor 4 is 1 ohm. Reference numerals 30 and 31 respectively represent the pulses observed at the connection points A and B in FIG. That is, the pulse observed at the connection point A is observed at the connection point B after about 20 ps. On the other hand, in FIG. 6, the dimensions of the inductor 3 and the characteristics of the superconducting junction 2 are the same, and the connection point A of FIG.
The pulses 40 and 41 observed in B are shown. Here, the pulse 40 corresponds to the pulse 30, and the pulse 41 corresponds to the pulse 3.
Corresponds to 1.

【0014】両者を比較して明らかなように、インダク
タ3と接地の間で抵抗4をシャントすることによって、
磁束量子パルスに続く振動が大幅に低減されることがわ
かる。すなわち、図5では磁束量子パルスは、やや小さ
くなったものの、磁束量子パルスに続く振動が短い時間
で納まっている。インダクタ3と接地の間で抵抗4をシ
ャントすることによって振動が短い時間で納まる理由
は、超電導接合線路のインダクタ3と抵抗4の組み合わ
せによる積分作用により、急峻なパルスの減衰効果が得
られる。
As is apparent by comparing the two, by shunting the resistor 4 between the inductor 3 and ground,
It can be seen that the vibrations following the flux quantum pulse are significantly reduced. That is, in FIG. 5, the magnetic flux quantum pulse is slightly smaller, but the vibration following the magnetic flux quantum pulse is settled in a short time. The reason why the vibration is settled in a short time by shunting the resistor 4 between the inductor 3 and the ground is that a steep pulse damping effect is obtained by the integral action of the combination of the inductor 3 and the resistor 4 in the superconducting junction line.

【0015】また図5と図6とを比較して分かるよう
に、シャント抵抗4を接続することによって、隣接する
超電導接合間での、磁束量子パルスの伝搬時間が延びて
いる。
As can be seen by comparing FIGS. 5 and 6, by connecting the shunt resistor 4, the propagation time of the magnetic flux quantum pulse between the adjacent superconducting junctions is extended.

【0016】図7はインダクタ3の寸法および超電導接
合2の特性を同じくして、異なった値のシャント抵抗4
を接続した場合の、隣接する超電導接合2間での、磁束
量子パルスの伝搬時間を評価した図である。超電導接合
2にバイアス電流源から供給されるバイアス電流の臨界
電流に対する割合は95%および85%とした。これら
の結果からわかるように、シャント抵抗4の値を低くす
ることによって、磁束量子パルスの伝搬時間を大きくす
ることができる。またバイアス電流のの臨界電流に対す
る割合を小さくすることによっても、磁束量子パルスの
伝搬時間を伸ばすことができる。
FIG. 7 shows the dimensions of the inductor 3 and the characteristics of the superconducting junction 2 being the same, and the shunt resistor 4 having different values.
FIG. 4 is a diagram in which the propagation time of the magnetic flux quantum pulse between the adjacent superconducting junctions 2 in the case where is connected is evaluated. The ratio of the bias current supplied to the superconducting junction 2 from the bias current source to the critical current was set to 95% and 85%. As can be seen from these results, the propagation time of the magnetic flux quantum pulse can be increased by reducing the value of the shunt resistor 4. Further, the propagation time of the magnetic flux quantum pulse can be extended by reducing the ratio of the bias current to the critical current.

【0017】このことは、本発明の抵抗挿入が、超電導
接合線路を伝搬する磁束量子パルスの磁束量子パルスに
続く振動を大幅に低減することだけでなく、シャント抵
抗の値や、バイアス電流の割合を調節することによっ
て、隣接する超電導接合間での磁束量子パルスの伝搬時
間を所望の値に設定するためにも有用であることを意味
する。これらの結果から、シャント抵抗を接続した超電
導接合線路を遅延線として用い、かつ遅延時間を広い範
囲で任意の値に設定できる。たとえば、図7の例では、
シャント抵抗を0.5オームとして、バイアス率を85
%とすれば、超電導接合線路1段分、すなわち隣接する
超電導接合間での遅延時間を52ピコ秒にできる。
This means that not only the resistance insertion of the present invention significantly reduces the vibration of the magnetic flux quantum pulse propagating in the superconducting junction line, but also the value of the shunt resistance and the ratio of the bias current. It is also useful for adjusting the propagation time of the magnetic flux quantum pulse between adjacent superconducting junctions to a desired value. From these results, it is possible to use a superconducting junction line connected to a shunt resistor as a delay line and set the delay time to any value in a wide range. For example, in the example of FIG.
Shunt resistance is 0.5 ohm and bias rate is 85
%, The delay time for one superconducting junction line, that is, the delay time between adjacent superconducting junctions can be 52 picoseconds.

【0018】本発明にかかる超電導接合線路の遅延線と
しての効果についてみる。たとえば超電導線を遅延線と
して用いた場合、50ピコ秒の遅延時間を得るのに、
1.5ミリメートルの長さを必要とする。これに対し
て、図7の例に示したように、インダクタ3の長さはト
ータル(超電導接合2−2間)で60ミクロンとして、
シャント抵抗を0.5オームとして、バイアス率を85
%とすれば、本発明にかかる超電導接合線路では、その
長さを伸ばすことなく52ピコ秒の遅延を得ることがで
きるわけであるから、25分の1に縮小できると言うこ
とになる。
The effect of the superconducting junction line according to the present invention as a delay line will be examined. For example, when using a superconducting wire as a delay line, to obtain a delay time of 50 picoseconds,
Requires a length of 1.5 mm. On the other hand, as shown in the example of FIG. 7, the total length of the inductor 3 (between the superconducting junctions 2-2) is 60 microns,
Shunt resistance is 0.5 ohm and bias rate is 85
%, The superconducting junction line according to the present invention can obtain a delay of 52 picoseconds without extending its length, which means that it can be reduced to 1/25.

【0019】本実施例1では、図5と図6の磁束量子パ
ルス波形を比較すれば明らかなように、シャント抵抗4
を接続した超電導接合線路では磁束量子パルスの高さが
やや小さくなっているのは事実であるが、磁束量子パル
スの高さは2mVで、シャント抵抗4を接続しない従来
の超電導接合線路のパルス高さと比べて遜色は無い。本
実施例1は、磁束量子パルスに続く振動を短い時間で納
めるとともに、所定の範囲で必要とする遅延時間を設定
できる機能を持つ有用な回路を提案するものである。
In the first embodiment, as is clear by comparing the magnetic flux quantum pulse waveforms of FIGS. 5 and 6, the shunt resistance 4
It is true that the height of the magnetic flux quantum pulse is slightly smaller in the superconducting junction line connected to, but the height of the magnetic flux quantum pulse is 2 mV, and the pulse height of the conventional superconducting junction line without the shunt resistor 4 connected. Comparable to that. The first embodiment proposes a useful circuit that has a function of containing the vibration following the magnetic flux quantum pulse in a short time and setting a delay time required in a predetermined range.

【0020】(実施例2)実施例1で説明した超電導接
合線路の遅延効果に着目した磁束量子回路を構成した例
について説明する。実施例1で説明したように、本発明
によれば、線路の長さあたりの遅延時間を任意に調節で
きるから、複数個の信号の伝播する線路の遅延時間を調
整して、同時に並列に入力したり、個別の回路で処理さ
れた複数個の信号を同時に並列に出力するような場合
に、チップ上での面積を大きくすること無く容易に実現
できる。
(Embodiment 2) An example of constructing a magnetic flux quantum circuit focusing on the delay effect of the superconducting junction line described in Embodiment 1 will be described. As described in the first embodiment, according to the present invention, the delay time per length of the line can be arbitrarily adjusted, so that the delay time of the line through which a plurality of signals propagate is adjusted, and the signals are input in parallel at the same time. Alternatively, when a plurality of signals processed by individual circuits are simultaneously output in parallel, it can be easily realized without increasing the area on the chip.

【0021】図8は、フラッシュ型の4ビット・アナロ
グ・デジタル変換回路に遅延効果に着目した磁束量子回
路を応用した例を示す図である。スクイド型高速信号検
出器の出力信号波形を梯子型抵抗で4個に分割する。分
割された各ビットの信号をアナログ・デジタル変換器の
レベル判定回路にそれぞれ加える。レベル判定回路に
は、それぞれ、発振器で発生されたクロックパルスが分
岐回路で分周され、4つの超電導線路を介して、クロッ
ク1−クロック4に加えられて、クロックが加えられた
ときのレベル判定回路の状態を出力する。この出力は、
図示しないシフトレジスタを経て、デジタルデータとし
て外部に取り出される。したがって、アナログ・デジタ
ル変換回路が正しい出力を出すためには、クロック1−
クロック4が、実質的に同じタイミングで加えられるこ
とが重要である。
FIG. 8 is a diagram showing an example in which a magnetic flux quantum circuit focusing on the delay effect is applied to a flash type 4-bit analog-digital conversion circuit. The output signal waveform of the SQUID type high speed signal detector is divided into four by a ladder type resistor. Each divided bit signal is applied to the level determination circuit of the analog-digital converter. In the level determination circuit, the clock pulse generated by the oscillator is frequency-divided by the branch circuit and added to clock 1 to clock 4 via the four superconducting lines, and the level determination when the clock is applied is performed. Outputs the circuit status. This output is
It is taken out as digital data via a shift register (not shown). Therefore, in order for the analog-digital conversion circuit to output the correct output, the clock 1-
It is important that clock 4 be applied at substantially the same timing.

【0022】この場合、発振器とAD変換器の各レベル
判定回路の距離を構造上同じにすることは出来ない。す
なわち、図に示すように、各回路要素が基板上に配列さ
れているものとした場合、発振器からレベル判定回路へ
のクロックのパスの長さはクロック1のパスの長さが最
も短く、クロック4のパスの長さが最も長い。そのた
め、超電導接合線路の長さの差によって、クロック信号
はレベル判定回路には同時に到達しない。
In this case, it is impossible to make the distance between the oscillator and the level decision circuits of the AD converter the same structurally. That is, as shown in the figure, when each circuit element is arranged on the substrate, the length of the clock path from the oscillator to the level determination circuit is the shortest of the clock 1 paths. The length of pass 4 is the longest. Therefore, the clock signal does not reach the level determination circuit at the same time due to the difference in the length of the superconducting junction line.

【0023】図9は超電導接合線路の長さの差によって
クロックの到着に差が生じることを示す図である。この
例では、隣り合うレベル判定回路間で10ピコ秒の時間
差が生じている。最両端のレベル判定回路間では30ピ
コ秒である。この時間はクロック周波数を50ギガヘル
ツとした場合、1.5周期分のずれに相当する。
FIG. 9 is a diagram showing that there is a difference in clock arrival due to a difference in length of the superconducting junction line. In this example, there is a time difference of 10 picoseconds between adjacent level determination circuits. It takes 30 picoseconds between the level determination circuits at the extreme ends. This time corresponds to a shift of 1.5 cycles when the clock frequency is 50 GHz.

【0024】これを、ほぼ同時に到達するように、クロ
ックのパスの長さが短いパスについては、分岐回路から
AD変換器の各レベル判定回路へのクロックパルスを伝
播する超電導線路に適当な遅延機能を持たせることが必
要である。そこで、分岐回路とレベル判定回路間に、本
発明に係る超電導接合線路を用いた。すなわち図8に示
すように、分岐回路から各レベル判定回路に向かって、
最も距離の長いクロックのパスについては従来の超電導
接合線路とした。それよりも距離の短いクロックのパス
については本発明に係る超電導接合線路による遅延回路
を部分的に用いることとした。
In order to arrive at this almost at the same time, for a path having a short clock path, a delay function suitable for a superconducting line for propagating a clock pulse from a branch circuit to each level judgment circuit of an AD converter. It is necessary to have. Therefore, the superconducting junction line according to the present invention is used between the branch circuit and the level determination circuit. That is, as shown in FIG. 8, from the branch circuit to each level determination circuit,
The conventional superconducting junction line was used for the clock path with the longest distance. For a clock path having a shorter distance than that, the delay circuit using the superconducting junction line according to the present invention is partially used.

【0025】超電導磁束量子回路において、このような
超電導接合線路を磁束量子信号の遅延線として用いる。
超電導接合線路において、インダクタのインダクタンス
と抵抗の大きさの比、あるいは超電導接合に通電するバ
イアス電流と臨界電流の比によって遅延時間を設定する
ことができる。
In a superconducting flux quantum circuit, such a superconducting junction line is used as a delay line for a flux quantum signal.
In the superconducting junction line, the delay time can be set by the ratio of the magnitude of the inductance to the resistance of the inductor or the ratio of the bias current and the critical current flowing in the superconducting junction.

【0026】本発明に係る超電導接合線路は長さ60ミ
クロンのインダクタとIcRn値が2mVの超電導接
合、およびシャント抵抗から成り、2段で構成した。シ
ャント抵抗の大きさは距離の短い線路から順に、0.5
オーム、0.8オーム、および2オームとした。残りの
1ビット分はシャント抵抗を付加しない従来構造の超電
導接合線路とした。本発明に係る超電導接合線路の長
さ、および残りの1ビット分に付加した従来構造の超電
導接合線路の長さは等しくした。このような構成になる
超電導接合線路を用いて、クロック信号を4個のレベル
判定回路に供給した。
The superconducting junction line according to the present invention is composed of an inductor having a length of 60 μm, a superconducting junction having an IcRn value of 2 mV, and a shunt resistor, and has two stages. The shunt resistance is 0.5 in order from the line with the shortest distance.
It was ohm, 0.8 ohm, and 2 ohm. The remaining 1 bit is a superconducting junction line of the conventional structure without adding a shunt resistance. The length of the superconducting junction line according to the present invention and the length of the superconducting junction line of the conventional structure added to the remaining 1 bit are equal. The clock signal was supplied to the four level determination circuits by using the superconducting junction line having such a configuration.

【0027】図10は、上述の例で、各レベル判定回路
に入力されるクロック信号波形を示す図である。クロッ
ク1の遅延時間が他のクロック2,3と比較して不足の
感じがあるが、4個の磁束量子パルス波形の入力タイミ
ングのずれは5ピコ秒以下の範囲に納まっている。この
ことは本発明に係る超電導接合線路が遅延線として有効
に機能していることを示すものである。しかも、図4
(A)のレイアウトからも分かるように、抵抗4を挿入
するだけであるから、従来構造の超電導接合線路を延ば
すことによって遅延線とした場合より、最大で1mm近
い大幅な寸法の縮小効果を得ることができることがわか
る。
FIG. 10 is a diagram showing a clock signal waveform input to each level determination circuit in the above example. Although there is a feeling that the delay time of the clock 1 is insufficient as compared with the other clocks 2 and 3, the deviation of the input timing of the four magnetic flux quantum pulse waveforms is within the range of 5 picoseconds or less. This shows that the superconducting junction line according to the present invention effectively functions as a delay line. Moreover, FIG.
As can be seen from the layout in (A), since only the resistor 4 is inserted, a significant size reduction effect of up to 1 mm can be obtained compared with the case where a delay line is formed by extending a superconducting junction line having a conventional structure. You can see that you can.

【0028】本実施例2では、クロックのパスの長さが
短いパスにおいては、超電導接合の臨界電流とインダク
タのインダクタンスの積を、磁束量子の大きさより十分
大きくする。これによって、1個のインダクタと、これ
に接続される2個の超電導接合と接地によって囲まれ、
かつ囲まれた内部に抵抗を含む超電導ループに、複数個
の磁束量子信号を一時的に保持できるようにする。この
ことによって、安定な遅延動作を実現できる。
In the second embodiment, the product of the critical current of the superconducting junction and the inductance of the inductor is made sufficiently larger than the size of the magnetic flux quantum in the path having the short clock path. With this, it is surrounded by one inductor, two superconducting junctions connected to it, and ground,
And, it is possible to temporarily hold a plurality of magnetic flux quantum signals in a superconducting loop which includes a resistance inside thereof. As a result, stable delay operation can be realized.

【0029】このように本発明に係る超電導接合線路は
超高速で動作する磁束量子回路にあって、複数個の回路
に同じタイミングでクロック信号を供給し、高周波領域
で正常な回路動作に寄与するものである。
As described above, the superconducting junction line according to the present invention is a magnetic flux quantum circuit that operates at an ultrahigh speed, supplies clock signals to a plurality of circuits at the same timing, and contributes to normal circuit operation in a high frequency region. It is a thing.

【0030】(実施例3)実施例1で説明した超電導接
合線路の遅延効果に着目した磁束量子回路を構成した他
の例について説明する。この実施例3も、本質的には実
施例2と同じ機能を果たすものである。
(Embodiment 3) Another example of a magnetic flux quantum circuit, which focuses on the delay effect of the superconducting junction line described in Embodiment 1, will be described. The third embodiment also has essentially the same function as the second embodiment.

【0031】図11は高速の磁束量子信号をデマルチプ
レクサで4チャンネルに分配し、周波数を1/4に低減
して、超電導回路の外部に取り出す磁束量子回路に適用
した例を示す図である。デマルチプレクサから出た4本
の信号線は出力タイミングを合わせるために、セット・
リセット・フリップ・フロップ(RS−FFと略称)で
待機する。リセット信号が入力されると、保持されてい
た信号は一斉に出力される。同時に出力されるために
は、リセット信号が同時に4個のRS−FFに入力され
る必要がある。しかるに、実施例2で説明したと同様
に、1個の信号源から分岐回路で4個に分割したリセッ
ト信号線を分岐して配分する構造では、隣り合うRS−
FFに繋がる超電導接合線路の長さがそれぞれ異なって
しまう。この実施例3では約750ミクロン異なるもの
となっていた。
FIG. 11 is a diagram showing an example in which a high-speed magnetic flux quantum signal is distributed to four channels by a demultiplexer, the frequency is reduced to 1/4, and the magnetic flux quantum circuit is taken out of the superconducting circuit. Set the four signal lines from the demultiplexer to match the output timing.
Standby by a reset flip-flop (abbreviated as RS-FF). When the reset signal is input, the held signals are output all at once. In order to be output at the same time, the reset signals need to be input to the four RS-FFs at the same time. However, as described in the second embodiment, in the structure in which the reset signal line divided into four by the branch circuit from one signal source is branched and distributed, adjacent RS-
The lengths of the superconducting junction lines connected to the FF are different from each other. In Example 3, the difference was about 750 microns.

【0032】図12は超電導接合線路の長さの差によっ
てクロックの到着に差が生じることを示す図である。こ
の例では、隣り合うRS−FF間で25ピコ秒の時間差
が生じる。両端のレベル判定回路間では75ピコ秒であ
る。そこでリセット信号が分岐回路から各RS−FFま
でに至る到達時間の差を補償するために、実施例2と同
様に、本発明に係る超電導接合線路を用いた。
FIG. 12 is a diagram showing that there is a difference in clock arrival due to a difference in length of the superconducting junction line. In this example, a time difference of 25 picoseconds occurs between adjacent RS-FFs. It is 75 picoseconds between the level determination circuits at both ends. Therefore, in order to compensate for the difference in the arrival time of the reset signal from the branch circuit to each RS-FF, the superconducting junction line according to the present invention is used as in the second embodiment.

【0033】図13は本実施例3で採用した超電導接合
線路の等価回路を示す図である。4つのインダクタ3を
構成するトータルの長さが120ミクロンのインダクタ
とIcRn値が2mVの超電導接合2、および3個のシ
ャント抵抗4から成り、1段で構成した。シャント抵抗
の大きさは距離の短い線路から順に、0.6オーム、1
オーム、および3オームとした。このような構成になる
超電導接合線路を用いて、リセット信号1−リセット信
号4をそれぞれのRS−FFに供給した。
FIG. 13 is a diagram showing an equivalent circuit of the superconducting junction line used in the third embodiment. The four inductors 3 are composed of an inductor having a total length of 120 μm, a superconducting junction 2 having an IcRn value of 2 mV, and three shunt resistors 4 in one stage. The size of the shunt resistance is 0.6 ohm, 1 in order from the line with the shortest distance.
Ohms, and 3 ohms. The reset signal 1 to the reset signal 4 were supplied to each RS-FF using the superconducting junction line having such a configuration.

【0034】図14は各RS−FFに入力されるリセッ
ト信号の波形を示す図である。この例でも、4個の磁束
量子パルス波形の入力タイミングのずれは5ピコ秒以下
の範囲に納まっている。このことは本発明に係る超電導
接合線路が遅延線として有効に機能していることを示す
ものである。しかも、従来構造の超電導接合線路を延ば
すことによって遅延線とした場合より、最大で2mm以
上の大幅な寸法の縮小効果を示すことがわかる。
FIG. 14 is a diagram showing the waveform of the reset signal input to each RS-FF. Also in this example, the deviation of the input timing of the four magnetic flux quantum pulse waveforms is within the range of 5 picoseconds or less. This shows that the superconducting junction line according to the present invention effectively functions as a delay line. Moreover, it can be seen that, compared with the case where the delay line is formed by extending the superconducting junction line having the conventional structure, the maximum size reduction effect of 2 mm or more is significantly exhibited.

【0035】以上述べたごとく、本発明に係る超電導接
合線路は超高速で動作する磁束量子回路にあって、複数
個の回路に同じタイミングでセット信号を供給し、高周
波領域で多ビットの信号を互いに離れた配線位置から同
時に出力するのに寄与するものである。
As described above, the superconducting junction line according to the present invention is a magnetic flux quantum circuit that operates at an ultrahigh speed, and a set signal is supplied to a plurality of circuits at the same timing to generate a multi-bit signal in a high frequency region. This contributes to simultaneous output from wiring positions distant from each other.

【0036】(実施例4)図15に、本発明に係る超電
導接合線路を用いたリング発振回路のブロック構成の等
価回路を示す。回路の構成はトリガ発振部51、入力側
超電導接合線路52、超電導接合リング53、および出
力側超電導接合線路54からなる。このリング発振回路
の構成は、本願の発明者がかかわる特開2001−21
7687号の超電導発振器と本質的に同じであるが、先
の出願が金属系の超電導体で実現されるものを意識して
発明されたのに対して、本願の発明では酸化物系の超電
導体で実現されるリング発振回路を提案する点に於いて
異なる。図15と、特開2001−217687号の図
1とを対比して分かるように、実施例4の超電導接合線
路および超電導接合リングには、超電導接合線路のイン
ダクタ3間と接地の間にシャント抵抗4が設けられてい
ることを別にすれば、構造は同じである。本発明に係わ
る超電導接合線路を用いた。。
(Embodiment 4) FIG. 15 shows an equivalent circuit of a block configuration of a ring oscillation circuit using a superconducting junction line according to the present invention. The circuit configuration includes a trigger oscillator 51, an input-side superconducting junction line 52, a superconducting junction ring 53, and an output-side superconducting junction line 54. The configuration of this ring oscillator circuit is related to the inventor of the present application.
Although it is essentially the same as the superconducting oscillator of No. 7687, the previous application was invented with the intention of being realized by a metal-based superconductor, whereas the invention of the present application is an oxide-based superconductor. It is different in that it proposes a ring oscillation circuit realized by. As can be seen by comparing FIG. 15 and FIG. 1 of JP 2001-217687 A, the superconducting junction line and the superconducting junction ring of Example 4 have a shunt resistance between the inductor 3 and the ground of the superconducting junction line. The structure is the same, except that 4 is provided. The superconducting junction line according to the present invention was used. .

【0037】リング発振回路は図4に示される酸化物系
薄膜によって構成した。インダクタのインダクタンスは
30ピコヘンリ、超電導接合の臨界電流は0.2mA,
IcRn値は2mVとした。また、シャント抵抗4は2
オームとした。このようなリング発振回路で、超電導接
合に90%の直流バイアス電流を印加したところ、30
GHzの高周波発振動作が得られた。高周波発振の周期
は、磁束量子信号が超電導接合リングを1周するのに必
要とする時間に相当する。
The ring oscillator circuit was composed of the oxide thin film shown in FIG. The inductor has an inductance of 30 picohenry and the superconducting junction has a critical current of 0.2 mA.
The IcRn value was 2 mV. Also, the shunt resistance 4 is 2
Ohm. When a 90% DC bias current was applied to the superconducting junction in such a ring oscillator circuit,
A high frequency oscillation operation of GHz was obtained. The cycle of high frequency oscillation corresponds to the time required for the magnetic flux quantum signal to make one round in the superconducting junction ring.

【0038】なおシャント抵抗を用いない場合、正常な
リング発振動作は得られなかった。これは磁束量子パル
スのあとに振動が残り、リングの場合、特にこの現象が
顕著に現れるからである。このように本発明に係る超電
導接合線路を用いることによって、酸化物系のリング発
振器を構成し、動作させることができた。
When the shunt resistor was not used, normal ring oscillation operation could not be obtained. This is because vibration remains after the magnetic flux quantum pulse, and this phenomenon is particularly remarkable in the case of a ring. As described above, by using the superconducting junction line according to the present invention, an oxide ring oscillator could be constructed and operated.

【0039】[0039]

【発明の効果】本発明に係わる超電導接合線路は磁束量
子パルスに続く振動を短い時間で納めることができ、且
つ、磁束量子の伝播動作を遅延させることができる。
The superconducting junction line according to the present invention can contain the vibration following the magnetic flux quantum pulse in a short time and delay the propagation operation of the magnetic flux quantum.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明における超電導接合線路の基本的な構成
を示す図。
FIG. 1 is a diagram showing a basic configuration of a superconducting junction line according to the present invention.

【図2】従来の磁束量子を転送する超電導接合線路の一
例を示す図。
FIG. 2 is a diagram showing an example of a conventional superconducting junction line that transfers magnetic flux quanta.

【図3】酸化物系の超電導接合線路で磁束量子信号が伝
搬する様子を示す図。
FIG. 3 is a diagram showing how a magnetic flux quantum signal propagates in an oxide-based superconducting junction line.

【図4】図1に示す超電導接合線路の単位超電導接合線
路の断面構造を示し、(A)は平面図、(B)は(A)
のB−B位置において矢印方向に見た断面図、(C)は
(A)のC−C位置において矢印方向に見た断面図。
4A and 4B show sectional structures of unit superconducting junction lines of the superconducting junction line shown in FIG. 1, where FIG. 4A is a plan view and FIG.
3B is a cross-sectional view as seen in the direction of the arrow at BB position in FIG. 3C, and FIG.

【図5】図4に示した超電導接合線路を伝搬する磁束量
子パルスの動作特性を説明する図。
FIG. 5 is a diagram for explaining operating characteristics of magnetic flux quantum pulses propagating in the superconducting junction line shown in FIG. 4.

【図6】従来の超電導接合線路を伝搬する磁束量子パル
スの動作特性を説明する図。
FIG. 6 is a diagram illustrating operating characteristics of a magnetic flux quantum pulse propagating in a conventional superconducting junction line.

【図7】実施例1に係る超電導接合線路を伝搬する磁束
量子パルスの遅延時間に対するシャント抵抗依存性を説
明する図。
FIG. 7 is a diagram illustrating the shunt resistance dependency of the delay time of the magnetic flux quantum pulse propagating through the superconducting junction line according to the first embodiment.

【図8】フラッシュ型の4ビット・アナログ・デジタル
変換回路に遅延効果に着目した磁束量子回路を応用した
例を示す図。
FIG. 8 is a diagram showing an example in which a magnetic flux quantum circuit focusing on a delay effect is applied to a flash type 4-bit analog-digital conversion circuit.

【図9】超電導接合線路の長さの差によってクロックの
到着に差が生じることを示す図。
FIG. 9 is a diagram showing that there is a difference in clock arrival due to a difference in length of the superconducting junction line.

【図10】図9の例で、各レベル判定回路に入力される
クロック信号波形を示す図。
FIG. 10 is a diagram showing a clock signal waveform input to each level determination circuit in the example of FIG. 9;

【図11】高速の磁束量子信号をデマルチプレクサで4
チャンネルに分配し、周波数を1/4に低減して、超電
導回路の外部に取り出す磁束量子回路に適用した例を示
す図。
FIG. 11: A high-speed flux quantum signal is demultiplexed by 4
The figure which shows the example applied to the magnetic flux quantum circuit which distribute | circulates to a channel, reduces the frequency to 1/4, and takes it out of the superconducting circuit.

【図12】超電導接合線路の長さの差によってクロック
の到着に差が生じることを示す図。
FIG. 12 is a diagram showing that there is a difference in clock arrival due to a difference in length of the superconducting junction line.

【図13】実施例3で採用した超電導接合線路の等価回
路を示す図。
FIG. 13 is a diagram showing an equivalent circuit of a superconducting junction line used in Example 3;

【図14】図13の各RS−FFに入力されるリセット
信号の波形を示す図。
14 is a diagram showing a waveform of a reset signal input to each RS-FF in FIG.

【図15】本発明に係る超電導接合線路を用いたリング
発振回路のブロック構成の等価回路を示す図。
FIG. 15 is a diagram showing an equivalent circuit of a block configuration of a ring oscillation circuit using a superconducting junction line according to the present invention.

【符号の説明】[Explanation of symbols]

1:直流電源、2:超電導接合、3:インダクタ、4:
抵抗、11:基板、12:磁気遮蔽膜、13:層間絶縁
膜、14:下部電極、15:層間絶縁膜、16:抵抗
膜、17:上部電極、18:接合障壁層、19:インダ
クタ、20:コンタクト、30:前段の超電導接合部出
力波形、31:後段の超電導接合部出力波形、40:前
段の超電導接合部出力波形、41:後段の超電導接合部
出力波形、51:トリガ発振部、52:入力側超電導接
合線路、53:超電導接合リング、54:出力側超電導
接合線路。
1: DC power supply, 2: superconducting junction, 3: inductor, 4:
Resistance, 11: substrate, 12: magnetic shielding film, 13: interlayer insulating film, 14: lower electrode, 15: interlayer insulating film, 16: resistance film, 17: upper electrode, 18: junction barrier layer, 19: inductor, 20 : Contact, 30: Output waveform of superconducting junction in front stage, 31: Output waveform of superconducting junction in rear stage, 40: Output waveform of superconducting junction in front stage, 41: Output waveform of superconducting junction in rear stage, 51: Trigger oscillator, 52 : Input side superconducting junction line, 53: Superconducting junction ring, 54: Output side superconducting junction line.

フロントページの続き (72)発明者 樽谷 良信 東京都江東区東雲一丁目14番3号 財団法 人 国際超電導産業技術研究センター 超 電導工学研究所内 (72)発明者 杉山 英行 東京都江東区東雲一丁目14番3号 財団法 人 国際超電導産業技術研究センター 超 電導工学研究所内 (72)発明者 田辺 圭一 東京都江東区東雲一丁目14番3号 財団法 人 国際超電導産業技術研究センター 超 電導工学研究所内 Fターム(参考) 4M113 AA06 AA16 AA25 AA37 AC33 AC44 AD23 AD36 AD42 AD45 AD67 AD68 BB07 BC08 CA34 5J022 AA06 BA05 BA06 CE04 CE08 CF08 CG02 5J056 AA11 BB21 CC00 CC14 CC16 KK03 Continued front page    (72) Inventor Yoshinobu Tarutani             Foundation law, 1-14-3 Shinonome, Koto-ku, Tokyo             International Superconductivity Technology Center             Institute of Electrical Engineering (72) Inventor Hideyuki Sugiyama             Foundation law, 1-14-3 Shinonome, Koto-ku, Tokyo             International Superconductivity Technology Center             Institute of Electrical Engineering (72) Inventor Keiichi Tanabe             Foundation law, 1-14-3 Shinonome, Koto-ku, Tokyo             International Superconductivity Technology Center             Institute of Electrical Engineering F term (reference) 4M113 AA06 AA16 AA25 AA37 AC33                       AC44 AD23 AD36 AD42 AD45                       AD67 AD68 BB07 BC08 CA34                 5J022 AA06 BA05 BA06 CE04 CE08                       CF08 CG02                 5J056 AA11 BB21 CC00 CC14 CC16                       KK03

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】磁束量子を信号の担体とし、酸化物系超電
導体による超電導接合と超電導線のインダクタによって
構成される超電導接合線路において、インダクタの任意
の場所と接地の間に抵抗を配してなることを特徴とする
超電導接合線路。
1. In a superconducting junction line composed of a superconducting junction made of an oxide-based superconductor and an inductor of a superconducting wire, using a flux quantum as a signal carrier, a resistor is arranged between an arbitrary place of the inductor and ground. A superconducting junction line characterized in that
【請求項2】前記超電導線のインダクタのインダクタン
スと抵抗の大きさの比、あるいは超電導接合に通電する
バイアス電流と臨界電流の比によって遅延時間を設定す
る請求項1記載の超電導接合線路。
2. The superconducting junction line according to claim 1, wherein the delay time is set by the ratio of the magnitude of the inductance and the resistance of the inductor of the superconducting wire, or the ratio of the bias current and the critical current applied to the superconducting junction.
【請求項3】磁束量子を信号の担体とし、酸化物系超電
導体による超電導接合と超電導線のインダクタによって
構成される超電導接合線路であって、該超電導接合線路
は1個のインダクタとこれに接続される2個の超電導接
合と接地によって囲まれる超電導ループがカスケードに
接続されるものであるとともに、前記超電導接合の臨界
電流とインダクタのインダクタンスの積を磁束量子の大
きさより十分大きくすることによって、一つの超電導ル
ープ内に複数個の磁束量子信号を一時的に保持できるも
のとすることを特徴とする超電導接合線路。
3. A superconducting junction line composed of a superconducting junction made of an oxide-based superconductor and an inductor of a superconducting wire, wherein the flux quantum is used as a signal carrier, and the superconducting junction line is connected to one inductor and the inductor. Two superconducting junctions and a superconducting loop surrounded by ground are connected in a cascade, and the product of the critical current of the superconducting junction and the inductance of the inductor is made sufficiently larger than the size of the magnetic flux quantum. A superconducting junction line, wherein a plurality of magnetic flux quantum signals can be temporarily held in one superconducting loop.
【請求項4】磁束量子を信号の担体とし、酸化物系超電
導体による超電導接合と超電導線のインダクタと、該イ
ンダクタの任意の場所と接地の間に抵抗を配して構成さ
れる単位超電導接合線路が複数個カスケードに接続され
た超電導接合線路と、該超電導接合線路の一部から分岐
して再び前記超電導接合線路の一部に戻るように接続さ
れた酸化物系超電導体による超電導接合と超電導線のイ
ンダクタと、該インダクタの任意の場所と接地の間に抵
抗を配して構成される単位超電導接合線路が複数個接続
された超電導接合線路とよりなることを特徴とする超電
導発振回路。
4. A unit superconducting junction formed by using a flux quantum as a signal carrier, a superconducting junction made of an oxide superconductor and an inductor of a superconducting wire, and a resistor arranged between an arbitrary place of the inductor and ground. A superconducting junction line in which a plurality of lines are connected in a cascade, and a superconducting junction and a superconducting oxide superconductor connected so as to branch from a part of the superconducting junction line and return to a part of the superconducting junction line again. A superconducting oscillator circuit, comprising: a line inductor; and a superconducting junction line to which a plurality of unit superconducting junction lines configured by arranging a resistor between an arbitrary place of the inductor and the ground are connected.
【請求項5】磁束量子を信号の担体とし、酸化物系超電
導体による超電導接合と超電導線のインダクタと、該イ
ンダクタの任意の場所と接地の間に抵抗を配して構成さ
れる単位超電導接合線路が複数個カスケードに接続され
た超電導接合線路が複数個独立して設けられるととも
に、前記超電導線のインダクタのインダクタンスと抵抗
の大きさの比、あるいは前記超電導接合に通電するバイ
アス電流と臨界電流の比によってそれぞれの超電導接合
線路の遅延時間を調整してそれぞれの超電導接合線路に
入力される信号がほぼ同一のタイミングで出力されるこ
とを特徴とする複数の超電導接合線路よりなる回路。
5. A unit superconducting junction formed by using a magnetic flux quantum as a signal carrier, a superconducting junction made of an oxide superconductor and an inductor of a superconducting wire, and a resistor arranged between an arbitrary place of the inductor and ground. A plurality of superconducting junction lines in which a plurality of lines are connected in a cascade are provided independently, and the ratio of the inductance and the resistance of the inductor of the superconducting wire or the bias current and the critical current of the superconducting junction. A circuit comprising a plurality of superconducting junction lines, characterized in that the delay time of each superconducting junction line is adjusted by a ratio, and signals input to the respective superconducting junction lines are output at substantially the same timing.
JP2002081538A 2002-03-22 2002-03-22 Superconducting junction line Expired - Lifetime JP3737980B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002081538A JP3737980B2 (en) 2002-03-22 2002-03-22 Superconducting junction line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002081538A JP3737980B2 (en) 2002-03-22 2002-03-22 Superconducting junction line

Publications (2)

Publication Number Publication Date
JP2003283324A true JP2003283324A (en) 2003-10-03
JP3737980B2 JP3737980B2 (en) 2006-01-25

Family

ID=29230133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002081538A Expired - Lifetime JP3737980B2 (en) 2002-03-22 2002-03-22 Superconducting junction line

Country Status (1)

Country Link
JP (1) JP3737980B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007115930A (en) * 2005-10-21 2007-05-10 Chugoku Electric Power Co Inc:The Superconducting junction element and superconducting junction circuit
CN110268526A (en) * 2017-02-06 2019-09-20 微软技术许可有限责任公司 Josephson transmission line for superconducting apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007115930A (en) * 2005-10-21 2007-05-10 Chugoku Electric Power Co Inc:The Superconducting junction element and superconducting junction circuit
US8330145B2 (en) 2005-10-21 2012-12-11 The Chugoku Electric Power Co., Inc. Superconducting junction element and superconducting junction circuit
CN110268526A (en) * 2017-02-06 2019-09-20 微软技术许可有限责任公司 Josephson transmission line for superconducting apparatus
CN110268526B (en) * 2017-02-06 2023-08-08 微软技术许可有限责任公司 Josephson transmission line for superconducting devices

Also Published As

Publication number Publication date
JP3737980B2 (en) 2006-01-25

Similar Documents

Publication Publication Date Title
US8330145B2 (en) Superconducting junction element and superconducting junction circuit
US6486756B2 (en) Superconductor signal amplifier
US6549059B1 (en) Underdamped Josephson transmission line
US6580310B2 (en) Double flux quantum superconductor driver
US7772871B2 (en) Method and apparatus for high density superconductor circuit
US6518673B2 (en) Capacitor for signal propagation across ground plane boundaries in superconductor integrated circuits
US7268713B2 (en) Superconducting circuit
JP4681755B2 (en) Single flux quantum logic circuit and single flux quantum output conversion circuit
JP4130065B2 (en) Superconducting quantum interference device and superconducting circuit
US7095227B2 (en) Superconducting driver circuit
Herr et al. High speed data link between digital superconductor chips
US6483339B1 (en) Single flux quantum series biasing technique using superconducting DC transformer
Hashimoto et al. A design approach to passive interconnects for single flux quantum logic circuits
Chonigman et al. Optimization of passive transmission lines for single flux quantum circuits
JP2003028898A (en) Sampler and measurement method
JP2003283324A (en) Superconducting junction line
Hashimoto et al. Implementation of a 4/spl times/4 switch with passive interconnects
Rainal Impedance and crosstalk of stripline and microstrip transmission lines
JP4524126B2 (en) Superconducting SFQ circuit
Miller et al. A single-flux-quantum demultiplexer
JP4340748B2 (en) Superconducting oscillator
US5939895A (en) Frozen wave high speed receiver
Tarutani et al. Oscillation of SFQ pulse in oxide JTL [Josephson transmission line]
EP0354547B1 (en) Regulator of power source for superconducting circuit
JP2001345695A (en) Superconductive signal generator

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20031210

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050708

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050719

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050916

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20051018

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20051028

R150 Certificate of patent or registration of utility model

Ref document number: 3737980

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081104

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313117

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081104

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081104

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091104

Year of fee payment: 4

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091104

Year of fee payment: 4

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091104

Year of fee payment: 4

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091104

Year of fee payment: 4

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101104

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101104

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111104

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121104

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121104

Year of fee payment: 7

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121104

Year of fee payment: 7

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131104

Year of fee payment: 8

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

EXPY Cancellation because of completion of term