JP2001345695A - Superconductive signal generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a signal of a high frequency band difficult to realize with a circuit of a conventional semiconductor element. SOLUTION: Logical signal sequence data previously programmed with a circuit of the semiconductor element disposed in an ambient temperature area is introduced into a superconductive shifter in which a magnetic flux quantum is used as a carrier, shifted by a clock by the magnetic flux quantum, and logical signal sequence data of a high speed such as 10 GHz or more is output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for generating an arbitrary programmable logic signal sequence necessary for performing, for example, evaluation of operating characteristics of a digital circuit.

[0002]

2. Description of the Related Art A conventional programmable signal train generator is constructed by combining a semiconductor oscillation circuit and the like. In particular, in order to evaluate the operating characteristics of a high-speed digital circuit, a programmable signal generator capable of generating a high-frequency signal corresponding to this is required. Such a high-speed signal generator is composed of a high-speed semiconductor element such as GaAs HEMT, and an apparatus for generating a signal exceeding 10 GHz has been manufactured.

[0003]

By using a semiconductor circuit, an apparatus for generating a signal train exceeding 10 GHz has been obtained. However, a higher value is required for the operating frequency required for a programmable signal train generator required for testing a high-speed circuit as the performance of a semiconductor element is improved. As a matter of course, even if a device for generating a signal train is made of an InP-based heterobipolar transistor having a high-speed performance among semiconductors, a signal train generated by this device will not produce an InP-based heterobipolar transistor having the same performance. The limitations of high-speed performance cannot be evaluated. In order to evaluate the operation of a circuit that is considered to be the fastest in a semiconductor, it is necessary to configure a signal train generator with elements that have the possibility of exhibiting higher-speed performance than the semiconductor to be evaluated.

A superconducting circuit using flux quanta as a carrier of a signal is a picosecond high-speed signal, that is, several tens of GHz or one hundred GH.
There is a possibility that a high-speed signal of z or more can be generated. However, conventionally, such a high-speed signal is generated by a magnetic flux quantum circuit,
There was no concept to take this out directly and use it. Rather, a method has been adopted in which the frequency of a signal processed at high speed is divided and output from a superconducting magnetic flux quantum circuit to an external semiconductor circuit by a parallel signal line.

SUMMARY OF THE INVENTION It is an object of the present invention to obtain a programmable high-frequency signal sequence which is difficult to realize with a conventional semiconductor device. The present invention is to provide a signal generator for generating a high-speed signal sequence according to a program set by the user.

[0006]

According to the present invention, a conventional semiconductor device generates "0" and "1" states of a logic signal in a predetermined permutation, and associates this signal string with the presence or absence of a superconducting flux quantum. The present invention realizes a signal generator that generates the same signal train in the "0" and "1" states at a high speed by processing with a superconducting circuit.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a basic configuration of a signal generator according to the present invention. In the drawing, reference numeral 1000 denotes a room temperature region, in which a data storage circuit 1 using a semiconductor element is shown.
001, Logic signal string data setting by semiconductor element-input circuit 1002 and signal output circuit 10 by semiconductor element
03 is arranged. 2000 is a superconducting temperature region,
Here, superconducting signal sequence generation circuit 2001 is arranged. The data storage circuit 1001 in the room temperature region 1000 stores necessary data in accordance with a logic signal sequence to be obtained as an output, and in response to this, sets the logic signal sequence data-input circuit 1002 from the logic signal sequence pattern and the trigger. A signal and a clock signal are output. These are supplied to the superconducting signal train generation circuit 2001 through a normal signal line in the same environment as the room temperature region. On the other hand, the superconducting signal train generation circuit 2
The high-speed signal train generated in 001 is output through a signal output circuit 1003 through, for example, a coaxial cable in the same environment as a room temperature region.
Conveyed to. The signal output circuit 1003 is a so-called buffer circuit, and is not always necessary depending on the form of a circuit using the high-speed signal sequence generated by the superconducting signal sequence generation circuit 2001.

An embodiment for dealing with some logic signal sequence data will be specifically described below.

First Embodiment FIG. 2 shows a block configuration of a first embodiment. The signal trains in the "0" and "1" states of the logic signals generated by the semiconductor elements are introduced into a shift register formed of superconducting elements and stored, and are output by a high-speed clock signal. This is an example of a signal generation circuit for generating the signal.

Reference numeral 201 denotes a conversion circuit for converting a level signal into a magnetic flux quantum.
Is converted into a magnetic flux quantum. 202
Is a clock generation circuit based on magnetic flux quanta.
01 is converted to a predetermined clock signal. Reference numeral 203 denotes a conversion circuit for converting a level signal into a magnetic flux quantum, which has the same function as that of the conversion circuit 201 and converts a clock signal supplied from the logic signal sequence data setting / input circuit 1002 into a magnetic flux quantum. Reference numeral 204 denotes a confluence buffer, which includes a clock generation circuit 202 and a conversion circuit 203.
Is passed through. Reference numeral 205 denotes a conversion circuit for converting a level signal into a magnetic flux quantum, which has the same function as that of the conversion circuit 201,
2 is converted into a magnetic flux quantum. Reference numeral 206 denotes a shift register.
Is used as a data input signal, and the magnetic flux quantum given from the confluence buffer 204 is used as a clock signal. A signal amplification circuit 207 amplifies the output of the shift register 206 to a predetermined level and has a predetermined output impedance. Specific examples of each component will be described later. In this embodiment, the shift register 206 has a 16-bit configuration. Therefore, the input logic signal string data is 1
The limit is 6 bits, and the clock generation circuit 202 generates a 16-bit clock signal corresponding to the trigger signal.

The generation of high-speed logic signal sequence data according to this embodiment will be described.

First, a signal sequence corresponding to a high-speed signal sequence to be output created by the logic signal sequence data setting-input circuit 1002 is stored in the shift register 206. For this purpose, the signal sequence set in the logic signal sequence data setting-input circuit 1002 is introduced into the conversion circuit 205 as a signal sequence of a frequency generated by the semiconductor element in the room temperature region 1000.
At the same time, a clock signal having the same frequency is introduced from the logic signal sequence data setting / input circuit 1002 to the conversion circuit 203. The shift register 206 is provided with a magnetic flux quantum corresponding to the signal sequence to be output from the conversion circuit 205, and a clock signal corresponding thereto from the conversion circuit 203 as a magnetic flux quantum. As a result, in a state where a signal sequence having a predetermined number of bits is output from the logic signal sequence data setting / input circuit 1002, the shift register 206 is in a state where data corresponding to the same signal sequence is stored.

Next, a trigger signal is applied to the clock generation circuit 202 from the logic signal string data setting / input circuit 1002. Correspondingly, a high-speed 16-bit clock signal generated by the magnetic flux quantum is generated from the clock generation circuit 202. Since the clock signal generated from the clock generation circuit 202 is supplied to the shift register 206 via the confluence buffer 204, the shift register 20
The high-speed signal sequence corresponding to the signal sequence stored in 6 is output from the shift register 206. This output is amplified by the amplifier circuit 207 and provided to the signal output circuit 1003 in the room temperature region 1000.

FIG. 3 schematically shows the relationship between the low-speed signal train provided by the logic signal train data setting-input circuit 1002 in the room temperature region 1000 and the high-speed signal output obtained by the amplifier circuit 207 in the superconducting temperature region 2000. It is shown.
In the figure, the horizontal axis indicates time, and the vertical axis indicates signal output.
The time axis on the horizontal axis is a level far apart, and the size of the figure has no meaning. Here, it is significant only in that the output signal is obtained after the setting of the input signal and the input / output signal is obtained in the same pattern. The upper part of the figure shows a state where a 16-bit logical data signal is input from the logical signal string data setting-input circuit 1002 at a low speed corresponding to a frequency of 10 kHz. In FIG. 3, for simplicity, 1,1,
8 bits of 0, 1, 0, 1, 1, 1 are shown. The input signal stored in the shift register 206 at the lower stage is generated by the clock generation circuit 202 activated by the trigger signal given from the logic signal string data setting-input circuit 1002 to generate a high-speed 16-bit clock.
This shows a state in which a logic signal for eight bits of 1, 0, 1, 0, 1, 1, 1 has been generated. By changing the bias current for the superconducting junction of the clock generation circuit 202,
A faster clock can be used. If the relationship between the bias current for the superconducting junction of the clock generation circuit 202 and the frequency of magnetic flux quantum generation is associated in advance, an output at an arbitrary speed can be obtained.

Next, a more specific configuration example of each component shown in FIG. 2 will be described.

FIG. 4 shows an example of the conversion circuit 201 and the clock generation circuit 202. In this embodiment, the conversion circuit 20
In this example, the output magnetic flux quantum of No. 1 is a clock generation circuit 202 including a branch circuit SP, a superconducting junction line JTL, and a confluence buffer CB. The conversion circuit 201 to which a trigger signal can be applied generates a magnetic flux quantum from a dc input and outputs this via a superconducting junction line, as will be described later. Conversion circuit 2
The magnetic flux quantum output from the superconducting junction line No. 01 is divided into two magnetic flux quantums by a branch circuit 132 and applied to superconducting junction lines 133 and 134 provided at the subsequent stages. A confluence buffer 136 is provided at the output stage of the superconducting junction line 134. The output of another superconducting junction line 135 is added to the confluence buffer 136, and the output of one of the superconducting junction lines JTL is output as a magnetic flux quantum. Although the description is omitted, the series circuit of the superconducting junction line and the branch circuit on the upper side of the figure and the series circuit of the superconducting junction line and the confluence buffer on the lower side of the figure are composed of a paired branch circuit and a confluence buffer. Because the above operation is repeated by the superconducting junction lines, a clock generation circuit is obtained in which the output flux quanta generates magnetic flux quanta that is a multiple of the number of repetitions of one magnetic flux quantum. In the present embodiment, a 16-bit clock generation circuit that generates 16 flux quanta for one flux quantum is used. Also, the superconducting junction line JTL
By changing the bias current of the superconducting element, the propagation speed of the magnetic flux quantum can be changed, so that the frequency of the clock signal can be changed.

FIG. 5 shows an example of the conversion circuit 205 and the shift register 206. In this embodiment, the set / reset flip-flop rs-FF is a superconducting junction line JT
A lower circuit connected in cascade through L and an upper circuit connected to the cascade of the superconducting junction line JTL and the branch circuit SP by using a clock signal introduced through the confluence buffer 203. Set / reset flip-flop rs in which clock signals branched by branch circuit SP are at corresponding positions
This is an example in which the configuration is added as a reset signal of -FF.

First, logic signal string data setting-input circuit 1
A description will be given from the introduction of the data given from 002 into the shift register 206. The output flux quantum of the conversion circuit 205 is introduced into the first set / reset flip-flop 146, and 146 is set to a state corresponding to the data input. The clock signal from the conversion circuit 203 introduced from the confluence buffer 204 is
1, a superconducting junction line 143 divided into two magnetic flux quanta by a branch circuit 142 and provided at each subsequent stage.
144. The clock signal output from the superconducting junction line 143 is propagated via the superconducting junction line JTL and the branch circuit SP connected in cascade. When the clock signal is propagated through the superconducting junction line 145 to the set / reset flip-flop 146 and applied to the set / reset flip-flop 146, a signal corresponding to the state of 146 is output to the superconducting junction line 14.
7 to the second-stage set / reset flip-flop 148.

Next, the second signal of the data signal is introduced into the first set / reset flip-flop 146 via the conversion circuit 205, and 146 is set to a state corresponding to the second data input. The second clock signal from the conversion circuit 203 introduced from the confluence buffer 204 is, as described above, a superconducting junction line J.
The signal is propagated to the subsequent stage while repeating propagation and division by the TL and the branch circuit 142. Second from superconducting joint line 149
A signal corresponding to the state of the set / reset flip-flop 148 is transmitted to the third set / reset flip-flop 151 via the superconducting junction line 150 by the clock signal applied to the set / reset flip-flop 148 of the stage. Thereafter, the first set / reset flip-flop 146
Is reset, and the second-stage set-reset flip-flop 148 is set to a state corresponding to the second data input.

In this way, the shift is repeated one after another, and the first set / reset flip-flop 146
To the final set-reset flip-flop 15
2 stores a signal corresponding to the signal sequence given from the logic signal sequence data setting-input circuit 1002.

Next, a description will be given of outputting the logic signal string data stored in the last set / reset flip-flop 152 of the shift register 206 from the first set / reset flip-flop 152 as a high-speed signal.

As described with reference to FIG. 4, a magnetic flux quantum is generated from the conversion circuit 201 by the trigger signal given from the logic signal string data setting-input circuit 1002, and thus, a predetermined number of bits and A high-speed clock signal is generated. This clock signal is introduced via the confluence buffer 204 and propagated to the subsequent stage via the superconducting junction line JTL and the branch circuit SP, similarly to the introduction of data into the shift register 206. When the first clock signal is divided by the branch circuit 142 and applied to the final set / reset flip-flop 152 via the superconducting junction line 144,
The data stored in 52 is output via superconducting junction line 153. Each time the clock signal divided by the branch circuit 142 is transmitted to the subsequent stage, the clock signal is divided by the branch circuit SP and the set / reset flip-flop rs-FF at the corresponding position is reset to store the stored data by one stage. Shift by one. Thus, when the last clock signal is applied to the last-stage set / reset flip-flop 152 via the superconducting junction line 141, the branch circuit 144 and the superconducting junction line 144, the clock signal is successively shifted and stored in the 152. The last data is output via the superconducting junction line 153. Shift register 2 output one after another via superconducting junction line 153
As described above, the output of the data 06 is in the room temperature region 10.
Transmitted to 00.

FIGS. 6 to 8 are diagrams for explaining an example of the signal amplifying circuit 207. FIG. 6 is a schematic diagram of the constituent blocks.
FIG. 7 shows an equivalent circuit, and FIG. 8 shows a plan view when mounted on a substrate.

Reference numeral 10 denotes a superconducting magnetic flux quantum circuit. In the embodiment of the present invention, conversion circuits 201, 203 and 20 are used.
5 is a circuit corresponding to FIG. This output, the flux quantum SF
Although Q is a signal to be amplified, the configuration of this circuit will be briefly described first. The superconducting flux quantum circuit 10
This is an example of a circuit that generates a magnetic flux quantum pulse by a trigger signal source 1 as shown in the equivalent circuit of FIG. In the superconducting flux quantum circuit 10, inductor 2 ₁ and the superconducting junction 5 _1, 5
AC power source 1 as a pulse source in superconducting closed loop consisting of _two
Alternating current is supplied through the superconducting junction 5 _3. One input line of the AC power supply 1 is connected to the ground 3 via the inductor 2 _2, the other of the trigger signal source 1 it is also connected to ground 3. By applying a current to the superconducting closed loop, one magnetic flux quantum is generated in the superconducting closed loop. Here, reference numeral 6 denotes an appropriate bias power supply, one end of which is connected to the superconducting junctions 5 ₁ and 5 ₂ in order to supply an appropriate current to the superconducting junctions 5 ₁ and 5 _2.
1, 5 ₂ and the other end connected to ground 3. The other end of each superconducting junction 5 _1, 5 ₂ is connected to ground 3. As the superconducting junction, a junction in which a resistor was connected in parallel to a tunnel junction, or a junction having no history in current-voltage characteristics was used.

Next, the signal amplifying circuit 207 will be described with reference to FIG. 6. However, since the figure and the description are complicated, equivalent components are denoted by the same symbol marks, and reference numerals are omitted as appropriate. The flux quantum to be amplified is first introduced into a first-stage branch circuit (indicated by SP) 12. The magnetic flux quantum divided into two in the branch circuit 12 is introduced into the second branch circuit via superconducting junction lines (indicated by JTL) 13 and 14. The magnetic flux quantum divided into two in the second-stage branch circuit 15 is introduced into the third-stage branch circuit via the superconducting junction lines 17 and 18. The magnetic flux quantum divided into two in the third-stage branch circuit 20 is introduced into the fourth-stage branch circuit via the superconducting junction lines 21 and 22. In the embodiment shown in the figure, the flux quanta divided into two by the final-stage and fourth-stage branch circuits 31 are superconducting junction lines 41 and 42.
Through superconducting quantum interference devices (indicated by JI) 61, 62
Are applied to the magnetic field application control lines 51 and 52. The superconducting junction line 7 is connected to each of the magnetic field application control lines 51 and 52.
1 and 72 are connected and grounded via final terminating resistors 81 and 82. Reference numeral 90 denotes a power supply, which supplies a current to a voltage output line 91 of the superconducting quantum interference device. A series circuit of the voltage output line 91 and the power supply 90 connected in series is grounded at both ends.

Each of the other ends of the branch circuits whose description is omitted has the same configuration. Therefore, here, a four-stage branch circuit is provided, and 16 superconducting quantum interference devices JI are connected in series. FIG. 7 shows an equivalent circuit of this configuration in all of the uppermost and lowermost parts, omitting parts in the middle, and corresponding components are given the same reference numerals as in FIG.

FIG. 8 specifically shows the top three stages and the bottom three stages of the signal amplifying circuit shown in FIGS. 6 and 7, with the middle part omitted from the illustration. It is a top view showing an example. 8, the same components as those shown in FIGS. 6 and 7 are denoted by the same reference numerals. Also, for the sake of simplicity,
The illustration of the insulating layer is omitted, and the connection relationship with the necessary conductive layer is understood.

Reference numeral 110 denotes an input inductor of the superconducting quantum interference device 61, and both ends are used as lower electrodes of a superconducting junction. 112 and 113 are upper electrodes of the superconducting junction. 111 is a superconducting quantum interference device 62
Is a superconductor that also serves as a connection conductor to the input inductor. Superconductor 110 as lower electrode and upper electrode 112
And 113 form a superconducting junction, and the contact area of both electrodes is set so that superconductor 111 also serving as a connection conductor to the input inductor of superconducting quantum interference device 62 forms a resistive connection with upper electrodes 112 and 113. Have been. Therefore, superconductor 110, upper electrodes 112 and 11
3. The superconductor 111 forms the superconducting loop of the superconducting quantum interference device 61. For the superconducting quantum interference device 62 and below, these relationships are in the form of a repetitive pattern. The lowermost superconductor 115 is connected to the magnetic shielding film 100 at a connection point 116. The input inductor 110 of the uppermost superconducting quantum interference device 61 is directly connected to the voltage output line 91, and the voltage output line 91 is directly connected to the output pad 101 and the power supply connection pad 102.

In the input inductor 110 of the superconducting quantum interference device 61, control lines 51 for applying a magnetic field are arranged in an overlapping manner via an insulating film. As shown in FIGS. 6 and 7, the magnetic field application control line 51 is configured such that the magnetic flux quantum superconducting junction lines 41 and 71 are formed at the input and output ends thereof. 51, two superconducting junctions composed of upper electrodes 127 and 128 connected in resistance and a lower electrode 129 connected in resistance to the magnetic shielding film 100, and upper electrodes 122 and 123 of the same configuration. It is formed by two superconducting junctions including the lower electrode 124. Furthermore, the control line 51 for applying a magnetic field
Is connected to the magnetic shield film 100 by a resistor and connected to the magnetic shield film 100 by a resistor.

In the present embodiment, the superconducting quantum interference devices other than the lowermost superconducting quantum interference device are formed in portions where the magnetic shielding film 100 is cut out, and one of the superconducting junctions of the lowermost superconducting quantum interference device is formed. The electrodes are connected to the magnetic shielding film 100 in the entire area.

The biggest factor in lowering the frequency of the superconducting flux quantum circuit is that the effect of the parasitic capacitance increases as the operating frequency increases. When using a magnetic shielding film of the ground potential in a superconducting quantum interference device,
A capacitance is formed between the electrode and the magnetic shielding film via the interlayer insulating film. Capacitance of 0.1 pF for devices with dimensions of tens of microns
To 1 pF.

In the case of one stage of the superconducting quantum interference device, the electric charge stored in the capacitance is not a magnitude that has a significant influence on the picosecond operation. However, when a large number of superconducting quantum interference devices are connected in series, the capacitance increases in proportion to the number of devices and the generated voltage increases, so that the amount of accumulated charge increases approximately in proportion to the square of the number of devices. However, according to the structure of the superconducting signal amplifying circuit according to the present embodiment, since the superconducting quantum interference device does not have a magnetic shielding film, such a rise time delay factor does not exist. The capacitance component with the ground exists between the electrode of the superconducting quantum interference device and the control line,
Estimated from the fact that the crossing area is relatively small and the interlayer insulating film is relatively thick, it is 1/20 or less of the accumulation time. Therefore, in the superconducting driver circuit according to the present embodiment, it was possible to amplify and output a signal having a high frequency of 10 GHz or more.

The width of the superconducting wiring and the distance between the superconducting wiring and the ground line were adjusted so that the impedance of the output line became 50 ohms. The output signal from the signal amplifier circuit was a current of 0.18 mA and a voltage of 6 mV, which could be a value close to the impedance of the output line, so that the impedance matching with a circuit including a semiconductor element in a room temperature region could be improved.

Second Embodiment In the first embodiment described above, the logic signal sequence data input to the shift register 206 to be output at a high speed is output only once at a high speed. The output of the shift register 206 is fed back and circulated as the input of the shift register 206, so that the output can be repeatedly output by one input operation.
FIG. 9 shows a block configuration of the second embodiment, and FIG. 10 shows a block configuration of a shift register that can be used for feedback in the second embodiment. In FIG. 9, components having the same reference numerals as those in FIG. 2 have the same functions. As apparent from a comparison between FIG. 2 and FIG.
The biggest difference between the first embodiment and the first embodiment is that the shift register 206
Is provided with a shift register 212 for circulating the output of the shift register 206 again as an input of the shift register 206.

The conversion circuit 205 is provided in the shift register 206.
, And a clock signal via the conversion circuit 203, respectively, from the logic signal sequence data setting-input circuit 1002, and stored. In this case, in the second embodiment, since the logic signal string data output from the shift register 206 is input again via the shift register 212, the logic signal string data is stored in the confluence buffer 21.
0 is introduced. Logic signal string data setting—the clock signal supplied from the input circuit 1002 is
3, the confluence buffer 20
4 is the same as in the first embodiment. The clock signal from the clock generation circuit 202 is once introduced into the shift register 212, derived via the upper circuit connected to the cascade of the superconducting junction line JTL and the branch circuit SP, and then introduced via the confluence buffer 204. . The output of the shift register 206 is divided by a branch circuit 211, one of which is added to the signal amplification circuit 207 as in the first embodiment, while the other is supplied via a shift register 212 after a predetermined time delay. The shift register 20 is again transmitted via the confluence buffer 210.
6 is introduced.

FIG. 10 shows a configuration example of the 4-bit shift register 212 for circulating the output of the shift register 206 again as the input of the shift register 206. FIG.
Is essentially the same as the configuration of the shift register 206 described with reference to FIG. 5, and those denoted by the same reference numerals as those in FIG. 5 have equivalent functions. The shift register 212 receives the first set via the superconducting junction line 145 via the superconducting junction line JTL and the upper circuit connected to the cascade of the branch circuit SP.
The only difference from the shift register 206 is that the clock signal applied to the reset flip-flop 146 is derived via the branch circuit 154. Of course, the number of bits required for the shift register 206 to store the logic signal sequence data is
Naturally, the difference is that 2 is the number of bits required to circulate the output of the shift register 206 again as the input of the shift register 206. The number of bits required for the shift register 212 indicates the time required for the clock signal to pass through the two shift registers,
It is sufficient if the number is equal to or greater than a value obtained by dividing by the time required for the step shift. This value is set to 4 in the second embodiment.

The signal generator of the second embodiment was operated in the following procedure. Logic signal string data setting in the room temperature region 1000-16-bit logic data from the input circuit 1002 via the conversion circuit 205 and the confluence buffer 210, and 16-bit clock signal via the conversion circuit 203 and the confluence buffer 204, respectively.
It was input to the shift register 206 as an initial input. Subsequently, a trigger signal was applied to the conversion circuit 201 from the logic signal string data setting / input circuit 1002 in the room temperature region 1000, and a clock signal was generated from the clock generation circuit 202.
In the second embodiment, the clock generation circuit 202 generates clock signals of the number obtained by adding the number of bits of the two shift registers 206 and 212.

As described in the first embodiment, 16 bits of data are stored in the shift register 206 by the initial input. The shift register 212 has no data. Subsequently, the clock signal generated by the clock generation circuit 202 is applied to the shift register 206 via the shift register 212 and the confluence buffer 204.

Therefore, the logic signal sequence data stored in the shift register 206 is sequentially output and sent to the signal output circuit in the room temperature region 1000 via the signal amplifier circuit. At the same time, the output of the shift register 206 is applied to the shift register 212 via the branch circuit 211. As the shift register 206 sequentially outputs its output according to the clock signal, the shift register 21
The output of the shift register 206 to which 2 has been added is also shifted and returned to the shift register 206 via the confluence buffer 204. After the lock generation circuit 202 generates a predetermined number of clock signals, the shift register 2
The same data as initially set to 06 is stored.

Subsequently, when a trigger signal is repeatedly applied to the conversion circuit 201 from the logic signal string data setting / input circuit 1002 in the room temperature region 1000 and a clock signal is generated from the clock generation circuit 202, the same operation as that described above is performed. Are repeated, and high-speed logic signal string data can be output repeatedly.

FIG. 11 shows a room temperature region 10 according to the second embodiment.
10 schematically shows the relationship between the low-speed signal sequence provided by the logic signal sequence data setting-input circuit 1002 and the high-speed signal output obtained by the amplifier circuit 207 in the superconducting temperature region 2000. In FIG. 11, similarly to FIG. 3, the horizontal axis indicates time, and the vertical axis indicates signal output. However, the time axis on the horizontal axis is a level far apart, and the size of the figure has no meaning. Here, it is meaningful only in that an output signal is obtained after setting an input signal, an input / output signal is obtained in the same pattern, and an output signal is repeatedly obtained by setting one input signal. In the upper part of the figure, the logic signal string data setting-frequency 10 k from the input circuit 1002
This shows a state where a 16-bit logical data signal is input at a low speed corresponding to Hz. In FIG. 11, for simplicity, 1,1,1,
10 bits of 0, 1, 1, 1, 0, 1, 1 are shown.
The input signal stored in the shift register 206 at the lower stage is generated by generating a high-speed 16-bit clock by the clock generation circuit 202 activated by the trigger signal given from the logic signal string data setting-input circuit 1002 to 10 GHz.
Shows a state where 10-bit logic signals of 1,1,1,0,1,1,1,0,1,1 have been repeatedly generated. By changing the bias current for the superconducting junction of the clock generation circuit 202, a higher-speed clock can be obtained. Here, T is a repetition period of the trigger signal given from the logic signal sequence data setting-input circuit 1002, and for example, the repetition frequency can be set to 100 MHz.

What is important in such an internal clock operation of the second embodiment is that a bit signal string of logical data is output at exactly a predetermined timing in a series of signal generation cycles. In the operation of the shift register, a bit signal first arrives at each stage, and then a clock signal is input to transfer the bit signal. If the clock signal comes in before the bit signal arrives, this stage is empty,
Even if the original input bit is "1", "0" is sent to the subsequent stage, resulting in malfunction. Conversely, if a bit signal continues to enter before the clock signal enters, a malfunction similarly occurs.

In a single shift register, as long as a bit signal and a clock signal are input in synchronization, a correct operation is executed. When the output bit signal sequence from the shift register is taken into the same shift register again as in the second embodiment, it is important that the bit signal and the clock signal are supplied at a predetermined timing as described above. Becomes

In general, considering that a shift register is formed by a superconducting circuit on one substrate, and a bit signal output from the shift register is transferred to its input point and input again, the time required for this transfer is as follows. , The transfer time between stages in the shift register is longer. On the other hand, it takes a time corresponding to the number of stages to pass the clock signal through the shift register via the superconducting junction line JTL and the upper circuit connected to the cascade of the branch circuits SP. It is extremely difficult to match these time delays with a superconducting circuit formed on the substrate.

In the circuit configuration of the second embodiment, 16b
Immediately before the operation of the it shift register 206 is executed, a bit signal sequence is stored in the shift register 206,
The 4-bit shift register 212 is empty. The clock signal from the clock generation circuit 202 is input to the data signal output side of the shift register 212, and at the moment when the first bit signal from the shift register 212 reaches the shift register 206, the shift register 2
The clock signal has not yet reached the last stage of 06. However, since the bit signals of the shift register 212 are all “0”, no malfunction occurs. The first bit signal of the shift register 206 is the shift register 21
2, at the moment of reaching the last stage of the shift register 206, that is, the signal input point, the data is transferred via the superconducting junction line JTL of both shift registers and the upper circuit connected to the cascade of the branch circuit SP. The clock signal should have reached the last stage of the shift register 206, that is, the signal input point.

As described above, by setting the shift register 212 to a necessary and sufficient number of stages and inputting the clock signal to the data signal output point side of the shift register 212, the shift register 212 can be set in the shift register 206 without any bit shift. A bit signal sequence could be repeatedly generated at high speed.

An external alternating current to the superconducting circuit becomes a noise source and causes a malfunction. In the second embodiment, since the alternating current input required at the time of operation is only the repetition period signal which is the trigger signal given from the logic signal string data setting-input circuit 1002, the malfunction of the superconducting circuit can be reduced. . Moreover, since a sine wave can be used as the trigger signal source 1 as a repetition period signal applied to the conversion circuit 201, the repetition frequency can be increased as necessary.

Third Embodiment According to the second embodiment, the logic signal sequence data can be repeatedly generated only by setting the logic signal sequence data in the shift register 206 once. However, it is necessary to add a trigger signal as a repetition period signal. there were. In the third embodiment, by providing the ring oscillation circuit at the preceding stage of the clock generation circuit, if one trigger signal is input to the ring oscillation circuit, the logic signal sequence data is set in the shift register 206 only once and the logic is repeated. The signal sequence data may be generated.

FIG. 12 shows an overall configuration of the third embodiment, and FIG. 13 shows circuit examples of the conversion circuit 201 and the ring oscillation circuit 213, respectively. As is clear from comparison between FIGS. 9 and 12, the third embodiment differs from the second embodiment except that a ring oscillation circuit 213 is inserted between the conversion circuit 201 and the 4-bit shift register 212. Absent. In the third embodiment, when a trigger signal is given from the logic signal sequence data setting-input circuit 1002, the ring oscillation circuit 213 generates the repetitive trigger signal in the second embodiment by the clock generation circuit 20.
2 and an output signal as described with reference to FIG. 11 is obtained.

FIG. 13 is the same as the SFQ circuit described in FIG. The configuration and operation of the ring oscillation circuit 213 are as follows. Here, the same components as those of the above-mentioned reference numerals are used for the constituent elements of the circuit.

Ring oscillation circuit 213 includes a superconducting closed loop composed of inductor 2 and superconducting junction 5 connected in an appropriate number of cascades, includes two connection points functioning as splitters, and a superconducting junction functioning as a unidirectional circuit. It is assumed. Connection point of the ring oscillator circuit 213 flux quanta through the inductor 2 ₁₁ from converter 201 J
When input to P ₁ , it is split and propagated in the respective directions of inductor 2 ₁₂ and inductor 2 ₁₃ . The flux quantum propagated in the direction of the inductor 2 ₁₂ is successively propagated through the superconducting closed loop of the superconducting junction line.
When it reaches the connection point JP ₂ via ₁₄ , the inductor 2
It is divided ₁₅ and in each direction of the inductor 2 ₁₆ is propagated. Flux quantum propagated in the direction of the inductor 2 ₁₅ is added as a trigger signal to the clock generation circuit 202.

[0053] flux quantum propagated in the direction of the inductor 2 ₁₃ flux quantum and the inductor 2 ₁₆ is propagated in the direction of, since those orbiting one ring in the opposite direction, if allowed to stand, in the ring Collision disappears. The inductor 2 ₁₇ , the inductor 2 ₁₈ and the inductor 2 ₁₉ , and the superconducting junctions 5 ₁₁ , 5 ₁₂ and 5 ₁₃ constitute a one-way circuit for preventing this. Flux quantum propagated in the direction of the inductor 2 ₁₃ is being successively propagate superconducting closed loop of the superconducting junction ring 300, when it reaches the inductor 2 _17, the superconducting junction 5 ₁₂ and 5 ₁₃ through the superconducting junction 5 ₁₁ It will be added to the parallel circuit. As a result, the magnetic flux quantum propagated in the direction of the inductor 2 ₁₃ will disappear here. On the other hand, the magnetic flux quantum propagated in the direction of the inductor 2 _16, regardless of the existence of one-way circuit, superconducting junction ring 3
00 superconducting closed loops. Of course, the propagation of flux quanta that are propagated in the direction of the inductor 2 ₁₃ prior to the flux quantum that is propagated in the direction of the propagating direction of the inductor 2 ₁₃ magnetic flux quantum and the inductor 2 ₁₆ will collide since it should be prevented, a position constituting a one-way circuit in the ring should be an position close to JP ₁ counterclockwise when viewed connection point JP ₁ as a starting point.

That is, the magnetic flux quantum inputted from the conversion circuit 201 to the ring oscillation circuit 213 is
While circulating in the 3, it will be added as a trigger signal to the clock generation circuit 202 outputs a flux quantum in each pass through the connection point JP _2.

By the way, when the flux quantum that Ichi循ring oscillator circuit 213 passes through the connection point JP _1, made here in the inductor 2 ₁₁ and be propagated is divided in each direction of the inductor 2 _12. Flux quanta propagate in the direction of the inductor 2 ₁₂ will circulate the ring oscillator circuit 213, a magnetic flux is a clock generation circuit 202 is necessary to output a magnetic flux quantum, which is propagated in the direction of the inductor 2 ₁₁ Since the quantum is transmitted in the direction of the conversion circuit 201, it is useless if the magnetic flux quantum circulates normally in the ring oscillation circuit 213. However, the magnetic flux quanta propagate in the direction of the inductor 2 ₁₁ is that only disappear in the conversion circuit 201 does not become an obstacle.

According to the third embodiment, the magnetic flux quantum is periodically sent from the ring oscillation circuit 213 to the clock generation circuit 202 only once the trigger signal is given. By using this as a repetitive periodic signal, a logical signal sequence could be sent out without any need for an AC signal from a room temperature system during operation. In this case, it is clear that the repetition frequency can be further increased.

The superconducting signal generator of the present invention can be manufactured using an oxide superconducting thin film. That is, L
A magnetic shielding film was formed of a Y, Ba, and Cu oxide superconducting thin film on a single crystal substrate of a, Sr, and Al oxide. La, Sr,
A Y, Ba, Cu oxide superconducting thin film as an electrode through an interlayer insulating film of Al oxide or Sr, Ti oxide,
A superconducting junction using a Ce oxide thin film as an insulating layer was produced.
The superconducting junction was a ramp edge type junction, and a layer in which the end surface of the lower superconducting electrode was damaged by Ar ions was a superconducting coupling layer. A superconducting junction was formed between the coupling layer and the upper and lower superconducting electrodes. Au thin film is used as a resistance element, and Au
Both sides of the film were connected by Y, Ba, and Cu oxide superconducting electrodes.

Also, these superconducting signal generators are Nb
It can also be manufactured using a superconducting film or the like. That is, an Nb magnetic shielding film, an interlayer insulating film made of a Si oxide thin film, a resistor using a Mo thin film, an Nb film as an electrode,
Superconducting junction using an ultra-thin oxide thin film as a barrier layer, and N
A superconducting circuit was formed using the b film as a control line. Since the superconducting junction is of a tunnel type having a history in current-voltage characteristics, a resistor is connected in parallel with the superconducting junction so that the superconducting junction has no history.

[0059]

According to the present invention, it is possible to realize a superconducting signal generator which generates logic signal sequence data having a very high frequency utilizing the characteristics of the superconducting circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a signal generator according to the present invention.

FIG. 2 is a diagram illustrating a block configuration according to the first embodiment.

FIG. 3 is a diagram schematically showing a relationship between a low-speed signal train provided by an input circuit and a high-speed signal output obtained from an amplifier circuit in a superconducting temperature region according to the first embodiment; .

FIG. 4 is a block diagram illustrating an example of a conversion circuit and a clock generation circuit according to the first embodiment.

FIG. 5 is a block diagram illustrating an example of a conversion circuit and a shift register according to the first embodiment.

FIG. 6 is a schematic diagram of a configuration block of an example of a signal amplification circuit according to the first embodiment.

FIG. 7 is a diagram illustrating an equivalent circuit of an example of a signal amplification circuit according to the first embodiment.

FIG. 8 is a plan view showing an example when the signal amplification circuit according to the first embodiment is mounted on a substrate.

FIG. 9 is a diagram illustrating a block configuration according to a second embodiment.

FIG. 10 is a diagram illustrating a block configuration of a shift register that can be used for feedback according to the second embodiment.

FIG. 11 is a diagram schematically illustrating a relationship between a low-speed signal train provided by an input circuit and a high-speed signal output obtained from an amplifier circuit in a superconducting temperature region according to a second embodiment; .

FIG. 12 is a diagram illustrating a block configuration according to a third embodiment.

FIG. 13 is a block diagram illustrating an example of a conversion circuit and a ring oscillation circuit according to a third embodiment.

[Explanation of symbols]

1000: room temperature region, 1001: data storage circuit using semiconductor elements, 1002: logic signal string data setting-input circuit using semiconductor elements, 1003: signal output circuit using semiconductor elements, 2000: superconducting temperature area, 2001: superconducting signal string generating circuit , 201, 203 and 205: a conversion circuit from a level signal to a magnetic flux quantum, 202: a clock generation circuit, 136, 204: a confluence buffer, 2
06,212: shift register, 207: signal amplification circuit, 213: ring oscillation circuit, 12, 15, 20, 3
1, 132, 142: branch circuit (SP), 13, 14,
17, 18, 21, 22, 41, 42, 71.72, 1
33,134,135,141,143,144,14
7,150: Superconducting junction line (JTL), 146,14
8, 152: set / reset flip-flop, 1
0: superconducting magnetic flux quantum circuit, SFQ: magnetic flux quantum, 1: trigger signal source, 2: inductor, 3: ground, 5: superconducting junction, 6: bias power supply, 51, 52: control line for applying magnetic field, 61, 62: Superconducting quantum interference device (JI), 8
1, 82: termination resistance, 90: power supply, 91: voltage output line,
100: magnetic shielding film, 101: output pad, 102: power supply connection pad, 110: input inductor, 111, 11
5,131: superconductor, 112, 113, 122, 12
3, 124, 127 and 128: upper electrode, 116:
Connection points 124 and 129: lower electrode

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor ▲ Taka ▼ Kazuma Ki 2520 Akanuma, Hatoyama-cho, Hiki-gun, Saitama Prefecture Inside Hitachi, Ltd.Basic Research Laboratories Co., Ltd. Address: Hitachi, Ltd.Basic Research Laboratories (72) Inventor Tokukai 2520, Akanuma-cho, Hatoyama-cho, Hiki-gun, Saitama Pref. F-term in Hitachi, Ltd. Basic Research Laboratories (reference) 4M113 AA01 AA51 AC08 AD04 AD21 AD22 AD23 AD44 5J042 AA10

Claims (5)

[Claims] A shift register capable of holding data of a predetermined number of bits using a superconducting magnetic flux quantum arranged in a superconducting temperature region as a signal carrier, and a superconducting magnetic flux quantum for shifting data of the shift register as a signal carrier. A clock amplifying circuit, a signal amplifying circuit using a superconducting flux quantum for amplifying data sent from the shift register as a signal carrier, and a plurality of conversion circuits for converting a signal given from a circuit in a room temperature region into a superconducting flux quantum. The shift register introduces data to be held and a clock signal through the conversion circuit to hold the data, and the clock generation circuit introduces a trigger signal through the conversion circuit to generate a predetermined clock to superconducting magnetic flux. Transmitting the data generated by the quantum and held by the shift register. Superconducting signal generator. 2. A first shift register capable of holding data of a predetermined number of bits using a superconducting magnetic flux quantum disposed in a superconducting temperature region as a signal carrier, and for amplifying data transmitted from the first shift register. A signal amplification circuit using a superconducting magnetic flux quantum as a signal carrier, a second shift register using a superconducting magnetic flux quantum as a signal carrier, receiving data sent from the first shift register and returning an output to an input of the first shift register. A clock generation circuit using a superconducting flux quantum for shifting data of the first and second shift registers as a signal carrier, and a plurality of conversion circuits for converting a signal given from a circuit in a room temperature region into a superconducting flux quantum. And the first shift register introduces data to be held and a clock signal through the conversion circuit and holds the data. In addition, the clock generation circuit introduces a trigger signal through a conversion circuit to generate a predetermined clock with a superconducting magnetic flux quantum, and to shift data held in the first and second shift registers. Characteristic superconducting signal generator. 3. A first shift register capable of holding data of a predetermined number of bits using a superconducting magnetic flux quantum arranged in a superconducting temperature region as a signal carrier, and amplifying data transmitted by the first shift register. A signal amplification circuit using a superconducting magnetic flux quantum as a signal carrier, a second shift register using a superconducting magnetic flux quantum as a signal carrier, receiving data sent from the first shift register and returning an output to an input of the first shift register. A clock generation circuit using a superconducting flux quantum for shifting data of the first and second shift registers as a signal carrier, and a plurality of conversion circuits for converting a signal given from a circuit in a room temperature region into a superconducting flux quantum, A circuit mainly composed of a semiconductor element arranged in a room temperature region, wherein the data to be held by the first shift register; A clock signal for driving a shift register and a circuit for outputting a trigger signal for activating the clock generation circuit. The first shift register introduces data to be held and a clock signal through the conversion circuit. While holding the data, the clock generation circuit introduces a trigger signal through a conversion circuit to generate a predetermined clock with the superconducting magnetic flux quantum and shifts the data held in the first and second shift registers. A signal generator characterized in that: 4. The clock generation circuit holds the first and second shift registers with a clock generated by a ring oscillation circuit having a superconducting magnetic flux quantum activated by a trigger signal introduced via a conversion circuit as a signal carrier. 4. The signal generator according to claim 2, wherein the data is shifted. 5. The signal generator according to claim 1, wherein a clock frequency output from said clock generation circuit is adjustable by a value of a DC bias current for a superconducting element constituting said clock generation circuit.