JP2003281737A - Device and method of wobble demodulation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suggest a wobble demodulation device for stably performing FM demodulation even when deformation due to a defect of a medium exists in FM modulated wobble signals. <P>SOLUTION: The FM demodulation is stably performed without causing bit slip even when the wobble signal is deformed due to the defect of the medium, etc., by determining a synchronization state from the continuously detected number of edges of the wobble signals existing by every bit of digital information and operating the wobble demodulation device so as to lock an output position of a window for detecting the edges when the wobble signals are determined as a synchronized lock state. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention detects a wobble signal from an optical recording medium on which digital information such as control information peculiar to the optical recording medium is recorded by forming FM-modulated wobbles on a track. The present invention relates to a wobble demodulation device and method for demodulating digital information by performing FM demodulation.

[0002]

2. Description of the Related Art As a conventional example of an optical disc having wobbled tracks, the wobbles of which are FM-modulated, for example, a CD disclosed in Japanese Patent Laid-Open No. 2001-143404, "Wobble signal data demodulation circuit" is disclosed. -R (Comp
act Disk-Recordable). In the CD-R, the wobble signal is a signal that is FSK-modulated with a biphase code modulation signal, and the wobble frequency becomes 22.05 ± 1 kHz when the disk rotation is at a specified linear velocity.
When the frequency is 05 kHz, the data is "0", and when the frequency is 30.05 kHz, the data is "1". As a conventional example of the wobble demodulation circuit for FM demodulating the wobble signal as described above,
For example, JP-A-11-45519, "Frequency demodulation circuit and optical disk device having the same" can be mentioned.

FIG. 13 is a block diagram showing the configuration of a conventional example of a wobble demodulating device for demodulating the FM-modulated wobble signal as described above. In FIG. 13, reference numeral 1301 denotes an optical disk in which FM-modulated wobbles are formed on a track, and 1302 denotes an optical head that irradiates the optical disk 1301 with a light beam, detects the amount of reflected light from the optical disk 1301, and outputs an electric signal. . Reference numeral 1303 is a wobble signal detecting means for extracting an FM-modulated wobble signal from the electric signal. 1304 is a PLL (Phase) that generates a sampling clock from a wobble signal.
1305 is a wobble demodulation circuit that performs FM demodulation of the wobble signal.

The wobble demodulation circuit 1305 is for data "
Transition detection circuit 1 for detecting the transition between 0 "and" 1 "
306 and a data determination circuit 1307 that determines the data "0" and "1" by detecting the edge of the wobble signal based on the transition detection position. Turn detection circuit 13
Reference numeral 06 measures the cycle of the wobble signal by the sampling clock, and detects the data transition from the change in the measured value. The data determination circuit 1307 generates an edge detection window based on the transition detection position, determines data “0” and “1” based on the number of detected edges in the window, and outputs the result as an FM demodulation result.

In addition to the CD-R as described above, FIG.
As shown in, when the digital information data is "1", one wobble wave (cycle T) with respect to the FM modulation cycle T, "
When it is 0 ", the wobble is 0.5 wave (cycle T / 2) with respect to the FM modulation cycle T, and the wobble FM is such that the polarity is connected so as to be inverted with respect to the previous 1-bit waveform.
An optical recording medium has been proposed in which control information unique to the optical recording medium is recorded by modulation.

An FM as shown in FIG. 2 is used in the conventional extension technique.
When a wobble demodulator corresponding to the modulation is configured, for example, it is as follows. FIG. 14 is a timing chart when FM demodulation is performed by the conventional wobble demodulation circuit.

The wobble signal 1401 is 1 bit of digital information data, and 0.5 when the data is "0".
The wave and the data “1” are FM-modulated so as to have one wave, and 1402 is a wobble binary signal obtained by binarizing the wobble signal 1401.

The transition detecting circuit 1306 measures the edge interval of the wobble binarized signal 1402 with the sampling clock generated by the PLL circuit 1304, determines the position where the measurement value has changed as the transition of 1-bit data, and detects the transition. The signal 1405 is output.

The data judgment circuit 1307 generates a window 1403 for detecting the edge of the wobble binary signal 1402 from the value of the counter 1406 which operates on the basis of the transition detection signal 1405, and detects the edge when the edge is detected in the window. The pulse 1404 is output. Further, every time the counter 1406 counts a data 1-bit section, data “0” and “1” are determined from the output number and output position of the edge detection pulse 1404, and the FM demodulation result 14
07 is output.

[0010]

However, the conventional wobble demodulator determines the transition of 1 bit of data from the change of the edge interval or the cycle of the wobble signal, and is FM-modulated as shown in FIG. When the wobble signal is deformed with respect to the wobble signal due to a defect of the medium or the like, it is easy to erroneously detect the transition. As a result of erroneous detection of the transition point, there is a problem that the FM demodulation with respect to 1 bit of data is out of synchronization and the digital information cannot be reproduced accurately.

FIG. 15 is a timing chart showing the operation when the wobble signal is deformed. Reference numeral 1501 is a deformed wobble signal, 1502 is a wobble binary signal obtained from the wobble signal 1501, and 1505 is a transition detection signal by the transition detection circuit 1306. Due to the deformation of the wobble signal, the transition between the data “0” and the data “1” is erroneously detected, and the phase between the counter 1506 and the data bit is deviated. As a result, the number of bits of the FM demodulation result 1507 output from the data determination circuit 1307 increases, resulting in a bit slip error when reproducing digital information.

Therefore, in the present invention, in view of the above-mentioned current situation, even if the wobble signal is deformed, the wobble signal can be FM-stably stably without the bit synchronization being shifted.
It is an object to propose a wobble demodulation circuit that can demodulate.

[0013]

In order to solve the above-mentioned problems, the wobble demodulator of the present invention forms a wobble track in which the wobble period is modulated so as to include digital information, and the wobble is a digital information " 0 "
A demodulator for reproducing the digital information from an optical recording medium that has been FM-modulated so as to invert the phase at the cycle T corresponding to "1" of the digital information at cycle T / 2 corresponding to Wobble signal detecting means for extracting the wobble signal of the track from the optical recording medium, first window generating means for generating a first window for each modulation cycle of the FM modulation, and the wobble in the first window. A first edge detecting means for detecting an edge of the signal and outputting a first edge detection result; and a second window generating means for generating a second window after half a modulation cycle of the FM modulation from the position of the first window. Window generating means, second edge detecting means for detecting an edge of the wobble signal in the second window and outputting a second edge detection result, and the first edge detecting means. Demodulation means for demodulating "0" and "1" of the digital information based on the edge detection result and the second edge detection result, the output position of the first window by the first window generation means, and And a control means for controlling the output position of the second window by the second window generation means, wherein the control means includes the first
Is detected from the edge detection result and the second edge detection result, and when it is determined to be in the synchronous lock state, the output positions of the first window and the second window are locked. .

Further, in the wobble demodulation method of the present invention, a wobble track in which the wobble cycle is modulated so as to include digital information is formed, and the wobble is digital at a cycle T corresponding to "0" of the digital information. Corresponding to the information "1", the phase is inverted at the cycle T / 2 so that F
A demodulation method for reproducing the digital information from an M-modulated optical recording medium, comprising a wobble signal detecting step of extracting a wobble signal of the track from the optical recording medium, and a first step for each FM modulation period. A first window generating step of generating a window of
A first edge detection step of detecting an edge of the wobble signal in the window and outputting a first edge detection result; and a second edge after a half cycle of the modulation period of the FM modulation from the position of the first window. Second to create a window
Window generation step, a second edge detection step of detecting an edge of the wobble signal in the second window and outputting a second edge detection result, and the first edge detection step of
Demodulation step of demodulating "0" and "1" of the digital information on the basis of the edge detection result and the second edge detection result, and the first window generation step.
Output position of the window and a control step of controlling the output position of the second window in the second window generation step, the control step including the first edge detection result and the second edge. A synchronous state is determined from the detection result, and when the synchronous state is determined, the operation is performed so that the output positions of the first window and the second window are locked.

According to the wobble demodulation apparatus and method of the present invention, after the first edge detection result and the second edge detection result are determined to be in the synchronous lock state, the outputs of the first window and the second window are output. By operating so as to lock the position, even if the wobble signal is deformed, the relationship between the 1-bit data and the window output position does not shift, and stable FM demodulation of the wobble signal is performed. You can

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A wobble demodulation circuit according to the present invention will be described below with reference to FIGS. Figure 1
FIG. 1 is a block diagram showing a configuration of an embodiment of a wobble demodulation device according to the present invention. In FIG. 1, 101 is an optical disk in which FM-modulated wobbles are formed on a track as shown in FIG. 2, 102 is a light beam emitted to the optical disk 101, and the amount of reflected light from the optical disk 101 is detected to generate an electrical signal. It is an optical head that outputs. Reference numeral 103 is a wobble signal detecting means for extracting an FM-modulated wobble signal from the electric signal. A wobble demodulation circuit 104 performs FM demodulation of the wobble signal.

The wobble demodulation circuit 104 includes an FM cycle calculation circuit 105 for calculating an average value of FM cycles corresponding to 1 bit of data, a window generation circuit 106 for generating a window for detecting an edge of a wobble signal, and a window within the window. An edge detection circuit 107 that detects the edge of the wobble signal, a data determination circuit 108 that determines data “0” and “1” from the edge detection result and outputs an FM demodulation result, a synchronization state is confirmed from the edge detection result, and a synchronization state The sync detection circuit 109 controls the window output position in accordance with the above.

Next, the related operation of each component of the wobble demodulation circuit 104 will be described. FIG. 9 is a timing chart showing the operation of the wobble demodulation circuit 104. In FIG. 9, the wobble signal 901 is FM-modulated so that the original data 1 bit has 0.5 wave when the data is “0” and 1 wave when the data is “1”. It is a wobble binarization signal obtained by binarizing the wobble signal 901.

The window generation circuit 106 has a timer counter 907 which operates at the FM cycle average value obtained by the FM cycle calculation circuit 105. Based on the timer counter 907 and the FM cycle average value, the first window is output at the transition of 1-bit data, and the second window is output at the position where the value of the timer counter 907 is half the FM cycle average value. The timer counter 907 is reset when it counts up to the FM cycle average value or when an edge is detected in the first window, and is also reset by a control signal from the synchronization detection circuit 109.

FIG. 3 is a block diagram showing the configuration of the window generation circuit 106. Window generation circuit 106
Is a timer counter 301 that operates with a sampling clock of a predetermined frequency, a match detection circuit 302, an OR circuit 303, a first section detection circuit 304, and a second section detection circuit 3.
It is composed of 05 and.

The coincidence detection circuit 302 outputs a coincidence pulse signal when the value of the timer counter 301 coincides with the FM cycle average value. The OR circuit 303 receives the coincidence pulse signal, the first edge detection pulse 905 output from the edge detection circuit 107, and the control signal from the synchronization detection circuit 109, and the output signal is the timer counter 301.
Input to the reset terminal of. As a result, the timer counter 301 is reset when it counts up to the FM cycle average value or when an edge is detected in the first window, and is also reset by the control signal from the synchronization detection circuit 109. To work.
The first section detection circuit 304 has a section in which the value of the timer counter 301 is 0 to (FM cycle average value × 1/8) and (FM
The first window is output in the section of (period average value × 7/8) to (FM period average value). Second section detection circuit 3
05 outputs the second window in the section where the value of the timer counter 301 is (FM cycle average value × 3/8) to (FM cycle average value × 5/8).

Returning to FIG. 9, the edge detection circuit 107
When an edge is detected in the first window 903, the first edge detection pulse 905 is output, and the second window 9
When an edge is detected in 04, the second edge detection pulse 906 is output.

FIG. 4 is a block diagram showing the configuration of the edge detection circuit 107. The edge detection circuit 107 includes two-stage D flip-flop circuits 401 and 402 that operate with a sampling clock of a predetermined frequency, an exclusive OR circuit 403, and two AND circuits 404 and 405.
It consists of and.

The wobble binary signal 902 is input to the input terminal D of the D flip-flop circuit 401, and its output terminal Q is input to the input terminal D of the other D flip-flop circuit 402. The output terminals Q of the two D flip-flop circuits are input to the exclusive OR circuit 403, and the edge pulse of the wobble binary signal 902 is obtained from the outputs. The edge pulse and the first window are input to the AND circuit 404, and the first edge detection pulse 905 is obtained from the output thereof. Similarly, AND circuit 4
The edge pulse and the second window are input to 05, and the second edge detection pulse 906 is obtained from the output.

Returning to FIG. 9, the data judgment circuit 108
Data "1" when the second edge detection pulse is output for each data 1-bit section, data when it is not output "
It is determined to be 0 ”and the FM demodulation result 908 is output.

FIG. 5 is a block diagram showing the structure of the data judgment circuit 108. The data determination circuit 108 includes a set / reset flip-flop circuit 501, a D flip-flop circuit 502 that operates with a sampling clock of a predetermined frequency, and a decode circuit 503. The decoding circuit 503 outputs a reset pulse when the value of the timer counter 907 is 0. At the set input terminal S of the set / reset flip-flop 501,
The second edge detection pulse 906 is input, and the reset pulse is input to the reset input terminal R. The signal output from the output terminal Q is the D flip-flop circuit 50.
2 is input to the input terminal D of the D flip-flop circuit 5
A reset pulse is input to the enable terminal EN of 02. Then, the FM demodulation result 908 is obtained from the output terminal Q of the D flip-flop circuit 502.

The FM cycle calculation circuit 105 measures the interval between the first edge detection pulses and calculates the average value of the FM cycle based on the value obtained by integrating the measured values N times. FIG. 6 is a block diagram showing the configuration of the FM cycle calculation circuit 105. The FM cycle calculation circuit 105 includes a counter 601 that operates with a sampling clock having a predetermined frequency, and an integration circuit 602.

The counter 601 uses the first edge detection pulse 905 as a reset input signal and measures the interval. The measured value is sent to the integrating circuit 602. In the integration circuit 602, the first edge detection pulse is input as the operation enable signal EN, and when the first edge detection pulse is output, 1 / N of the integrated value is output as the FM cycle average value. Then, from the integrated value, output F
The M period average value is subtracted, and then the value measured by the counter 601 is added to the integrated value. In addition, the integrating circuit 60
An FM cycle correction signal, which is a control signal from the synchronization detection circuit 109, is input to 2 and the FM cycle deviation is corrected by correcting the integrated value by half or double according to the FM cycle correction signal.

By the above operation, the FM cycle average value is calculated for each bit of data, and if the rotation speed of the optical disc 101 changes, the output position of each window by the window generating means 106 also changes accordingly.

Returning to FIG. 9, the synchronization detection circuit 109 determines the synchronization state from the detection states of the first edge detection pulse 905 and the second edge detection pulse 906, and resets the timer counter 907 according to the synchronization state. By doing so, the output positions of the first window and the second window are controlled.

FIG. 7 is a block diagram showing the structure of the synchronization detection circuit 109. The synchronization detection circuit 109 includes a first edge detection counter 701 that counts the number of consecutive detections of the first edge detection pulse, and a second edge detection counter 702 that counts the number of consecutive detections of the second edge detection pulses.
A first edge undetected counter 703 that counts the number of consecutive undetected first edge detection pulses, and a second edge undetected counter 704 that counts the number of consecutive undetected second edge detection pulses, It is composed of a synchronization determination circuit 705. The synchronization determination circuit 705 determines the synchronization state based on the four counter values, and the timer counter 90
The control signal 7 is output.

FIG. 8 is a diagram showing a flow of detection of the synchronization state by the synchronization determination circuit 705. When the wobble demodulation operation is started, the synchronization determination circuit 705 first enters the synchronization non-detection state 801. In the synchronization non-detection state 801, the first window 903 is controlled to be always output, and the second window 904 is controlled not to be output. Therefore, when the edge of the wobble binary signal is detected once and the value of the first edge detection counter 701 becomes 1, a control signal for resetting the timer counter 907 is output, and the synchronization state 910 of the synchronization determination circuit 705 is output. Transits to the synchronization confirmation state 802.

In the synchronization confirmation state 802, the synchronization lock is detected based on the number of consecutive detections of the first edge detection pulse. The first edge detection pulse is continuously output K times, and when the value of the first edge detection counter 701 becomes K, it is determined that the synchronization is locked, and the synchronization state 910 transits to the synchronization lock state 804.

In the synchronization confirmation state 802, the phase shift is detected from the number of consecutive detections of the first edge detection pulse and the number of consecutive detections of the second edge detection pulse. Figure 10
FIG. 7 is a timing chart showing an operation of phase shift detection.

The phase shift occurs when the edge first detected in the synchronization undetected state 801 is not the transition edge of 1-bit data. At this time, the timer counter 1007 operates with a shift of half the FM cycle with respect to the transition of 1 bit of data. For this reason,
The second window 1004 is output at the transition of 1-bit data, and the second edge detection pulse 10
06 will be output continuously. From this,
The synchronization determination circuit 705 shifts the phase when the second edge detection pulse is continuously detected L times (where L> K) and the number of consecutive detections of the first edge detection pulse has not reached K times. To determine. That is, the value of the second edge detection counter 702 is L, and the first edge detection counter 701 is
If the value of is less than K, it is determined that there is a phase shift, and the shift detection pulse 10 is set as the reset signal of the timer counter 1007.
08 is output. At this time, the timer counter 1007
Is reset by the shift detection pulse 1008, and the shift is corrected. Further, the synchronization state 1009 transits to the synchronization deviation correction state 803.

Further, in the synchronization confirmation state 802, period deviation detection is also performed. FIG. 16 is a timing chart showing the operation for detecting the period shift. 16A shows an FM cycle calculation circuit 105.
In the case where the FM cycle average value calculated in 1 is twice, B is 1/2. In the case of A, both the first window 1603 and the second window 1604 are output at the transition of 1-bit data, so that both the first edge detection pulse 1605 and the second edge detection pulse 1606 are continuous. And output. From this, the synchronization determination circuit 705 detects the first edge detection pulse F times or more (where F ≦ K) continuously, and the second edge detection pulse F times or more consecutively. In this case, it is determined that there is a double cycle shift. That is,
2 if the value of the first edge detection counter 701 is F or more and the value of the second edge detection counter 702 is F or more
It is determined that there is a double cycle shift, and the double cycle shift detection pulse 1608 is output to the FM cycle calculation circuit 105. The FM cycle calculation circuit 105 that has received the double cycle shift detection pulse 1608 as the FM cycle correction signal corrects the double cycle shift by halving the integrated value. Further, the synchronization state transits to the synchronization deviation correction state 803.

In the case of FIG. 16B, the second window 1610 is always output at a position where no edge exists. From this, the synchronization determination circuit 705 determines that the second
If the number of consecutive undetected edges of the edge detection pulse is G times and the number of consecutive detections of the first edge detection pulse has not reached K times, it is determined as a half cycle shift. That is, if the value of the second edge non-detection counter 704 is G and the value of the first edge detection counter 701 is less than K, it is determined that there is a half cycle shift, and the FM cycle calculation circuit 105 is shifted by a half cycle. The detection pulse 1614 is output. The FM cycle calculation circuit 105 which receives the half cycle deviation detection pulse 1614 as the FM cycle correction signal corrects the half cycle deviation by doubling the integrated value. In addition, the synchronization state is the synchronization deviation correction state 8
Transition to 03.

In the synchronization deviation correction state 803, similarly to the synchronization confirmation state 802, the synchronization lock is detected after the deviation of the timer counter is corrected, and when the synchronization lock is detected, the state shifts to the synchronization lock state 804.

Further, in the synchronization confirmation state 802 and the synchronization deviation correction state 803, the synchronization unlock detection is performed from the number of consecutive undetections of the first edge detection pulse and the second edge detection pulse. FIG. 11 is a timing chart showing the operation of the synchronization unlock detection.

The synchronization unlock state is the synchronization non-detection state 801.
In the case where the edge detected first in is a false detection, or when the tracking jumps to an adjacent track, etc. At this time, the first window 11
03 and the second window 1104 are output at positions where edges do not exist. From this, when neither the first edge detection pulse nor the second edge detection pulse is continuously detected M times or more, it is determined that the synchronization is unlocked. That is, the first edge undetected counter 70
The value of 3 is M or more, and the second edge undetected counter 70
If the value of 4 is M or more, it is determined that the synchronization is unlocked, and the unlock detection signal 1108 is output. At this time, the synchronization state 1109 transits to the synchronization non-detection state 801, and thereafter, the same detection operation is performed.

In the synchronization lock state 804, the same synchronization deviation detection and synchronization unlock detection as in the synchronization confirmation state 802 are performed. However, once the synchronous lock is detected, the thresholds of the synchronous deviation detection and the synchronous unlock detection are set to the synchronous confirmation state 802 in order to improve the stability against the deformation of the wobble signal.
And a sync shift correction state 803. The condition for detecting the synchronization deviation is that the value of the second edge detection counter 702 is P (where P >> L) and the first edge detection counter 7 is
The value of 01 is less than K. The condition of the synchronous unlock detection is that the value of the first edge undetected counter 703 is Q.
(However, Q >> M) or more, and the value of the second edge undetected counter 704 becomes Q or more.

FIG. 12 is a timing chart showing the operation of the wobble demodulation circuit 104 when the wobble signal is deformed and is lost over a long section.

In the synchronization confirmation state 802 shown in FIG. 12B, the synchronization unlock is detected during the missing section, and the synchronization is detected again from the synchronization non-detection state 801. In FIG. 12, since the edge detected first is not the transition of the FM cycle, the synchronization shift is detected. After that, the shift is corrected, the synchronization lock is detected, and the state shifts to the synchronization lock state 804, and the FM demodulation can be accurately performed. However, during the resynchronization as described above, a few bits of the FM demodulation result are output by the correction processing of the timer counter, which causes a bit slip error in the reproduction of digital information.

FIG. 12A shows that the synchronization lock state 804 has already been reached.
Similarly, the operation of the wobble demodulation circuit 104 when the wobble reproduction signal is lost over a long period is shown. In the synchronization lock state 804, the synchronization unlock is not detected, and an accurate FM demodulation result can be obtained from the time when the wobble signal is restored. Also,
Since the re-synchronization processing is not performed, the FM demodulation result is not output extra, and the bit slip error can be prevented in reproducing the digital information.

Further, in the conventional wobble demodulation device, even if the wobble signal is deformed by mistakenly detecting the transition of one bit of data, the synchronization shift is detected based on the number of consecutive edge detections. Stable without FM
Can be demodulated.

In the above embodiment, a value obtained by measuring the FM cycle of wobble corresponding to 1 bit of digital information with a sampling clock having a fixed frequency is used, but the present invention is not limited to this.

In the above embodiment, when the digital information data is "1", one wobble wave (cycle T) is generated for the FM modulation cycle T, and when the digital information data is "0", it is compared for the FM modulation cycle T. As a result, wobble FM modulation was used in which the wobble is 0.5 waves (cycle T / 2) and the polarity is connected so as to be inverted with respect to the previous 1-bit waveform, but the present invention is not limited to this. , The same effect is exhibited even when the wobble cycle for the data “1” and “0” is opposite.

[0048]

As described above, according to the wobble demodulator of the present invention, the synchronization state is determined from the number of consecutive detections of wobble edges for each bit of digital information, and when it is determined to be the synchronization lock state, the window state is determined. By operating so as to lock the output position, even if the wobble signal is deformed due to a medium defect or the like, it is possible to stably reproduce digital information without causing bit slip.

Further, by detecting the synchronization deviation, the window output position is corrected by the deviation so that the resynchronization can be accurately performed and the digital information can be reproduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a wobble demodulator according to the present invention.

FIG. 2 is a diagram showing a wobble wave number for one bit of digital information.

FIG. 3 is a block diagram showing a configuration of a window generation circuit.

FIG. 4 is a block diagram showing a configuration of an edge detection circuit.

FIG. 5 is a block diagram showing a configuration of a data determination circuit.

FIG. 6 is a block diagram showing the configuration of an FM cycle calculation circuit.

FIG. 7 is a block diagram showing the configuration of a synchronization detection circuit.

FIG. 8 is a diagram showing a flow of synchronization detection of the wobble demodulator according to the present invention.

FIG. 9 is a timing diagram showing the operation of the wobble demodulator according to the present invention.

FIG. 10 is a timing diagram showing the operation of the wobble demodulator according to the present invention when the wobble signal is deformed.

FIG. 11 is a timing diagram showing an operation related to phase shift detection of the wobble demodulator according to the present invention.

FIG. 12 is a timing diagram showing an operation relating to synchronization unlock detection of the wobble demodulator according to the present invention.

FIG. 13 is a block diagram showing the configuration of a conventional wobble demodulator.

FIG. 14 is a timing chart showing the operation of a conventional wobble demodulator.

FIG. 15 is a timing chart showing the operation of the conventional wobble demodulator when the wobble signal is deformed.

FIG. 16 is a timing chart showing an operation related to detection of a period shift of the wobble demodulator according to the present invention.

[Explanation of symbols]

101, 1301 Optical disks 102, 1302 Optical heads 103, 1303 Wobble detection means 104, 1305 Wobble demodulation circuit 105 FM period calculation circuit 106 Window generation circuit 107 Edge detection circuit 108, 1307 Data judgment circuit 109 Sync detection circuit 301 Timer counter 302 Match detection Circuit 303 OR circuit 304 First section detection circuit 305 Second section detection circuit 401, 402, 502 D flip-flop circuit 403 Exclusive OR circuit 404, 405 AND circuit 501 Set / reset flip-flop circuit 503 Decoding circuit 601 Measurement counter 602 Integration Circuit 701 First edge detection counter 702 Second edge detection counter 703 First edge undetected counter 704 Second edge undetected counter 705 Period judging circuit 801 shift synchronization undetected 802 synchronization confirmation state 803 synchronization correction condition 804 sync lock state 901,1001,1101,1401,1501,1
601 Wobble signals 902, 1002, 1102, 1201, 1207, 1
402, 1502, 1602 Wobble binary signals 903, 1003, 1103, 1202, 1208, 1
603, 1609 First window 904, 1004, 1104, 1203, 1209, 1
604, 1610 Second window 905, 1005, 1105, 1204, 1210, 1
605, 1611 First edge detection pulses 906, 1006, 1106, 1205, 1211, 1
606, 1612 Second edge detection pulse 907, 1007, 1107, 1607, 1613 Timer counter value 908, 1407, 1507 FM demodulation result 909, 1009, 1109, 1206, 1212 Sync state 1008, 1213 Deviation detection pulse 1108, 1214 Ann Lock detection signal 1304 PLL circuit 1306 Transition detection circuit 1403, 1503 Window 1404, 1504 Edge detection pulse 1405, 1505 Transition detection signal 1406, 1506 Counter 1608 Double cycle deviation detection 1614 Half cycle deviation detection

Continued front page    (72) Inventor Makoto Usui             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 5D044 BC02 CC04 FG09 GL43 GM16                 5D090 AA01 CC04 CC16 EE15 GG03                       HH01 LL09

Claims (12)

[Claims] 1. A wobble track in which a wobble period is modulated to include digital information is formed, and the wobble has a period T corresponding to "0" of digital information,
A demodulator for reproducing the digital information from an optical recording medium that is FM-modulated so as to invert the phase at a cycle T / 2 corresponding to "1" of the digital information. Wobble signal detection means for extracting a wobble signal, first window generation means for generating a first window for each modulation period of the FM modulation, and first for detecting an edge of the wobble signal in the first window First edge detecting means for outputting the edge detection result, second window generating means for generating a second window after a half period of the modulation period of the FM modulation from the position of the first window, Second edge detection means for detecting an edge of the wobble signal in the second window and outputting a second edge detection result; and the first edge detection result. Demodulation means for demodulating "0" and "1" of the digital information based on the edge detection result of No. 2, the output position of the first window by the first window generation means, and the second window generation means Control means for controlling the output position of the second window by the control means, wherein the control means controls the first edge detection result and the second edge detection result.
The wobble demodulator that operates to lock the output positions of the first window and the second window when the synchronization state is determined from the edge detection result of 1. and the synchronization lock state is determined. 2. The wobble demodulator according to claim 1, wherein the control means determines that the state is the synchronous lock state when the number of consecutive outputs of the first edge detection result reaches a predetermined value. 3. The control means determines a phase shift state when the number of consecutive outputs of the second edge detection result reaches a predetermined value and the number of consecutive outputs of the first edge detection result is less than a predetermined value. The wobble demodulator according to claim 1, wherein the output positions of the first window and the second window are respectively corrected by a half cycle of the modulation cycle of the FM modulation. 4. The synchronous unlocking state when both the number of consecutive non-outputs of the first edge detection result and the number of consecutive non-outputs of the second edge detection result are equal to or more than a predetermined value. It is determined that the first window and the second window
2. The wobble demodulator according to claim 1, wherein the output position of the window is corrected based on the next edge position of the wobble signal. 5. The control means determines a double cycle state when both the number of consecutive outputs of the first edge detection result and the number of consecutive outputs of the second edge detection result are equal to or more than a predetermined value. The wobble demodulator according to claim 1, wherein the output cycle of the first window and the second window is corrected to a half cycle in the double cycle state. 6. The control means is in a half-cycle state when the number of consecutive non-outputs of the second edge detection result is a predetermined value and the number of consecutive output of the first edge detection result is a predetermined value or less. 2. The wobble demodulation device according to claim 1, wherein the wobble demodulation device makes a determination and corrects a cycle of outputting the first window and the second window to a double cycle in a half cycle state. 7. A wobble track having a wobble period modulated to contain digital information is formed, and the wobble has a period T corresponding to "0" of the digital information,
A demodulation method for reproducing the digital information from an optical recording medium that is FM-modulated so as to invert the phase at a cycle T / 2 corresponding to "1" of the digital information. A wobble signal detecting step of extracting a wobble signal, a first window generating step of generating a first window for each modulation period of the FM modulation, and a first window detecting step of detecting an edge of the wobble signal in the first window. A first edge detection step of outputting the edge detection result of the second window generation step, and a second window generation step of generating a second window after a half cycle of the modulation cycle of the FM modulation from the position of the first window; A second edge detection step of detecting an edge of the wobble signal within a second window and outputting a second edge detection result; A demodulation step of demodulating "0" and "1" of the digital information based on the edge detection result and the second edge detection result, and the output position of the first window by the first window generation step, And a control step of controlling an output position of the second window by the second window generation step, the control step determining a synchronization state from the first edge detection result and the second edge detection result. A wobble demodulation method that operates so as to lock the output positions of the first window and the second window when it is determined to be in the synchronous lock state. 8. The wobble demodulation method according to claim 7, wherein the control step determines that a synchronous lock state is established when the number of consecutive outputs of the first edge detection result reaches a predetermined value. 9. The control step determines that a phase shift state exists when the number of consecutive outputs of the second edge detection result reaches a predetermined value and the number of consecutive outputs of the first edge detection result is less than a predetermined value. 8. The wobble demodulation method according to claim 7, wherein the output positions of the first window and the second window are respectively corrected by a half cycle of the modulation cycle of the FM modulation. 10. The synchronous unlock state when both the number of consecutive non-outputs of the first edge detection result and the number of consecutive non-outputs of the second edge detection result are equal to or more than a predetermined value in the control step. 8. The wobble demodulation method according to claim 7, wherein the output positions of the first window and the second window are corrected based on the next edge position of the wobble signal. 11. The control step determines a double cycle state when both the number of consecutive outputs of the first edge detection result and the number of consecutive outputs of the second edge detection result are equal to or more than a predetermined value. 8. The wobble demodulation method according to claim 7, wherein the cycle of outputting the first window and the second window is corrected to a half cycle in the double cycle state. 12. A half-cycle state is set when the number of consecutive non-outputs of the second edge detection result is a predetermined value and the number of consecutive output of the first edge detection result is a predetermined value or less in the control step. The first window and the second window
8. The wobble demodulation method according to claim 7, wherein the period for outputting the window is corrected to a double period in the half-cycle state.