JP2003279629A - Circuit for generating pulse, semiconductor testing device using the same, method of testing semiconductor, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that a dispersion is generated in the propagation delay time of a delay circuit by a factor of a temperature change accompanying the fluctuation of electric power consumption, so as to make the pulse generation time difficult to be controlled precisely, in a delay circuit using a CMOS-IC. <P>SOLUTION: This pulse generation circuit of the present invention is provided with a dummy pulse generating means for generating a dummy pulse in a period in which a pulse is not generated originally, and by keeping the electric power consumption constant in the pulse generating circuit, without expanding a dummy delay circuit (electric power consumption circuit) of a large scale, the electric power consumption per unit time is controlled to be constant. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generation circuit, a semiconductor test apparatus using the pulse generation circuit, a semiconductor test method, and a semiconductor device manufacturing method.

[0002]

2. Description of the Related Art Generally, in a functional test of an IC to be tested, various test signals are applied to the IC under test from an IC test device within each basic (test) cycle, and the test under test I is performed.
Each of the various response signals from C is taken into the IC test apparatus, and the quality of each is judged at the judgment timing for each, so that whether the function as the IC is normal or not is tested. Has become.

By the way, in recent years, with the increase in operating speed of ICs in general, an LSI test apparatus for testing those ICs has
The accuracy of the generation time (timing) of the test waveform affects the test performance. In particular, the timing edge generated by the pulse generation circuit provided in the LSI test apparatus requires extremely high time accuracy.

Here, FIG. 16 shows an outline of a conventional pulse generating circuit.

The pulse generation circuit 1 mainly includes a data operation circuit 5, a pulse generation circuit 6 and a pulse delay circuit 7. The data calculation circuit 5 calculates the delay data 9 that determines the pulse generation timing based on the test pattern data 3 sent in synchronization with the operation clock 4-1 from the pattern generation circuit (not shown), and generates the pulse. It outputs to the circuit 6 and the pulse delay circuit 7. The pulse generation circuit 6 and the pulse delay circuit 7 are based on the delay data 9 (TC, D, A) having different delay resolutions (delay units), respectively.
Generates a pulse at the specified timing.

Next, the control operation of the pulse generation circuit 6 will be described with reference to FIG. FIG. 20 shows the operation timing of each circuit unit shown in FIG. As an operation example using FIG. 20, the master clock 2 is set to 500 MHz (2 ns cycle), and the operation clock 4-1 is set to 250 MHz (4 ns).
The pulse generation circuit 6 will be described below.

First, the pulse generation circuit 6 can generate a pulse based on the delay data (TC) 9-1 sent from the data operation circuit 5. Here, since the delay data 9-1 (TC) is sent in synchronization with the operation clock 4-1, the pulse generation (delay) resolution is the operation clock cycle (4 ns cycle in this example).

Further, since the pulse generation circuit 6 uses the master clock 2 which is a half cycle of the operation clock, the half cycle of the operation clock (= master clock cycle: 2 ns in this example) is used as the delay resolution. The pulse can be delayed. In FIG. 17, the delay data (D) 9
-2 is latched by FFd11 in synchronization with the master clock, and when delay data (D) 9-2 is "0", FFcm
The output pulse of p10 is output to the FF1 (14) side, and when it is "1", it is output to the FF2 (15) side. The FF1 (14) and the FF2 (15) latch the pulses respectively sent thereto, and the FF2 (15) further FF2 '(1
Output pulse to 6). That is, the delay data (D)
If 9-2 is "1", the output pulse passes through one more stage of the flip-flop operating at the master clock 2 as compared with the delay path of "0", so that the pulse is set at 1 of the master clock.
The pulse can be output after delaying the pulse by the time corresponding to the period.

Further, in the pulse generation circuit 6 shown in FIG. 17, the outputs of the FF1 (14) and FF2 '(16) generated by the operation clock 4-1 are used as the OR gate 17 of the next stage.
Via FFor18, and AND processing is performed with the output of FFor18 and the inverted value of the FFs output latched once at the negative edge of master clock 2 (As19).
By doing so, the pulse width is shaped and output.

Next, the pulse delay circuit 7 can delay the pulse generated by the pulse generation circuit based on the delay data (A) 9-3 with a delay resolution of half the operation clock period or less. .

An example of the operation of the pulse delay circuit 7 will be described with reference to FIG. The pulse delay circuit 7 mainly includes a delay circuit 30, a FIFO 31 for reading the asynchronous delay data (A) 9-3 in synchronization with an output pulse, and
The read FF 32 is used.

First, the delay data (A) 9-3 is written and stored in the FIFO 31 in synchronization with the operation clock 4-1. The written delay data (A) 9-3 is read from the FIFO 31 and input to the delay circuit 30 by using the falling timing of the output pulse 7-1 immediately before which has passed through the pulse delay circuit 7 as a trigger. .

As shown in FIG. 19, the delay circuit 30 is composed of a delay element group 34 composed of inverters and the like, and a selection circuit 33 for selecting a pulse path. Is selected and the delay amount of the pulse is determined.

In the example shown in FIG. 19, when the delay data is "1", the input internal pulse 6-1 passes through the path having the delay element group 34 (delay amount Ans) on the long delay time side, When it is 0 ", it passes through the path having the short delay time without the delay element group 34.

As described above, the pulse generation circuit 1 can generate a pulse at a desired timing by combining the digital delay time in the pulse generation circuit 6 and the analog delay time in the pulse delay circuit 7.

Therefore, the pulse generation circuit 1 includes a waveform generator such as a pulse generator and an LSI test device (LSI).
It is often used for testers). Particularly in the LSI test apparatus, the test waveform generation accuracy influences the test performance, and thus the pulse generation accuracy of the pulse generation circuit 1 is required to be extremely high.

[0017]

However, in the conventional pulse generation circuit 1 which generates a pulse at a desired timing by combining the delay times set in the pulse generation circuit 6 and the pulse delay circuit 7, the output pulse When the generation period is changed, the power consumption of the circuit fluctuates, so the pulse generation timing varies,
There is a problem that the accuracy of pulse generation deteriorates.

A more detailed description is as follows.

In an LSI tester or the like, the pulse generation period needs to be changed according to the test pattern, so the pulse generation period is not always constant. On the other hand, the power consumption of the pulse generation circuit 1 is proportional to the pulse generation cycle (pulse generation interval per unit time) and the delay time given to the pulse (delay gate passage time in the delay circuit). The delay time given to the pulse also differs depending on the test pattern. Therefore, in the LSI test apparatus, when inspecting different types of LSIs or when the same type of L
Even with SI, if the inspection conditions are changed, the power consumption of the pulse generation circuit 1 will not be constant.

If the power consumption of the pulse generation circuit 1 is not constant in this way, (1) the change in the voltage due to the change in the power consumption increases the jitter of the output pulse, (2)
If the delay circuit in the pulse generation circuit is mainly composed of a CMOS gate array, the temperature (junction temperature) in the circuit changes when the pulse generation cycle changes and the power consumption changes, and the propagation delay time of the delay circuit varies. Occurs.
As a result, there is a problem in that the pulse generation timing varies and the pulse generation accuracy deteriorates. In particular, a CMOS circuit is likely to have an error in the propagation delay time of the circuit due to the temperature change and the voltage change due to the change in power consumption due to its characteristics.

Therefore, in the pulse generation circuit, a technique for making the power consumption constant during operation is indispensable in order to suppress the voltage variation due to the power consumption variation and the propagation delay time variation of the delay circuit.

With respect to this technique, conventionally, as shown in FIG. 21, in addition to the delay circuit (first delay circuit) of the pulse generating circuit, the power consumption is kept constant in order to keep the power consumption during operation of the pulse generating circuit constant. A circuit (second delay circuit) was separately provided.

For example, in Japanese Unexamined Patent Publication No. 8-330920, a pulse for current compensation is generated in a period in which no pulse is generated, and a dummy power consumption circuit prepared separately is driven by the pulse to generate a pulse generator circuit. A method of keeping power consumption constant is disclosed.

Further, in Japanese Patent Laid-Open No. 2000-275309, fluctuations in power consumption caused by variations in pulse delay time are interpolated by a dummy delay circuit for the difference in delay time of each pulse, and the delay of all pulses is delayed. A method of reducing by keeping the time constant is disclosed.

[0025]

[Patent Document 1] Japanese Unexamined Patent Publication No. 8-330920

[0026]

However, in these methods, in order to reduce fluctuations in power consumption and variations in delay time given to pulses, a dummy delay for interpolating power or delay time is used. It was necessary to prepare a circuit (power consumption circuit) separately. Considering that a delay circuit is required for each output pin, in order to match the power consumption of the entire circuit, a dummy delay circuit with the same circuit scale as the original delay circuit should be provided for each pin. There has been a problem that the circuit scale of the pulse generation circuit is increased because it must be newly prepared.

Therefore, in the present invention, the power consumption in the pulse generation circuit is kept constant and the accuracy of the pulse generation time is improved without adding a large-scale dummy delay circuit (power consumption circuit) as in the conventional example. An object is to provide a pulse generation circuit.

It is another object of the present invention to provide an LSI test apparatus which can apply a test waveform whose timing (time) is controlled with high accuracy.

Further, by using a test waveform whose timing (time) is controlled with high accuracy, a semiconductor device (L
It is an object to provide a semiconductor inspection method and a manufacturing method for inspecting (SI).

[0030]

The outline of the typical inventions among the inventions disclosed in the present application will be briefly described as follows. The pulse generation circuit and the pulse generator using the same are provided with a dummy pulse control means capable of detecting a period in which a real pulse does not occur and controlling generation of a dummy pulse (hereinafter, referred to as a dummy pulse). The pulse generation cycle (pulse generation interval per unit time) is adjusted using a dummy pulse.

Further, in the pulse generation circuit, the generation time of the pulse output from the pulse generation circuit is calculated based on the pattern data having information for determining whether or not the pulse is generated in the pulse generation circuit. Data calculation circuit, a dummy pulse control circuit for detecting a period in which a pulse is not generated in the pattern data, and generating a dummy pulse in a period in which the pulse is not generated, a pulse generated based on the pattern data, and the dummy pulse And a logic gate circuit between the pulse generation circuit and the output pin for removing the dummy pulse generated by the pulse generation circuit.

Further, a master clock, a pattern generation circuit for generating pattern data including information on a test waveform, a timing generation circuit for receiving the master clock and the pattern data and generating a test waveform, and the test waveform A semiconductor test device having a driver applied to a semiconductor device under test (LSI), a comparison circuit for judging a response waveform from the semiconductor device under test, and a fail memory for storing the judgment result, the timing generation The circuit has a pulse generation circuit that generates a pulse that determines the rising and falling timings of the test waveform, and a waveform formatter that generates the test waveform based on the pulse, and the pulse generation circuit further includes the pattern data. Pulse generation circuit detects a period in which no pulse is generated, and the pulse is generated In which it is provided with a dummy pulse control circuit for generating a dummy pulse period not.

Further, for each predetermined cycle, a cycle in which no pulse is generated is detected from the pattern data having information for determining whether or not to generate a pulse in the pulse generation circuit, and the pulse is generated. It is a semiconductor inspection method for inspecting a semiconductor device by using a test waveform formed under stable power consumption by generating a dummy pulse in a cycle not performed.

Further, a step of forming a circuit element on the semiconductor wafer, a step of forming a wiring for electrically connecting the electrode of the circuit element and an external connection terminal on the semiconductor wafer, and a protective film on the semiconductor wafer. What is claimed is: 1. A method of manufacturing a semiconductor device, comprising: forming a semiconductor wafer; dicing the semiconductor wafer; and inspecting a semiconductor device in a state of the semiconductor wafer or in a state of being diced and individualized. , Detects a cycle in which no pulse is generated from pattern data having information for determining whether or not to generate a pulse in the pulse generation circuit for each predetermined cycle, and dummy the cycle in which the pulse is not generated. By generating a pulse, a semiconductor device that inspects a semiconductor device using a test waveform formed under stable power consumption It is a method of manufacture.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments of the invention, components having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 shows a circuit configuration of an embodiment using the present invention.

The pulse generation circuit 101 of this embodiment includes a master clock 2, a clock division / multiplication circuit 4 capable of dividing or multiplying the master clock 2, and a test pattern from a pattern generation circuit (not shown). Generation time of output pulse based on data 3 (delay data 9 (TC, D,
A)) The data calculation circuit 5 for calculating the pattern and the test pattern data 3 from the pattern generation circuit detects the period (time, period) in which the pulse generation circuit 101 does not generate a pulse, and controls the generation of the dummy pulse. And a pulse generation circuit 102 for generating a pulse including a dummy pulse at a timing synchronized with the master clock based on the delay data (D) 103-2.
And a pulse delay circuit 104 capable of delaying an output pulse based on the delay data (A) 103-3 with a minute delay time of a master clock cycle or less, and the pulse delay circuit 1
AND for masking dummy pulse from 04 output
The gate 105 is used.

In the first embodiment, the number of pulses generated per unit time in the pulse generation circuit 102 can be made constant by adopting the above-mentioned configuration, and thus the power consumption of the entire pulse generation circuit can be reduced. Can be constant.

A more specific description will be given below.

Here, as an operation example, the master clock 2
Is set to 500 MHz (2 ns cycle) and operation clock 4-
The first embodiment will be described with reference to the pulse generating circuit 101 in the case of using 250 MHz (4 ns cycle) generated by dividing the master clock 2 into two by the clock dividing / multiplying circuit 4. Needless to say, these cycles may be changed as necessary.

First, the data operation circuit 5 delays data (TC) which determines the timing of pulse generation based on the test pattern data 3 sent in synchronization with the operation clock 4-1 from a pattern generation circuit (not shown). 9-1
(D) 9-2 and (A) 9-3 are calculated and output at a timing synchronized with the operation clock. Delay data (TC) 9-1 and (D) 9-2 output from the data operation circuit 5
Is sent to the dummy pulse control circuit and the delay data (A)
9-3 is also sent to the dummy pulse control circuit.

Here, the delay data 9 (TC, D, A) have different pulse delay resolutions. In this embodiment, (TC) 9-1 uses one cycle of the operation clock 4-1 as a delay unit. It is delay data (here, 4 ns delay data). The delay data (D) 9-2 represents delay data (here, 2 ns delay data) in which the master clock cycle (1/2 cycle of the operation clock 4-1) is used as a delay unit. The delay data (A) 9-3 represents minute delay data (here, delay data of less than 2 ns) shorter than the master clock cycle (1/2 cycle of the operation clock 4-1). Here, the delay unit of the delay data (D) 9-2 is smaller than the delay resolution of the delay data (TC) 9-1.

Next, the configuration of the dummy pulse control circuit 103 is shown in FIG. The dummy pulse control circuit 103 uses the delay data (TC) 9-1 sent from the data operation circuit 5
Is "0", that is, a cycle in which a real pulse is not generated in the pulse generation circuit 101 (a period in which the pulse generation circuit 101 does not originally need to generate a pulse to generate a test waveform to be applied to the LSI) is detected. , A circuit which controls the delay data (D) 9-2 and (A) 9-3 so as to generate a dummy pulse in the cycle (time, period).

The real pulse means a pulse generated by the pulse generation circuit 101 based on the test pattern data 3 from the pattern generation circuit (the pulse generation circuit 1 based on the test pattern data 3 from the pattern generation circuit 1).
The pulse generated by the pulse generation circuit 101 does not need to be generated by the pulse generation circuit 101 from the test pattern data 3 from the pattern generation circuit. A pulse generated by the pulse generation circuit 102 in order to make it constant or the like.

The dummy pulse control circuit 103 includes FFs 109 to 111 for latching the delay data 9 once, logic gate groups 108 and 112 to 113 for controlling the output of the dummy pulse from the delay data 9, and the delay data (T
C) It is composed of a FIFO m106 and an FFmsk 107 for outputting 9-1 as a mask signal of the dummy pulse in synchronization with the dummy pulse.

In the circuit shown in FIG. 2, the FFs 109 to 111 provided in the respective delay data paths have a pipeline structure, and the output data of the FF becomes the delay data in the current cycle (4 ns) and is latched by the FF. The previous data shows the delay data in the next 4 ns (cycle). The dummy pulse control circuit 103 determines whether or not a pulse will be generated in the next cycle from the delay data (TC) and (D) before being latched by the FF, and controls the generation of the dummy pulse. . Accordingly, at the time of determining whether or not to generate the dummy pulse, it is possible to determine whether or not there is a real pulse in the period to be determined, so that the pulse generation circuit 102 generates a pulse per unit time. The number can be constant.

The delay amount of the dummy pulse generated in the next cycle is preferably determined by the delay data of the current cycle so as not to connect to the pulse generated in the current cycle. Specifically, when a real pulse in the current cycle and a dummy pulse in the next cycle (to be generated) continue, the real pulse and the dummy pulse are slightly deviated from each other. It becomes the form combined with the pulse. This is because when two pulses are connected to form one pulse (apparently visible), the pulse generation circuit may not accurately generate the pulse that should be generated. AND113, when the 2ns delay data of the pulse occurring in the current cycle is 1,
The 2 ns delay data of the pulse generated in the next cycle is also set to 1. Further, the delay data of the dummy pulse less than 2 ns is controlled by the AND 112 so that it is always 0 (see FIG. 5).

Here, the logic circuit configuration of the dummy pulse control circuit 103 shown in FIG. 2 is a delay time setting (0 ns in FIG. 2) given to the dummy pulse if the logic is such that the number of pulses generated per unit time is constant. Alternatively, it is not limited to this, including 2 ns).

In the dummy pulse control circuit 103,
Mask signal 10 for masking the dummy pulse (removing the dummy pulse) at the final stage of the pulse generation circuit 101.
Generate 3-1. Dummy pulse mask signal MSK10
3-1 is data indicating the actual pulse generation timing, and delay data (TC) 9-1 is used in FIG. However, since the dummy pulse is generated at an appropriate timing, the delay data (TC) 9-1 and the dummy pulse mask signal MSK103-1 are out of timing. That is, since the pulse (including the dummy pulse) output from the pulse generation circuit 102 and the pulse delay circuit 104 and the mask signal are asynchronous, means for synchronizing them is required. In FIG. 2, the FIFO
(Buffer) is used and FIFOm
The delay data (TC) 9-1 written in 106 is synchronized with the output pulse by using the pulse of the previous cycle output from the pulse delay circuit 104 and reading the falling timing from the FIFOm 106 as the read clock. The generated mask signal is generated.

Next, the pulse generation circuit 102 will be described with reference to FIG.
The control operation of will be described.

In the pulse generation circuit 102, by using the master clock 2 (here, 2 ns cycle) as the operation clock, the pulse can be delayed in units of 2 ns.

In FIG. 3, 2 ns delayed data (D) 103
-2 is latched by the FFd 114 in synchronization with the master clock 2 and used as a selection signal for the selection circuit in the next stage. When the delay data (D) 103-2 is "0", FFd11
4 output to FF1 (117) side, FF2 when "1"
Output to the (118) side. FF1 (117) and FF
2 (118) latches the pulse respectively sent, and FF2 (118) further FF2 '(11
Output pulse to 9). That is, if the 2 ns delay data (D) 103-2 is "1", the master clock 2
Since one more stage passes through the flip-flops operating in (2 ns cycle), the input pulse can be delayed by 2 ns and output.

Further, in the pulse generation circuit 102 shown in FIG. 3, in order to reduce the pulse width of the output pulse, FF1 (1
17) and the output of FF2 '(119), the OR of the next stage
The master clock 2 is latched by the FFor 121 via the gate (120), and the master clock 2 and the output of the FFor 121 latched once at the negative edge of the master clock 2
The ND process (As122) is being performed.

Next, in the pulse delay circuit 104, the pulse generated by the pulse generation circuit 102 is delayed by a minute time of 2 ns or less of the master clock period based on the delay data (A) 103-3 of less than 2 ns. be able to.

The operation of the pulse delay circuit 104 will be described with reference to FIG. The pulse delay circuit 104 mainly includes a delay circuit 30, a FIFO 31 for reading asynchronous delayed data (A) 103-3 in synchronization with an output pulse, and a read FF 32.

First, delay data (A) 103 of less than 2 ns
-3 is written and stored in the FIFO 31 in synchronization with the operation clock 4-1. Written delay data (A) 10
3-3 is read from the FIFO 31 by using the falling edge of the output pulse 104-1 of the immediately preceding cycle which has passed through the pulse delay circuit 104 as a trigger, and the delay circuit 30-3.
Entered in.

As shown in FIG. 19, the delay circuit 30 is composed of a delay element group 34 composed of inverters and the like and a selection circuit 33 for selecting a pulse path. Is selected and the delay amount of the pulse is determined.

In the example of FIG. 19, when the delay data is "1", the input internal pulse 6-1 passes through the path having the delay element group 34 (delay amount Ans) and having the long delay time. If the wiring delay is ignored, the pulse will be output after Ans. When the delay data is "0", the pulse passes through the path having the short delay time without the delay element group 34, so that the pulse is output after 0 ns.

Although only one pulse delay circuit 104 is shown in FIG. 4, the pulse delay circuit 104 has a multi-stage configuration and the number of combinations of delay paths (delay times) is increased to increase the variable width of the delay. Of course, it is also possible to set a detailed pulse delay.

FIG. 5 shows the operation timing in each circuit section in the pulse generation circuit.

The timing chart of FIG. 5 shows the process of generating the dummy pulse from the delay data for the dummy pulse controlled by the dummy pulse control circuit in the pulse generation circuit of this embodiment. By generating the dummy pulse, the output pulse of the pulse generation circuit always generates one pulse in 4 ns, and it is understood that the power consumption per unit time is always constant.

As described above, in the present embodiment, the dummy pulse control circuit 103 that detects a period in which a real pulse does not occur and generates a dummy pulse in that period is used for a unit time (operation clock period 4 ns in this embodiment). The pulse generation per unit time can be controlled so that the power consumption per unit time can be kept constant.

Further, by making the dummy pulse pass through the same delay circuit as the real pulse, it is not necessary to separately provide a special power consumption circuit, and the power consumption can be stabilized while the size is reduced.

Further, since the power consumption of the pulse generation circuit 101 can be made constant, a new pulse generation circuit which suppresses voltage fluctuations and temperature changes in the circuit and improves the accuracy of pulse generation time is provided. You can

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. The pulse generation circuit 201 of the present invention is based on a master clock 2, a clock division / multiplication circuit 4 capable of dividing or multiplying the master clock, and test pattern data 3 from a pattern generation circuit (not shown). A data operation circuit 5 for calculating the output pulse generation time (delay data 9 (TC, D, A)) and a period in which no pulse is generated, and at least one type of dummy pulse is generated depending on the time in which no pulse is generated. Pulse control circuit 203 for controlling
And output data from the dummy pulse control circuit 203 (delay data (TC) 203-1, 203-3, (D) 203-
2, 203-4), a pulse generation circuit 202 for generating at least one kind of dummy pulse and a real pulse, and an output pulse based on the delay data (A) 203-5 with a master clock cycle or less. A pulse delay circuit 206 having means for adjusting the number of stages of the delay circuit through which the pulse passes (adjusting the power consumption of the pulse), which is capable of delaying in a minute time, and which depends on the type of dummy pulse;
It is composed of an AND gate 212 for masking the dummy pulse from the output of the pulse delay circuit.

As an operation example, the master clock is set to 500 MHz (2 ns cycle) and the operation clock 4-1 is used.
The pulse generation circuit 201 in the case of using 250 MHz (4 ns cycle) generated by dividing the master clock by the clock division / multiplication circuit 4 will be described.

First, in the pulse generation circuit described in the first embodiment, the number of pulses generated per unit time (operation clock cycle) is constant regardless of the period in which the real pulse is generated. The power consumption per clock cycle can be made constant. However, the waveform 2 in FIG.
33, for example, a real pulse 232 is 14n
When it occurs in s, a time (circled point) where the pulse generation interval is not 4 ns occurs, and the power consumption per shorter unit time (for example, 2 ns) is not constant.

Therefore, in this embodiment (second embodiment),
In the dummy pulse control circuit 203, the time (pulse interval) in which no pulse is generated is determined from the presence / absence of pulse output in the current cycle, the pulse delay data in the next cycle, and the pulse delay data in the next cycle. By detecting and controlling the output of two types of dummy pulses under the conditions shown below, the power consumption per 2 ns (master clock cycle) is made constant. (Condition 1) When the pulse interval t before and after is 8 ns (two operation clock cycles) or more (t ≧ 8 ns) → a dummy pulse (1) with power consumption "1" at a timing 4 ns after the pulse before the operation 1 ) Is generated (condition 2) When the pulse interval t before and after is 6 ns to 8 ns or less (6 ns ≦ t <8 ns) → operation 2 A dummy pulse of power consumption “0.5” (4 ns after the pulse before the operation 2) 2) is generated (Condition 3) When the pulse interval t before and after is 6 ns or less → Operation 3 As an example in which the dummy pulse is not generated, the operation clock 4-1 is 250 MHz (4 ns
In the pulse generation circuit of (cycle), if the power consumption when one pulse is generated in 4 ns is "1", one pulse is "1" when the pulses are generated at intervals such as a 6 ns cycle. If the power equivalent to .5 "is not consumed, the power consumption per unit time will not be constant.

Therefore, the dummy pulse control circuit 203
By generating a dummy pulse (2) having a power consumption of "0.5" at a timing 4 ns after the previous pulse and compensating for the remaining power consumption of 2 ns that the dummy pulse (1) cannot bear, The power consumption per unit time (master clock 2 ns cycle) is kept constant.

Here, as shown in FIG. 9, the dummy pulse (2) divides the pulse delay circuit into halves and passes only the latter half of the delay circuit, so that the power consumption of "0.5" is obtained. Has been realized.

A dummy pulse control circuit 2 will be described with reference to FIGS.
The structure of No. 03 is shown.

The dummy pulse control circuit 203 outputs the dummy pulse control section 207 for controlling the generation of the dummy pulses (1) and (2) based on the delay data 9 and the dummy pulse mask signal MSK203-6. FIF
It is composed of Omsk 209 and FFmsk 210, and transfers the delay data 9 sent from the data operation circuit 5 in synchronization with the operation clock 4-1 and the dummy pulse control unit 207 generates a real pulse and a dummy pulse (1). , (2) delay data is generated.

Here, the output control of the dummy pulse in the dummy pulse control section 207 will be described with reference to FIGS. 8 and 20.

The dummy pulse control unit 207 has the FF 213.
Up to 220 are used to form a two-stage pipeline configuration, and each delay data is transferred. Where FF2
The outputs latched in 16 to 218 represent the delay data of the current cycle. In addition, FF213-215 and FF2
The delay data between 16 and FF218 shows the delay data of the next cycle, and the delay data before being latched by FF213-215 shows the delay data of the next cycle.

The dummy pulse control section 207 generates a dummy pulse from these delay data,
It is possible to control which kind of dummy pulse is generated.

Dummy pulse control unit 20 in this embodiment
In 7, it is possible to generate two types of dummy pulses.

The conditions for generating each dummy pulse include the following five conditions, which will be described with reference to the truth table shown in FIGS. 8 and 12.

In the pulse symbols in FIG. 12, "P" represents a normal pulse, "D" represents a dummy pulse (1), and "D" represents a dummy pulse (1).
D '"represents a dummy pulse (2), and the subscript numbers" 0 "and" 2 "of each symbol indicate the presence or absence of 2 ns delay data of the pulse.

First, the conditions for generating the dummy pulse (1) will be described. [1] The 2 ns delay data of the pulse generated in the current cycle is "0", and the 4 ns delay data of the next cycle is "
In the case of 0 ", it is understood that no pulse is generated for 8 ns or more from the pulse of the current cycle. Therefore, the AND 221 outputs the dummy pulse (1) (no 2 ns delay) in the next cycle.
The delay data is generated (see FIG. 12A). [2] When the 2 ns delay data of the pulse generated in the current cycle is "1" and the 4 ns delay data of the next cycle and the next cycle is "0", the pulse of the current cycle It can be seen that no pulse is generated for 8 ns or longer. Therefore, the AND 223 causes the dummy pulse (1) in the next cycle.
Delay data (with 2 ns delay) is generated (see FIG. 12).
(See (b)). [3] The 2 ns delay data of the pulse generated in the current cycle is "1" and the 4 ns delay data of the next cycle is "1".
When 0 "and the 4 ns delay data and the 2 ns delay data of the next cycle are" 1 ", it can be seen that there is an interval of 8 ns from the pulse of the current cycle to the next pulse. Therefore, the AND 224 generates the delay data of the dummy pulse (1) (with a delay of 2 ns) in the next cycle (see FIG. 12C).

Next, the conditions for generating the dummy pulse (2) will be described. [4] If the 2 ns delay data of the pulse generated in the current cycle is "0" and the 4 ns delay data and the 2 ns delay data of the next cycle are "1", the pulse of the current cycle It can be seen that there is a 6 ns interval before the pulse. Therefore, the AND 228 generates the delay data of the dummy pulse (2) of power consumption "0.5" (no 2 ns delay) 4 ns after the pulse of the current cycle (see FIG. 12 (d)). [5] The 2 ns delay data of the pulse generated in the current cycle is "1" and the 4 ns delay data of the next cycle is "1".
0 and the 4ns delay data of the next cycle is "
When the delay data of 1 "and 2 ns is" 0 ", it can be seen that there is a 6 ns interval from the pulse of the current cycle to the next pulse. Delay data of a dummy pulse (2) of power "0.5" (with 2 ns delay) is generated (see FIG. 12 (e)).

Further, the delay data (A) 203-5 is controlled by the AND 225 so that it becomes "0" in the period in which the dummy pulse is generated.

Here, the dummy pulse control circuit 203 is
The condition is that it is a circuit that realizes the above operation, and the circuit that realizes the above operation is not limited to the logic circuit shown in FIG.

FIG. 10 shows the configuration of the pulse generation circuit 202.

The pulse generation circuit 202 receives the delay data of the normal pulse & dummy pulse (1) and the delay data of the dummy pulse (2) from the dummy pulse control circuit 203, and receives the normal pulse & dummy pulse (1), This is a circuit for generating the dummy pulse (2), and the configuration of the pulse generation circuit itself is the pulse generation circuit 6 described in FIG.
It performs the same operation as, and delay data (TC, D)
Pulse can be generated based on

As described above, in the present embodiment, the second dummy pulse whose power consumption is adjusted is used even in the time zone in which the power consumption cannot be supplemented by the pulse control per operation clock cycle (operation clock unit time). Is generated, the power consumption of the pulse generating circuit can be kept constant.

Further, since the power consumption of the pulse generating circuit 201 can be made constant, it is possible to suppress a voltage fluctuation and a temperature change in the circuit, and to provide a new pulse generating circuit with improved accuracy of pulse generation time. You can

(Third Embodiment) Next, a third embodiment of the present invention will be described.

In the pulse delay circuit 104 of the pulse generation circuit 101, the pulse generated by the pulse generation circuit 102 can be delayed with a minute delay time of the master clock period or less based on the delay data (A) 103-3. it can. The configuration and operation of the conventional pulse delay circuit 104 are as shown in FIG.

Here, the delay circuit 301 in the present embodiment.
The circuit configuration of will be described with reference to FIG.

The delay circuit 301 comprises a delay element group 304 composed of at least one delay element such as an inverter.
And the delay element group 304 has at least two or more delay paths having different numbers of elements (= pulse propagation delay time), and the delay element group 304 is provided with a selection circuit 305 for selecting which delay path is to be passed. It is arranged in the latter stage.

As a result, in this delay circuit, the input pulse 302 passes through all delay elements of all paths regardless of which delay path is selected by the delay data (A) 303. The power consumption is constant.

By using the delay circuit 301 whose power consumption is constant irrespective of the delay path thus selected in the pulse delay circuit of the pulse generation circuit 101 described in the first embodiment, the delay to be set is set. Since it is possible to suppress the fluctuation of the power consumption due to the change of time and keep the power consumption in the pulse generating circuit constant, it is possible to realize a more highly accurate pulse generating circuit.

(Fourth Embodiment) Next, with reference to FIGS. 14 and 15, an operation of an LSI test apparatus 401, that is, a semiconductor device test (inspection) method will be described as a fourth embodiment of the present invention.

In this embodiment, an LSI test apparatus 401 using the pulse generation circuit 101 mentioned in the first embodiment will be described.

The LSI test apparatus 401 is the LSI under test 4
12 is a device for performing an operation test of an LSI by giving a test waveform 408 to 12 and comparing a response waveform 409 returned from the LSI under test 412 with an expected value prepared in advance and judging the quality.

The LSI test apparatus 401 mainly includes a pattern generation circuit 402 for generating test pattern data 404 of a test waveform and an expected value, and a timing generation circuit 406 for generating a test waveform 408 based on the test pattern.
A driver 410 that adjusts the amplitude of the test waveform 408, an analog comparison circuit 411 that determines the voltage value (L / H) of the response waveform 409, and a fail memory 40 that stores the determination result.
3 and a CPU 407 for controlling each of these circuits
And a master clock 2 for driving the LSI test apparatus 401
Composed of.

FIG. 14 is a block diagram showing an example of the IC test apparatus, and FIG. 15 is a block diagram showing an example of the configuration of the timing generation circuit.

The pattern generation circuit 402 generates test pattern data 404 (pattern data) including information on test waveforms and expected values.

The timing generation circuit 406 receives the master clock from the master clock 2 and the test pattern data 404 from the pattern generation circuit 402, and the internal pulse generation circuit 1 raises / falls the timing of the test waveform 408. (413) and a timing edge (= pulse) 413 that indicates the rising / falling timing of the strobe pulse that determines the determination timing of the response waveform 409.
414 is generated. Here, the timing generation circuit 406
As shown in FIG. 15, includes a pulse generation circuit 1, a waveform formatter 415, and a digital comparison circuit 416.

Timing edge 413 of the test waveform showing the rising / falling timing of the test waveform 408.
The waveform formatter 415 that has received is formed a test waveform from the timing edge 413 based on the test pattern data 404 from the pattern generation circuit 402 (converted into a test waveform) and outputs it as a test waveform 408 to the driver 410.

In the driver 410, the waveform formatter 4
The reference voltage and amplitude of the test waveform 408 output from 15 are adjusted and applied to the LSI under test 412.

In the analog comparison circuit 411, the LS under test is tested.
The logical value voltage (L / L of the response waveform 409 returned from I
H) is determined.

If the predetermined voltage value is satisfied, the digital comparison circuit 4 in the timing generation circuit 406 is
At 16, it is determined that the expected value is sent from the pattern generation circuit 402. If the response result does not match the expected value, the LSI is determined to be defective, and the defect determination result is written in the fail memory 403.

In the LSI test apparatus 401, the accuracy of the generation time (timing) of the test waveform affects the test performance. Especially at the timing edge generated by the pulse generation circuit 1,
Very high time accuracy is required.

In this embodiment, by applying the pulse generation circuit described in the above embodiment in the LSI test apparatus 401, fluctuations in power consumption in the pulse generation circuit are suppressed and variations in pulse generation timing due to temperature fluctuations. Therefore, it is possible to realize an LSI test apparatus capable of generating a test waveform controlled with high accuracy. Also,
The LSI test equipment 4 is indispensable for testing high-performance LSIs because it can stabilize power consumption with a small-scale circuit.
It is also possible to support 01 multi-output (multi-pin).

(Fifth Embodiment) Next, a semiconductor device testing method and a semiconductor device manufacturing method using a test waveform from the semiconductor testing device described in another embodiment will be described.

FIG. 22 is a flow chart showing a method of manufacturing a semiconductor device which is inspected and shipped by the test waveform formed by the above embodiment. In FIG. 22, the product wafer manufactured in the process of step S1 is subjected to initial defect selection by P inspection (Pellet inspection) in step S2. Then, the selected non-defective wafer proceeds to step S3 or S5. The selection as to whether to proceed to step S3 or S5 is made based on the relation of manufacturing equipment and the like.

In step S3, the product wafer is diced, and only non-defective chips are individually packaged in CSP (Chip Size Package), BGA (Ball Grid Array) or the like in step S4. Then, the process proceeds to step S7.

In step S5, the wiring pattern and the protective film are collectively formed on the wafer.
Perform solder ball attachment. Subsequently, in step S6, the wafer on which the wiring pattern and the like are formed is individually divided by dicing. Then, the process proceeds to step S7.

In step S7, a semiconductor device inspection method is performed. In other words, the final-shaped products that have been individually divided are subjected to a burn-in test for final selection. Then, the product that finally becomes a good product is step S.
Shipped at 8.

In this embodiment, S2 and S in FIG. 22 are used by using the test waveform from the semiconductor test apparatus described in the above embodiment.
The inspection step 7 is performed. This gives the timing (time)
It is possible to inspect a high-performance (high-speed-operating) semiconductor device (LSI) by using a test waveform controlled with high precision and manufacture the semiconductor device.

(Sixth Embodiment) Next, a sixth embodiment of the present invention will be described with reference to FIG. The operation of the functional blocks constituting the pulse generation circuit 101 of this embodiment is the same as that shown in FIG.

In the present embodiment, in the pulse generation circuit mounted on the circuit board, the multi-chip module or the LSI chip, the circuit group including the path through which the pulse passes and the other circuit groups include a power source and a ground (power source system). The purpose is to suppress the propagation of power supply noise and improve the accuracy of pulse generation.

The power supply and the ground are separated in the circuit board, the multi-chip module or the LSI chip,
Isolate the circuit group including the path through which the pulse passes through A-6
0, when the other circuit group is the separation area B-61,
The power supply noise generated by the operation of the circuit in the separation area B-61 is the separation area A- which is the passage path of the pulse.
Since it is possible to suppress the propagation to 60, it is possible to suppress the accuracy deterioration of the pulse generation time due to the power supply noise.

Ideally, the separated power supply and ground should be completely separated as separate power supplies. As another method, by connecting via a bypass capacitor outside the pulse generation circuit (outside the LSI chip), it is possible to reduce power supply noise from the isolation region B from flowing into the isolation region A.

Furthermore, the above-mentioned power supply separation is an example,
The same effect may be realized by designing so that the characteristic impedance in the power supply and the ground between the isolation regions A and B becomes high.

By separating the power supply region, L
The SI chip and the like also have the effect of enabling high integration.

It is needless to say that this embodiment can be applied to the above embodiments 1 to 5 and the above effects can be obtained.

(Seventh Embodiment) Next, with reference to FIG. 24, a configuration example of the data operation circuit 5 shown in FIG. 23 will be described. The purpose of this embodiment is to reduce the power supply noise itself generated from the isolation region B-61 described with reference to FIG.

In this embodiment, the dummy pulse generating circuit and the dummy circuit (power consumption circuit) are applied in the data operation circuit. In order to make the power consumption of the circuit that does not operate in the cycle of the operation clock 4-1 constant, by detecting the time when the original pulse is not generated and operating the dummy circuit prepared separately in that cycle to consume the power. , Further stabilize the power consumption of the entire pulse generation circuit,
The time accuracy of pulse generation can be improved.

The data arithmetic circuit 5 includes a counter 51 for counting operation clocks and a timing data arithmetic circuit 55.
The coincidence detector 53 that compares the output of the counter with the output delay data (TC) of the counter, and outputs the coincidence signal (pulse generation signal), and the coincidence signal. FF that latches
56, an AND 57 that takes the logical product of the operation clock 4-1 and the coincidence signal, and a dummy pulse generation circuit (AND) 58.
And a dummy circuit (power consumption circuit) 59.

In this circuit, the dummy pulse generating circuit (AN
D) Invert the coincidence signal (pulse generation signal) in 58 and take the logical sum of the operation clock 4-1 and
Dummy pulses are generated in a cycle in which no pulse is originally generated.

The dummy circuit 59 having a dummy power consumption circuit is composed of a clock buffer or the like, and has a circuit scale (power consumption) almost equal to that of a circuit which does not operate in the operation clock cycle of the original pulse generation circuit.

Therefore, the dummy circuit 59 causes the input dummy pulse to have a cycle in which no pulse originally occurs.
By consuming the same power as when the pulse is generated, the power consumption in the pulse generation circuit can be made constant.

Further, the dummy circuit 59 may have a circuit structure capable of adjusting the consumed power by providing a means for switching the passage route of the inputted dummy pulse.

(Embodiment 8) Next, referring to FIG.
Data operation circuit 5 for obtaining the same effect as in the seventh embodiment
Another embodiment will be described.

The data operation circuit 5 of FIG. 25 compares the counter 51 that counts the operation clock with the output of the counter 51 and the output delay data (CT) 52-4 from the operation circuit 52, and when they match, a match signal is output. Coincidence detector 5 that outputs
3 and the coincidence signal from the coincidence detector 53 are enabled, and the delay data 52-4 is synchronized with the operation clock 4-1.
And an arithmetic circuit 5 for generating delay data 9-2, 9-3
It consists of 2. Furthermore, the arithmetic circuit 52 in this example
Is composed of FFs 52-1, 52-3, and a circuit group 52-2 composed of FFs and combinational circuits. The FFs used here are the data signal (D) currently input by the enable signal (EN). Is to take in.

FIG. 26 is an operation chart of the data operation circuit 5, in which the counter which operates in synchronization with the operation clock 4-1 and the delay data 52- which is the output of the operation circuit 52
4, 9-2, 9-3 and the output 9- of the coincidence detector 53
1 is shown. The arithmetic circuit 5 performs a predetermined arithmetic operation on the data from the test pattern data 3 to obtain the delay data 52-4.
("2") and 9-2, 9-3 (data a) are output. The delay data 52-4 is compared with the output from the counter 51 by the successive coincidence detection circuit, and the coincidence signal (“High” level) is output when the count value is “2”. With this coincidence signal, the arithmetic circuit 52 performs an operation for generating the next delay data, and the delay data 52-4
(“5”) and the delay data 9-2 and 9-3 (data b) are output. Thereafter, similarly, the arithmetic circuit 52 similarly generates delay data.

Here, since the FF in the arithmetic circuit 52 always operates with the operation clock, current is always consumed in the portion which operates by inputting the operation clock to the FF even in the period in which data operation is not required. To be done. As a result, it is possible to reduce the increase or decrease in the current consumption amount between the period in which the delay data (TC) is generated and the period in which the delay data (TC) is not generated.

That is, in the arithmetic circuit 52, even when data calculation is not required, the FF consumes the current, thereby reducing the increase or decrease in the consumption current which is a factor of the noise voltage. .

It goes without saying that by combining the data operation circuit described in the seventh and eighth embodiments with at least one of the other first to sixth embodiments, it is possible to provide a pulse generation circuit with further improved accuracy in pulse generation time. Nor.

Furthermore, the examples described in the seventh and eighth embodiments are as follows.
Separation areas A and B of the pulse generation circuit 101 described in FIG.
This is particularly effective in the case where the above is realized by one semiconductor chip and the same power supply or ground is used.

Further, as shown in FIG. 21, the data operation circuit described in the seventh and eighth embodiments is provided with a power supply in order to keep constant power consumption during operation of the pulse generation circuit separately from the delay circuit of the pulse generation circuit. It goes without saying that the accuracy of the pulse generation time can be improved even if the consumption circuit (dummy circuit) is separately applied to the pulse generation circuit.

The arithmetic circuits 52 and 55 are circuits which can reduce the power consumption (junction temperature of the circuit) which fluctuates according to the consumed current and the power supply voltage due to the current change, by keeping the consumed current constant. It is a feature. Therefore, it goes without saying that arithmetic circuits other than the logic circuits described in the arithmetic circuits 52 and 55 can obtain the same effect within the scope of the present embodiment.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

The representative aspects disclosed in the above embodiments are as follows.

In the pulse generation circuit, the cycle in which no pulse is generated is detected from the pattern data having the information for determining whether or not the pulse is generated in the pulse generation circuit, and the cycle in which the pulse is not generated is detected. It has a dummy pulse control circuit for generating a dummy pulse.

The pulse generating circuit described above is provided with a logic gate circuit for removing the generated dummy pulse before outputting the pulse from the pulse generating circuit.

Further, in the pulse generation circuit described above, the dummy pulse control circuit further detects a delay amount caused by the dummy pulse generated by the dummy pulse control circuit passing through the pulse delay circuit. A signal for removing the dummy pulse from the dummy pulse generation circuit is output based on the detection result.

Further, in the pulse generating circuit described above, the dummy pulse control circuit further detects the timing when the dummy pulse generated by the dummy pulse control circuit passes through the pulse delay circuit, and the dummy pulse control circuit detects the detected timing. A signal for removing the dummy pulse from the dummy pulse generation circuit is output based on the timing.

Data for calculating the pulse generation time output from the pulse generation circuit based on pattern data having information for determining whether or not the pulse is generated by the pulse generation circuit An arithmetic circuit, a dummy pulse control circuit that detects a period in which a pulse is not generated in the pattern data and generates a dummy pulse in a period in which the pulse is not generated, a pulse generated based on the pattern data, and the dummy pulse And a logic gate circuit between the pulse generating circuit and the output pin for removing the dummy pulse generated by the pulse generating circuit.

The pulse generating circuit described above has a pulse delay circuit between the pulse generating circuit and the logic gate.

In the pulse generating circuit described above, the dummy pulse control circuit supplies the pulse generating circuit with first delay data, the pulse delay circuit with second delay data, and the second delay data. The delay unit of the delay data is smaller than the delay unit of the first delay data.

In the pulse generation circuit described above, the dummy pulse generation circuit can generate a plurality of types of dummy pulses.

In the pulse generating circuit described above, the pulse generating circuit provided in the pulse generating circuit generates a constant number of pulses for each cycle.

In the pulse generating circuit described above, the power consumption of the pulse generating circuit included in the pulse generating circuit is constant for each cycle.

A semiconductor inspecting apparatus comprising the pulse generating circuit described above.

A master clock, a pattern generation circuit for generating pattern data containing information on a test waveform, the master clock and the pattern data,
A timing generation circuit for generating a test waveform, a driver for applying the test waveform to a semiconductor device under test (LSI),
What is claimed is: 1. A semiconductor testing device comprising: a comparison circuit for determining a response waveform from a semiconductor device under test; and a fail memory for storing the determination result, wherein the timing generation circuit determines the rising and falling timings of the test waveform. And a waveform formatter that generates the test waveform based on the pulse, and the pulse generation circuit detects a period in which no pulse is generated by the pulse generation circuit from the pattern data. A dummy pulse control circuit for generating a dummy pulse in a cycle in which the pulse is not generated is provided.

In the semiconductor test apparatus described above, the pulse generation circuit includes a logic gate circuit for removing the dummy pulse before outputting the pulse to the waveform formatter.

A master clock, a pattern generation circuit for generating pattern data containing information about a test waveform, the master clock and the pattern data,
A timing generation circuit for generating a test waveform, a driver for applying the test waveform to a semiconductor device under test, a comparison circuit for determining a response waveform from the semiconductor device under test, and a fail memory for storing the determined result. In the semiconductor test apparatus having the above, the timing generation circuit has a pulse generation circuit that generates a pulse that determines the rising and falling timings of the test waveform, and a waveform formatter that generates the test waveform based on the pulse. Further, the pulse generation circuit further detects a period in which no pulse is generated in the pattern data, the data calculation circuit calculating a generation time of the pulse output from the pulse generation circuit based on the pattern data, A dummy pulse control circuit for generating a dummy pulse in a cycle in which the pulse is not generated, and A pulse generating circuit for generating a generated pulse and the dummy pulse, those having a logic gate circuit for removing a dummy pulse generated by the dummy pulse control circuit after the said pulse generating circuit.

A semiconductor inspection method for inspecting a semiconductor device using a test waveform formed by using the pulse generation circuit described above.

A cycle in which no pulse is generated is detected from pattern data having information for determining whether or not a pulse is generated in the pulse generation circuit for each predetermined cycle, and a cycle in which the pulse is not generated is detected. It is a semiconductor inspection method for inspecting a semiconductor device by using a test waveform formed under stable power consumption by generating a dummy pulse at.

Further, a step of forming a circuit element on the semiconductor wafer, a step of forming a wiring for electrically connecting the electrode of the circuit element and an external connection terminal on the semiconductor wafer, and a protective film on the semiconductor wafer. What is claimed is: 1. A method of manufacturing a semiconductor device, comprising: forming a semiconductor wafer; dicing the semiconductor wafer; and inspecting a semiconductor device in a state of the semiconductor wafer or in a state of being diced and individualized. , Detects a cycle in which no pulse is generated from pattern data having information for determining whether or not to generate a pulse in the pulse generation circuit for each predetermined cycle, and dummy the cycle in which the pulse is not generated. By generating a pulse, a semiconductor device that inspects a semiconductor device using a test waveform formed under stable power consumption It is a method of manufacture.

[0154]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) Since the power consumption of the pulse generation circuit per unit time can be made constant (stable), the temperature change in the pulse generation circuit is suppressed, and the propagation delay time error (variation) of the delay circuit can be reduced, A highly accurate pulse generation circuit can be realized. Further, by combining a pulse delay circuit whose power consumption does not change even if the set delay amount changes, the power consumption of the pulse generating circuit can be further kept constant. (2) It is possible to provide an LSI test apparatus that can apply a test waveform whose timing (time) is controlled with high accuracy. (3) It is possible to manufacture a semiconductor device by inspecting a semiconductor device (LSI) operating at high speed by using a test waveform whose timing (time) is controlled with high accuracy.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a dummy pulse control circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a pulse generation circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a pulse delay circuit according to the first embodiment of the present invention.

FIG. 5 is a diagram showing an effect of the present invention and timing of each circuit unit in the first embodiment.

FIG. 6 is a diagram showing a problem in the second embodiment of the present invention.

FIG. 7 is a diagram showing a second embodiment of the present invention.

FIG. 8 is a diagram showing a dummy pulse control unit according to the second embodiment of the present invention.

FIG. 9 is a diagram showing a pulse delay circuit according to a second embodiment of the present invention.

FIG. 10 is a diagram showing a pulse generation circuit according to a second embodiment of the present invention.

FIG. 11 is a diagram showing an effect of the present invention and a timing of each circuit unit in the second embodiment.

FIG. 12 is a diagram showing conditions for generating a dummy pulse according to the second embodiment of the present invention.

FIG. 13 is a diagram showing a delay circuit according to a third embodiment of the present invention.

FIG. 14 is a diagram showing an outline of an LSI test apparatus according to a fourth embodiment of the present invention.

FIG. 15 is a diagram showing a timing generation circuit in an LSI test apparatus according to a fourth embodiment of the present invention.

FIG. 16 is a schematic diagram of a conventional pulse generation circuit.

FIG. 17 is a diagram showing a pulse generation circuit in a conventional pulse generation circuit.

FIG. 18 is a diagram showing a pulse delay circuit in a conventional pulse generation circuit.

FIG. 19 is a diagram showing a delay circuit in a conventional pulse generation circuit.

FIG. 20 is a diagram showing the timing of each circuit unit in the conventional pulse generation circuit.

FIG. 21 is a diagram showing an example of a conventional pulse generation circuit.

FIG. 22 is a diagram showing the manufacturing process of the semiconductor device.

FIG. 23 is a diagram showing a pulse generation circuit according to a sixth embodiment of the present invention.

FIG. 24 is a diagram showing a data operation circuit according to a seventh embodiment of the present invention.

FIG. 25 is a diagram showing a data operation circuit according to an eighth embodiment of the present invention.

FIG. 26 is a diagram showing an operation chart according to the eighth embodiment of the present invention.

[Explanation of symbols]

1 ... Pulse generation circuit, 2 ... Master clock, 3 ... Test pattern data, 4 ... Clock division / multiplication circuit, 4-1
... operation clock, 5 ... data operation circuit, 6 ... pulse generation circuit, 6-1 ... internal pulse, 7 ... pulse delay circuit, 7-1
... delay circuit output pulse, 8 ... output pin, 9 ... delay data, 9-1 ... delay data (TC), 9-2 ... delay data (D), 9-3 ... delay data (A), 10 ... flip-flop (Hereinafter referred to as FF) FFcmp, 11 ... FF (F
Fd), 12 ... AND (A1), 13 ... AND (A
2), 14 ... FF (FF1), 15 ... FF (FF2),
16 ... FF (FF2 '), 17 ... OR, 18 ... FF (F
For), 19 ... AND (As), 30 ... Delay circuit, 31
... FIFO, 31a ... FIFO (FIFOa), 31b
... FIFO (FIFOb), 32 ... FF, 32a ... FF
(FFa), 32b ... FF (FFb), 33 ... Selection circuit, 34 ... Delay element group, 35 ... OR, 51 ... Counter,
52 ... Operation circuit, 53 ... Matching detector, 54 ... Timing data operation circuit, 55 ... Timing data operation circuit, 5
6 ... FF, 57 ... AND, 58 ... AND, 59 ... Dummy circuit (power consumption circuit), 60 ... Separation area A, 61 ... Separation area B, 101 ... Pulse generation circuit, 102 ... Pulse generation circuit, 103 ... Dummy pulse Control circuit 103-1 ... Dummy pulse mask signal MSK, 103-2 ... Delay data (D), 103-3 ... Delay data (A), 104 ... Pulse delay circuit, 104-1 ... Delay circuit output pulse, 105 ...
AND, 106 ... FIFO (FIFOm), 107 ... F
F (FFmsk), 108 ... OR, 109 ... FF, 110
... FF, 111 ... FF, 112 ... AND, 113 ... AN
D, 114 ... FF (FFd), 115 ... AND (A
1), 116 ... AND (A2), 117 ... FF (FF
1), 118 ... FF (FF2), 119 ... FF (FF
2 '), 120 ... OR, 121 ... FF (FFor), 12
2 ... AND (As), 201 ... Pattern generation circuit, 20
2 ... Pulse generation circuit, 203 ... Dummy pulse control circuit,
204 ... Normal pulse & dummy pulse (1) generation circuit, 2
04-1 ... Normal pulse & dummy pulse (1), 205 ...
Dummy pulse (2) circuit, 205-1 ... Dummy pulse (2), 206 ... Pulse delay circuit, 206-1 ... Delay circuit output pulse, 206-2 ... Read clock, 207 ...
Dummy pulse (1) control unit, 207-1 ... Dummy (1)
Delay data (TC), 207-2 ... Dummy (1) Delay data (D), 208 ... Dummy pulse (2) Control circuit, 2
08-1 ... dummy (2) delay data (TC), 208-2
... dummy (2) delay data (D), 209 ... FIFO
(FIFOmsk), 210 ... FF (FFmsk), 211 ...
OR, 212 ... AND, 213 ... FF, 214 ... FF,
215 ... FF, 216 ... FF, 217 ... FF, 218 ...
FF, 219 ... FF, 220 ... FF, 221 ... AND,
222 ... FF, 223 ... AND, 224 ... AND, 22
5 ... AND, 226 ... OR, 301 ... Delay circuit, 302
... input pulse, 303 ... delay data (A), 304 ... delay element group, 305 ... selection circuit, 306 ... output pulse, 4
01 ... LSI test device, 402 ... Pattern generation circuit, 4
03 ... Fail memory, 404 ... Test pattern data, 405 ... Judgment result, 406 ... Timing generation circuit,
407 ... CPU, 408 ... Test waveform, 409 ... Response waveform, 410 ... Driver, 411 ... Analog comparison circuit, 4
12 ... LSI to be tested, 413 ... Timing edge (pulse), 414 ... Timing edge (pulse), 415 ...
Waveform formatter 416 ... Digital comparison circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Kenichi Shinbo             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside the Hitachi, Ltd. production technology laboratory (72) Inventor Ritsuro Orihashi             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside the Hitachi, Ltd. production technology laboratory (72) Inventor Tadashi Fukusaki             Hitachi Electronics, 3-16-3 Higashi, Shibuya-ku, Tokyo             Engineering Co., Ltd. (72) Inventor Nobuo Motoki             Hitachi Electronics, 3-16-3 Higashi, Shibuya-ku, Tokyo             Engineering Co., Ltd. F-term (reference) 2G132 AB07 AD07 AE06 AE08 AG01                       AG08 AL00

Claims (19)

[Claims] 1. A pulse generation circuit detects a period in which a pulse is not generated from pattern data having information for determining whether or not to generate a pulse, and generates a dummy pulse in a period in which the pulse is not generated. A pulse generation circuit having a dummy pulse control circuit. 2. The pulse generating circuit according to claim 1, further comprising a logic gate circuit for removing the generated dummy pulse before outputting the pulse from the pulse generating circuit. Pulse generator circuit. 3. The pulse generation circuit according to claim 1, wherein the dummy pulse control circuit further includes a delay amount generated by a dummy pulse generated by the dummy pulse control circuit passing through a pulse delay circuit. Is detected and a signal for removing the dummy pulse from the dummy pulse control circuit is output based on the detection result. 4. The pulse generation circuit according to claim 1, wherein the dummy pulse control circuit further detects a timing when a dummy pulse generated by the dummy pulse control circuit has passed through a pulse delay circuit, A pulse generation circuit, which outputs a signal for removing a dummy pulse from the dummy pulse control circuit based on the detected timing. 5. A data calculation circuit for calculating a generation time of a pulse output from the pulse generation circuit based on pattern data having information for determining whether the pulse generation circuit generates a pulse or not. A dummy pulse control circuit for detecting a period in which no pulse is generated in the pattern data and generating a dummy pulse in the period in which the pulse is not generated; and a pulse generation circuit for generating a pulse generated based on the pattern data and the dummy pulse ,
A pulse generation circuit comprising a logic gate circuit between the pulse generation circuit and an output pin and for removing a dummy pulse generated by the pulse generation circuit. 6. The pulse generation circuit according to claim 5, further comprising a circuit for delaying a pulse generated by the pulse generation circuit between the pulse generation circuit and the logic gate. Generator circuit. 7. The pulse generation circuit according to claim 6, wherein the dummy pulse control circuit supplies first delay data to the pulse generation circuit and second delay data to the pulse delay circuit, Further, the pulse generation circuit is characterized in that the delay resolution of the second delay data is smaller than the delay resolution of the first delay data. 8. The pulse generation circuit according to claim 1, wherein the dummy pulse control circuit is capable of generating a plurality of types of dummy pulses. 9. The pulse generation circuit according to claim 1, wherein the pulse generation circuit included in the pulse generation circuit generates a constant number of pulses for each cycle. A pulse generation circuit characterized by the above. 10. The pulse generating circuit according to claim 1, wherein power consumption of the pulse generating circuit is constant for each cycle. 11. A semiconductor inspection apparatus comprising the pulse generation circuit according to claim 1. Description: 12. A master clock, a pattern generation circuit for generating pattern data including information on a test waveform, a timing generation circuit for receiving the master clock and the pattern data and generating a test waveform, and the test waveform. A semiconductor test apparatus having a driver applied to a semiconductor device under test, a comparison circuit for judging a response waveform from the semiconductor device under test, and a fail memory for storing the judgment result, wherein the timing generation circuit is a test circuit. The pulse generation circuit has a pulse generation circuit that generates a pulse that determines the rising and falling timings of the waveform, and a waveform formatter that generates the test waveform based on the pulse. The pulse generation circuit further generates a pulse from the pattern data. The circuit detects a period in which no pulse is generated, and determines the period in which the pulse is not generated. A semiconductor test apparatus comprising a dummy pulse control circuit for generating a dummy pulse. 13. The semiconductor test apparatus according to claim 12, wherein the pulse generation circuit includes a logic gate circuit for removing the dummy pulse before outputting the pulse to the waveform formatter. Semiconductor test equipment. 14. A master clock, a pattern generation circuit for generating pattern data including information on a test waveform, a timing generation circuit for receiving the master clock and the pattern data and generating a test waveform, and the test waveform. A driver applied to the semiconductor device under test, and a comparison circuit for determining a response waveform from the semiconductor device under test,
A semiconductor test apparatus having a fail memory for storing the result of judgment, wherein the timing generation circuit generates a pulse for determining a rising timing and a falling timing of the test waveform, and a pulse generation circuit for generating a pulse based on the pulse. The pulse generation circuit further includes a waveform formatter for generating a test waveform, and the pulse generation circuit calculates a pulse generation time output from the pulse generation circuit based on the pattern data; A dummy pulse control circuit for detecting a period in which no pulse is generated by the pulse generation circuit and generating a dummy pulse in the period in which the pulse is not generated; a pulse generated based on the pattern data and a pulse generation circuit for generating the dummy pulse , The dummy pulse control circuit generated after the pulse generation circuit The semiconductor test apparatus characterized by comprising a logic gate circuit for removing Parusu. 15. A semiconductor inspection method, comprising inspecting a semiconductor device using a test waveform formed by using the pulse generating circuit according to claim 1. Description: 16. A pulse generation circuit detects a cycle in which no pulse is generated from pattern data having information for determining whether to generate a pulse or not in a pulse generation circuit for each predetermined cycle, and the pulse is generated. A semiconductor inspection method characterized by inspecting a semiconductor device by using a test waveform formed under stable power consumption by generating a dummy pulse in a cycle not performed. 17. A step of forming a circuit element on a semiconductor wafer, a step of forming wiring for electrically connecting an electrode of the circuit element and an external connection terminal on the semiconductor wafer, and a protective film on the semiconductor wafer. What is claimed is: 1. A method of manufacturing a semiconductor device, comprising: forming a semiconductor wafer; dicing the semiconductor wafer; and inspecting a semiconductor device in a state of the semiconductor wafer or in a state of being diced and individualized. , Detects a cycle in which no pulse is generated from pattern data having information for determining whether or not to generate a pulse in the pulse generation circuit for each predetermined cycle, and dummy the cycle in which the pulse is not generated. A semiconductor device is inspected by using a test waveform formed under stable power consumption by generating a pulse. Of manufacturing a semiconductor device. 18. The pulse generation circuit according to claim 1, wherein a circuit group including a path through which an output pulse passes, and a power supply and a ground of a second circuit group other than the circuit group. A pulse generation circuit characterized by separating the. 19. The pulse generating circuit according to claim 18, wherein a dummy consuming circuit is provided in the second circuit group.