JP2003273236A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress an increase in the number of manufacturing processes and to separately manufacture a gate electrode of an MISFET of a memory and a gate electrode of an MISFET of a logic part in a semiconductor integrated circuit device provided with the memory and the logic part on the same substrate. <P>SOLUTION: A gate electrode 10A composed of a laminated layer of a silicon polycrystal film, a tungsten nitride film and a tungsten film is formed in the memory and at the same time, a dummy gate electrode in the same structure as the gate electrode 10A is formed in the logic part. Afterwards, the tungsten film and the tungsten nitride film in the laminated film comprising the dummy gate electrode are eliminated, and further, a silicide layer 26 is formed on the surface of the silicon polycrystal film to form a gate electrode 10C composed of a silicon polycrystal film and the silicide layer 26 in the logic part. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technology of a semiconductor integrated circuit device, and more particularly to a logic circuit in which a memory circuit and a logic circuit are provided on the same substrate.
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having an embedded memory.

[0002]

2. Description of the Related Art For example, IMD
ternational Electron Device Meetings. "An Embedded
0.405 μm ² Stacked DRAM Technology Integrated with
High-performance 0.2 μm CMOS Logic and 6-Level Me
As described in "Tallization" PP41-44, 1999), in a semiconductor integrated circuit device having a memory circuit and a logic circuit on the same substrate, a MISFET (Metal Insulator Semiconductor) for selecting a memory cell that constitutes the memory circuit is used.
The gate electrode of the field effect transistor and the gate electrode of the MISFET forming the logic circuit have the same structure, for example, a polymetal structure in which a silicon polycrystal film, a barrier metal film, and a refractory metal film are sequentially stacked from the lower layer. There is. The barrier metal film is made of, for example, tungsten nitride (WN), and the refractory metal film is made of, for example, tungsten (W).

[0003]

In response to the demand for higher speed semiconductor integrated circuit devices, increasing the operating frequency of the ring oscillator of the logic section has been studied. However, in the gate electrode having the polymetal structure, the contact resistance at the interface between the silicon polycrystal film and the barrier metal film is 1 kΩ or more. Therefore, the operating frequency of the ring oscillator is from the current frequency, for example, 400 MHz to a desired frequency, for example, 500 MHz. Cannot raise to ~ 700MHz.

Therefore, the MI for memory cell selection in the memory section
The gate electrode of the SFET has a polymetal structure having a sheet resistance of about 4 to 5 Ω / □, which is composed of a laminated film of a conventional silicon polycrystal film, a barrier metal film and a refractory metal film, and the gate electrode of the MISFET of the logic portion is made of silicon polycrystal The present inventor has conducted studies on a silicided gate structure in which a silicide layer is formed on the surface of the film. By adopting this silicided gate structure, the contact resistance at the interface between the silicon polycrystalline film and the silicide layer becomes 1 kΩ or less, and the desired operating frequency of the ring oscillator can be obtained.

However, if the gate electrode of the memory cell selecting MISFET in the memory section and the gate electrode of the MISFET in the logic section are made to have different structures and the respective gate electrodes are simply made in different steps, the number of manufacturing steps increases. The problem remains that the throughput of the semiconductor integrated circuit device increases.

An object of the present invention is to suppress the increase in the number of manufacturing steps in a semiconductor integrated circuit device having a memory section and a logic section on the same substrate, and to suppress the increase in the number of manufacturing steps so that the memory section has an MI of polymetal structure.
It is an object of the present invention to provide a technique capable of forming a gate electrode of an SFET and a gate electrode of a MISFET having a silicided gate structure in a logic portion.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

According to the present invention, when a semiconductor integrated circuit device having a memory section and a logic section on the same semiconductor substrate is formed, a laminated film including a silicon polycrystalline film, a barrier metal film and a refractory metal film is formed on the semiconductor substrate. A film and a silicon nitride film are sequentially deposited from the lower layer, and by patterning them, a MIS for memory cell selection including a laminated film is formed in the memory section.
Forming a gate electrode of the FET and simultaneously forming a dummy gate electrode having the same structure as the gate electrode of the MISFET for memory cell selection in the logic part, and forming an insulating film on the semiconductor substrate, and then forming a dummy gate in the logic part A step of polishing and removing the insulating film and the silicon nitride film of the logic part until the surface of the laminated film forming the electrode is exposed, and a refractory metal film and a barrier metal film of the laminated film forming the dummy gate electrode of the logic part And a silicide layer is formed on the surface of the silicon polycrystalline film of the laminated film forming the dummy gate electrode of the logic portion, and a MISFET of the laminated film of the silicon polycrystalline film and the silicide layer is formed in the logic portion. And a step of forming a gate electrode.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) A method of manufacturing a semiconductor integrated circuit device according to the first embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 1, an element isolation groove 2 is formed in a main surface of a substrate 1 made of, for example, p-type silicon single crystal. The element isolation groove 2 is formed by etching the substrate 1 in the element isolation region to form a groove having a depth of about 350 μm, and subsequently depositing a silicon oxide film 3 on the substrate 1 by a CVD (Chemical Vapor Deposition) method. The external silicon oxide film 3 is formed by removing it by CMP (Chemical Mechanical Polishing).

Then, a p-type impurity such as boron is ion-implanted into a part of the substrate 1 and an n-type impurity such as phosphorus is ion-implanted into another part of the substrate 1 to form the p-well 4 and the n-wells 5 and 6, respectively. After the formation, an n
A high concentration n ⁺ semiconductor region 7 is formed by ion-implanting a type impurity such as arsenic.

Next, as shown in FIG. 2, memory cell selecting MISFETs are formed in the memory portion, and MISFETs having dummy gate electrodes are formed in the peripheral portion and the logic portion. These MISFETs can be formed as follows, for example. The peripheral part and the logic part have n
Although the channel MISFET and the p-channel MISFET are formed, the n-channel MISFET is illustrated here and the p-channel MISFET is omitted from the drawing.

First, the substrate 1 is heat-treated to form the gate insulating film 8 on each surface of the p well 4 and the n well 5. Next, a conductor film for a gate electrode is formed on the upper layer of the gate insulating film 8, and subsequently, a silicon nitride film 9 is deposited on the upper layer by a CVD method, and then the silicon nitride film 9 is dry-etched using the resist pattern as a mask. By patterning and the conductor film for the gate electrode, the gate electrode 10A (word line WL) is formed in the memory portion, and the dummy gate electrode 10B is formed in the peripheral portion and the logic portion. The conductor film for the gate electrode is formed of, for example, a laminated film of a silicon polycrystalline film deposited by the CVD method and a tungsten nitride film and a tungsten film deposited by the sputtering method. The thicknesses of the silicon polycrystalline film, the tungsten nitride film and the tungsten film are, for example, about 100 nm, 5 nm and 50 nm, respectively.

Then, the resist pattern was removed.
After that, using an etching solution such as hydrofluoric acid, the surface of the substrate 1
The dry etching residue and the resist residue left on the
Leave. Then, an n-type impurity such as arsenic is added to the p well 4.
By ion implantation^-The semiconductor region 11 is formed, and
P-type impurities such as boron are ion-implanted into the p-type ^-
After forming the semiconductor region, silicon is formed on the substrate 1 by the CVD method.
A nitride film 12 is deposited.

Next, the silicon nitride film 12 in the peripheral portion and the logic portion is anisotropically etched to form the dummy gate electrode 1.
After forming the spacer 12a on the side wall of 0B, the p well 4 in the peripheral portion and the logic portion and the n ⁺ semiconductor region 7 in the capacitor portion are formed.
N-type impurities, for example, arsenic, are ion-implanted to form an n ⁺ semiconductor region 13, and the n well 5 of the peripheral portion and the logic portion is formed.
A p-type impurity such as boron is ion-implanted into the p ⁺ semiconductor region to form a p ⁺ semiconductor region. The n ⁻ semiconductor region 11 and the n ⁺ semiconductor region 13 in the peripheral portion and the logic portion are n-channel MISs.
The source / drain of the FET is formed, and the p ⁻ semiconductor region and the p ⁺ semiconductor region form the source / drain of the p-channel MISFET.

Next, as shown in FIG. 3, the source / drain of the n-channel MISFET in the peripheral portion and the logic portion, p
A silicide layer 14 is formed on the surface of each of the source / drain of the channel MISFET and the n ⁺ semiconductor region 13 of the capacitance portion to reduce the contact resistance with a wiring (described later) connected to them. Silicide layer 1
4 is, for example, a cobalt or titanium film is deposited on the substrate 1 by a sputtering method, and then the substrate 1 is heat-treated.
(N ⁺ semiconductor region 13, p ⁺ semiconductor region) is reacted with the cobalt or titanium film to form a silicide layer 1 at the interface between the two.
After forming 4, the unreacted cobalt or titanium film is removed by etching.

In order to prevent deterioration of refresh characteristics due to increase in leak current, the silicide layer 14 is not formed on the surface of the source / drain of the memory cell selecting MISFET formed in the memory portion.

Next, the insulating film 15 is formed on the substrate 1.
This insulating film 15 can be formed as follows, for example. First, SOG (Spin On Glas
s) After depositing the film, heat treatment is performed to bake the SOG film. Then, after depositing a silicon oxide film on the SOG film, this silicon oxide film is polished by the CMP method to flatten its surface. The silicon oxide film is, for example, TEOS.
(Tetra Ethyl Ortho Silicate) and ozone can be deposited by the plasma CVD method using the source gas.

Next, by dry etching using the resist pattern as a mask, M for memory cell selection in the memory section is selected.
Contact holes 16 and 17 are formed in the insulating film 15 and the silicon nitride film 12 above the source / drain of the ISFET. At the same time, a contact hole 18 is formed in the insulating film 15 and the silicon nitride film 12 above the n ⁺ semiconductor region 7 of the capacitor portion. Then, after removing the resist pattern, a polycrystalline silicon film 20 having n-type conductivity is deposited on the insulating film 15 including the insides of the contact holes 16 to 18 by the CVD method.

Next, as shown in FIG. 4, after depositing a silicon nitride film 21 on the upper layer of the polycrystalline silicon film 20, the silicon nitride film 21 is patterned by dry etching using a resist pattern as a mask to form a memory portion. , The capacitor part, and the silicon nitride film 21 is left on the peripheral part and part of the logic part.

Next, as shown in FIG. 5, after removing the resist pattern, the silicon nitride film 21 is made to function as a stopper layer, and the silicon polycrystalline film 20 and the insulating film 15 are formed.
By a CMP method, and further by a CMP method including the silicon nitride films 9 and 21, a plug made of the polycrystalline silicon film 20 inside the contact holes 16 to 18 formed in the memory section and the capacitor section. 22 is formed,
Further, the surface of the tungsten film of the laminated film forming the dummy gate electrode 10B in the peripheral portion and the logic portion is exposed.

Next, as shown in FIG. 6, after forming a resist pattern 23 in the memory portion and the capacitor portion, the dummy gate electrode 10B in the peripheral portion and the logic portion is formed by dry etching using the resist pattern 23 as a mask. The tungsten film and the tungsten nitride film are removed from the constituent laminated film to expose the silicon polycrystalline film.

Next, as shown in FIG. 7, after removing the resist pattern 23, a silicon nitride film 24 is deposited on the substrate 1. Next, a resist pattern 25 is formed in the memory portion and the capacitor portion using the same mask as that used for forming the resist pattern 23, and then dry etching is performed using the resist pattern 25 as a mask.
The silicon nitride film 24 in the peripheral portion and the logic portion is removed.

Next, as shown in FIG. 8, after removing the resist pattern 25, a thickness of 10 to 10 is formed on the substrate 1.
A cobalt film of about 20 nm is deposited by the sputtering method. Subsequently, the substrate 1 is subjected to a heat treatment at about 500 to 600 ° C., and a thickness of 30 is selectively applied to the surface of the silicon polycrystalline film forming the dummy gate electrodes 10B in the peripheral portion and the logic portion.
A silicide layer 26 having a thickness of about nm is formed. After that, unreacted cobalt is removed, and then heat treatment at about 700 to 800 ° C. is applied to the substrate 1 to reduce the resistance of the silicide layer 26. As a result, the gate electrode 10C made of the silicon polycrystalline film and the silicide layer 26 is provided in the peripheral portion and the logic portion.
Is formed.

Next, as shown in FIG. 9, after depositing a silicon oxide film 27 on the substrate 1, the silicon oxide film 27 is deposited.
Is polished by CMP to planarize the surface, and the silicon nitride film 24 is removed. The silicon oxide film 27 can be deposited by, for example, a plasma CVD method using TEOS and ozone as source gases.

Subsequently, CV is formed on the upper layer of the silicon oxide film 27.
After depositing the silicon oxide film 28 by the D method, the silicon oxide film 28 above the contact hole 16 in the memory portion is etched to form a through hole 29. In the surrounding area,
Contact holes 31 and 32 are formed by etching the silicon oxide films 28 and 27 and the insulating film 15 above the n ⁺ semiconductor region 13, the p ⁺ semiconductor region and the gate electrode 10C of the logic portion and the capacitance portion, respectively.

Next, after depositing a titanium film on the substrate 1 including the insides of the through holes 29 and the contact holes 31 and 32 by a highly directional sputtering method, a titanium nitride film is deposited on the substrate 1 by a sputtering method, Subsequently, a titanium nitride film and a tungsten film are sequentially deposited by the CVD method.
Then, the tungsten film, the titanium nitride film, and the titanium film outside the through hole 29 and outside the contact holes 31 and 32 are removed by the CMP method, so that the plug 33 is formed inside the through hole 29 and inside the contact holes 31 and 32. Form.

After that, the bit line BL is formed above the through hole 29 of the memory portion, and the wiring 34 of the first layer is formed above the contact holes 31 and 32 of the peripheral portion, the logic portion and the capacitance portion. The bit line BL and the wiring 34 are formed by depositing a tungsten film on the substrate 1 by a sputtering method and then patterning the tungsten film by dry etching using a resist pattern as a mask.

Next, as shown in FIG. 10, C is formed on the substrate 1.
After the silicon oxide film 35 is deposited by the VD method, the silicon oxide film 35 and the underlying silicon oxide film 28 are patterned by dry etching using the resist pattern as a mask, so that the through hole is formed above the contact hole 17 in the memory portion. A hole 36 is formed, and a through hole 37 is formed above the contact hole 18 of the capacitance section.

Next, a silicon polycrystalline film having n-type conductivity is deposited by the CVD method on the silicon oxide film 35 including the insides of the through holes 36 and 37, and then the through hole 3 is formed.
By removing the silicon polycrystalline film outside the layers 6, 37 by the CMP method, the plugs 38 are formed inside the through holes 36, 37.

Next, as shown in FIG. 11, C is formed on the substrate 1.
After depositing the silicon nitride film 39 by the VD method and subsequently depositing the silicon oxide film 40 on the upper layer of the silicon nitride film 39 by the CVD method, the silicon oxide film 40 and the underlying silicon nitride film 39 are formed using the resist pattern as a mask. By etching, a concave groove 41 is formed above the through hole 36 of the memory portion, and a concave groove 42 is formed above the through hole 37 of the capacitance portion. When the silicon oxide film 40 is etched, the underlying silicon nitride film 39 is used as an etching stopper layer to prevent the underlying silicon oxide film 35 from being deeply etched.

Next, as shown in FIG. 12, concave grooves 41, 4
2 and the lower electrode 43 is formed inside the
By forming the capacitive insulating film 44 and the upper electrode 45 in the upper layer, the information storage capacitive element Cs is formed in the memory portion and the capacitive element Cn is formed in the capacitive portion. The capacitive element Cn of the capacitive section has the same shape and the same size as the information storage capacitive element Cs of the memory section.

To form the information storage capacitive element Cs and the capacitive element Cn, first, a silicon polycrystalline film having n-type conductivity is formed by CVD on the upper layer of the silicon oxide film 40 including the insides of the grooves 41 and 42. Groove 41, 42 after being deposited by the method
The lower portion of the lower electrode 43 is formed along the inner walls of the concave grooves 41 and 42 by removing the silicon polycrystal film outside the substrate by etching. The lower electrode 43 may be formed using a conductive material other than polycrystal silicon, for example, a refractory metal such as tungsten or ruthenium, or a conductive metal oxide such as ruthenium oxide or iridium oxide. The surface area of the lower electrode 43 may be further increased by roughening the surface.

Next, a thin tantalum oxide film is deposited on the lower electrode 43 by the CVD method, and subsequently, a heat treatment at about 800 ° C. is performed, and then, for example, CV is formed on the upper layer of the tantalum oxide film.
After the titanium nitride film is deposited by using the D method and the sputtering method in combination, the titanium nitride film and the tungsten oxide film are patterned by dry etching using the resist pattern as a mask. The capacitance insulating film 44 is formed of, for example, BST, barium titanate, lead titanate, PZT, PL.
It can also be made of a high dielectric material made of a metal oxide such as T or PLZT. The upper electrode 45 can also be formed using a conductive material other than titanium nitride, such as tungsten. Further, an information storage capacitive element C
The s and the capacitance element Cn may have a shape other than the above, for example, a fin shape.

Next, as shown in FIG. 13, a second-layer wiring 46 mainly made of an aluminum alloy film is formed on the upper layer of the information storage capacitive element Cs and the capacitive element Cn. To form the wiring 46, first, the silicon oxide film 47 is deposited on the substrate 1 by the CVD method, and then the silicon oxide films 47 and 40 and the silicon nitride film 39 are used with the resist pattern as a mask.
By dry etching the silicon oxide film 35 and the silicon oxide film 35, a through hole 48 is formed above the first layer wiring 34 in the peripheral portion and the logic portion, and a through hole is formed above the first layer wiring 34 in the capacitor portion. 49 is formed.

Next, after depositing a titanium nitride film and a tungsten film on the substrate 1 by the CVD method, through holes 48,
The plug 50 is formed inside the through holes 48 and 49 by removing these films outside the 49 by etching or CMP. Next, a titanium film, an aluminum alloy film, a titanium film, and a titanium nitride film are sequentially deposited on the substrate 1 by a sputtering method, and then these films are patterned by dry etching using a resist pattern as a mask to form a wiring 46. .

By the steps so far, the semiconductor integrated circuit device of the first embodiment is almost completed. In an actual semiconductor integrated circuit device, about 1 to 2 layers of wiring are formed on the upper layer of the second-layer wiring 46 via an interlayer insulating film, and a dense passivation film having high water resistance is further formed on the wiring. For example, a laminated film of a silicon oxide film and a silicon nitride film deposited by the plasma CVD method is formed, but their illustration is omitted.

As described above, according to the first embodiment, the gate electrode 10A of the MISFET formed of the laminated film of the silicon polycrystalline film, the tungsten nitride film and the tungsten film is formed in the memory portion, and at the same time, the peripheral portion and the logic portion are formed. After forming a dummy gate electrode 10B having the same structure as the gate electrode 10A, the tungsten film and the tungsten nitride film are removed from the laminated film forming the dummy gate electrode 10B, and the silicide layer 26 is formed on the surface of the silicon polycrystalline film.
To form a gate electrode 10A of a MISFET having a polymetal structure composed of a silicon polycrystal film, a tungsten nitride film and a tungsten film in the memory part, and a silicided gate composed of the silicon polycrystal film and the silicide layer 26 in the peripheral part and the logic part. Structure MISFET
Gate electrode 10C is formed. Therefore, an increase in the number of manufacturing steps can be suppressed as compared with a method in which a gate electrode having a polymetal structure is formed in the memory portion and a gate electrode having a silicided gate structure is separately formed in the peripheral portion and the logic portion in separate steps.

(Second Embodiment) A method of manufacturing a semiconductor integrated circuit device according to the second embodiment will be described in the order of steps with reference to FIGS.

First, in the first embodiment, as shown in FIG.
Similarly to the manufacturing method described with reference to FIG. 2, an n-channel MIS having a memory cell selecting MISFET in the memory portion and a dummy gate electrode 10B in the peripheral portion and the logic portion.
Form the FET and p-channel MISFET.

Next, as shown in FIG. 14, C is formed on the substrate 1.
After depositing the silicon oxide film 51 by the VD method, the surface of the silicon oxide film 51 in the memory portion is removed by dry etching using the resist pattern as a mask. Then, in FIG.
As shown in, the silicon nitride films 9 and 12 are made to function as stopper layers, and the silicon oxide film 51 is polished by the CMP method to flatten its surface.

Next, as shown in FIG. 16, C is formed on the substrate 1.
After depositing the silicon oxide film 52 by the VD method, the silicon oxide film 52 other than the memory portion is removed by dry etching using the resist pattern 53 as a mask until the silicon nitride film 9 in the peripheral portion and the logic portion is exposed.

Next, as shown in FIG. 17, after removing the resist pattern 53, the silicon nitride film 9 in the peripheral portion and the logic portion is removed, and the surfaces of the silicon oxide films 51 and 52 are slightly etched back. After that, the tungsten film and the tungsten nitride film in the laminated film forming the dummy gate electrodes 10B in the peripheral portion and the logic portion are removed. Here, the gate electrode 10A of the memory cell selecting MISFET in the memory portion is covered with the silicon oxide films 51 and 52.

Next, as shown in FIG. 18, after depositing a cobalt film on the substrate 1 by sputtering, 500 to 6
The substrate 1 is subjected to a heat treatment at about 00 ° C. to selectively form the silicide layer 26 on the surface of the silicon polycrystalline film forming the dummy gate electrodes 10B in the peripheral portion and the logic portion.
After that, unreacted cobalt is removed, and then heat treatment at about 700 to 800 ° C. is applied to the substrate 1 to reduce the resistance of the silicide layer 26. As a result, in the peripheral part and the logic part,
A MISFET having a gate electrode 10C made of a silicon polycrystalline film and a silicide layer 26 is formed.

Next, as shown in FIG. 19, on the substrate 1,
After forming the insulating film 27 whose surface is flattened, the contact holes 16 and 17 are formed in the memory portion and the contact hole 18 is formed in the capacitor portion. Then contact hole 16
To 18 are deposited on the substrate 1 including the inside of the substrate 1 by the CVD method, and then the silicon polycrystalline film outside the contact holes 16 to 18 is removed. To form.

Next, after depositing the silicon oxide film 28 on the substrate 1 by the CVD method, the through hole 29 is formed in the memory portion and the contact holes 31, 3 are formed in the peripheral portion, the logic portion and the capacitance portion.
2 are formed, and then the bit line BL and the first-layer wiring 34
To form. Subsequent steps are the same as those in the first embodiment.

As described above, according to the second embodiment, as in the first embodiment, the gate electrode of the polymetal structure is formed in the memory portion, and the gate electrode of the silicidated gate structure is formed in the peripheral portion and the logic portion in different steps. It is possible to suppress an increase in the number of manufacturing steps as compared with the method in which each is separately manufactured.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above-mentioned embodiment, the gate electrodes of the MISFETs in the peripheral portion and the logic portion have the silicided gate structure in which the silicide layer is formed on the silicon polycrystalline film, but the invention is not limited to this. A gate electrode having a different structure from the gate structure of the gate electrode of the memory cell selecting MISFET of the memory section can be manufactured as the MISFET of the peripheral section and the logic section.

[0052]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

When forming a semiconductor integrated circuit device having a memory portion and a logic portion on the same substrate, the gate electrode of the MISFET for selecting a memory cell having a polymetal structure and the logic are formed in the memory portion while suppressing an increase in the number of manufacturing steps. A gate electrode of a MISFET having a silicidated gate structure can be formed in the portion.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 11 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 13 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 15 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 16 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 17 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 18 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 19 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

[Explanation of symbols]

1 substrate 2 device isolation trench 3 silicon oxide film 4 p-well 5 n-well 6 n-well 7 n ⁺ semiconductor region 8 a gate insulating film 9 silicon nitride film 10A gate electrode 10B dummy gate electrode 10C gate electrode 11 n ^- semiconductor region 12 of silicon nitride Film 12a Spacer 13 n ⁺ Semiconductor region 14 Silicide layer 15 Insulating film 16 Contact hole 17 Contact hole 18 Contact hole 20 Silicon polycrystalline film 21 Silicon nitride film 22 Plug 23 Resist pattern 24 Silicon nitride film 25 Resist pattern 26 Silicide layer 27 Silicon oxide Film 28 Silicon oxide film 29 Through hole 31 Contact hole 32 Contact hole 33 Plug 34 Wiring 35 Silicon oxide film 36 Through hole 37 Through hole 38 Plug 39 Silicon nitride film 40 Silicon Chemical film 41 Concave groove 42 Concave groove 43 Lower electrode 44 Capacitive insulating film 45 Upper electrode 46 Wiring 47 Silicon oxide film 48 Through hole 49 Through hole 50 Plug 51 Silicon oxide film 52 Silicon oxide film 53 Resist pattern WL Word line BL Bit line Cs Information storage capacitive element Cn capacitive element

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/088 H01L 21/90 A 27/092 C 27/108 (72) Inventor Toshihiko Takakura Ome City, Tokyo 6-16 Shinmachi 3 Hitachi Ltd. Device Development Center (72) Inventor Yasuhiro Nariyoshi 5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi Ultra LIS Systems Inc. ( 72) Inventor Kaoru Osanotani 3-16-16 Shinmachi, Ome-shi, Tokyo Within Hitachi Device Development Center (72) Inventor Keisei Koporu 3-16-6 Shinmachi, Ome-shi, Tokyo Hitachi Device Co., Ltd. F-term in development center (reference) 4M104 AA01 BB01 BB14 CC05 DD03 DD37 DD43 DD84 FF14 FF18 GG16 5F033 HH04 HH08 HH18 HH19 HH25 HH33 HH34 JJ04 JJ18 JJ19 JJ33 KK01 KK19 MM07 MM08 MM13 PP06 PP15 QQ09 QQ25 QQ37 QQ48 QQ70 RR04 RR06 SS04 SS15 VV06 VV16 XX33 5F048 AA09 AB01 AB03 AC01 AC03 AC10 AD01 AD25 BF27 BF10 BF13 BB10 BB13 BB10 BB13 BB10 BB13 BB10 BB13 BB03 JA14 JA15 JA35 JA39 JA40 JA43 KA01 MA06 MA17 MA20 PR40 ZA12

Claims (5)

[Claims] 1. A first MI is formed in a first region of a main surface of a semiconductor substrate.
The SFET and the second M in the second region different from the first region.
A method of manufacturing a semiconductor integrated circuit device for forming an ISFET, comprising the steps of: (a) depositing a first conductor film and a second conductor film on a semiconductor substrate in order from the lower layer, and patterning the first conductor film and the second conductor film; A gate electrode of the first MISFET formed of a laminated film of the first conductor film and the second conductor film is formed in the region, and at the same time, a gate electrode of the first MISFET formed in the first region is formed in the second region. Forming a dummy gate electrode having the same structure, and (b) forming an insulating film on the semiconductor substrate, and then removing the insulating film in the second region until the second conductor film in the second region is exposed. Polishing and removing; (c) removing the second conductor film in the second region; (d) forming a silicide layer on the surface of the first conductor film in the second region; The first conductor in the area And a step of forming a gate electrode of the second MISFET made of a laminated film of a film and the silicide layer. 2. A first MI in the first region of the main surface of the semiconductor substrate.
The SFET and the second M in the second region different from the first region.
A method of manufacturing a semiconductor integrated circuit device for forming an ISFET, comprising: (a) depositing a first conductor film, a second conductor film, and a first insulating film on a semiconductor substrate sequentially from a lower layer, and patterning them. As a result, the first MISFET including a laminated film of the first conductor film and the second conductor film is formed in the first region.
And forming a dummy gate electrode having the same structure as the gate electrode of the first MISFET formed in the first region in the second region, and (b) forming a second dummy electrode on the semiconductor substrate. After forming the insulating film, polishing and removing the second insulating film until the first insulating film is exposed; (c) After forming the third insulating film on the semiconductor substrate, the second region Etching the third insulating film and the first insulating film, and (d) removing the second conductor film in the second region, and (e) the first conductor in the second region. A step of forming a silicide layer on the surface of the film, and forming a gate electrode of a second MISFET made of a laminated film of the first conductor film and the silicide layer in the second region. Method of manufacturing circuit device. 3. A first MI in the first region of the main surface of the semiconductor substrate.
The SFET and the second M in the second region different from the first region.
A method of manufacturing a semiconductor integrated circuit device for forming an ISFET, comprising: (a) forming a laminated film by sequentially depositing a silicon polycrystalline film and a refractory metal film from the lower layer on the semiconductor substrate, and further forming the laminated film. After depositing a first insulating film on the upper layer, the first insulating film and the laminated film are patterned to form a first MISF made of the laminated film in the first region.
Forming a gate electrode of ET and simultaneously forming a dummy gate electrode having the same structure as the gate electrode of the first MISFET formed in the first region in the second region, and (b) forming a dummy gate electrode on the semiconductor substrate. After forming the second insulating film, polishing and removing the second insulating film and the first insulating film in the second region until the refractory metal film in the second region is exposed; Removing the refractory metal film in the second region, and (d) forming a silicide layer on the surface of the silicon polycrystalline film in the second region by a self-alignment method, and forming a silicide layer in the second region. And a step of forming a gate electrode of the second MISFET including a laminated film of a crystal film and the silicide layer. 4. A first MI in the first region of the main surface of the semiconductor substrate.
The SFET and the second M in the second region different from the first region.
A method of manufacturing a semiconductor integrated circuit device for forming an ISFET, comprising: (a) forming a laminated film by sequentially depositing a silicon polycrystalline film, a barrier metal film, and a refractory metal film from the lower layer on the semiconductor substrate; Further, after depositing a first insulating film on the upper layer of the laminated film, the first insulating film and the laminated film are patterned to form a gate electrode of the first MISFET made of the laminated film in the first region. At the same time, in the second region, the first MISF formed in the first region
Forming a dummy gate electrode having the same structure as the ET gate electrode; and (b) forming a second insulating film on the semiconductor substrate and then exposing the refractory metal film in the second region until the refractory metal film is exposed. Polishing and removing the second insulating film and the first insulating film in a second region; (c) removing the refractory metal film and the barrier metal film in the second region; and (d) A silicide layer is formed on the surface of the silicon polycrystalline film in the second region by a self-alignment method, and a gate electrode of a second MISFET made of a laminated film of the silicon polycrystalline film and the silicide layer is formed in the second region. A method of manufacturing a semiconductor integrated circuit device, comprising: 5. The first MI is formed on the first region of the main surface of the semiconductor substrate.
The SFET and the second M in the second region different from the first region.
A method of manufacturing a semiconductor integrated circuit device for forming an ISFET, comprising: (a) forming a laminated film by sequentially depositing a silicon polycrystalline film, a barrier metal film, and a refractory metal film from the lower layer on the semiconductor substrate; Further, after depositing a first insulating film on the upper layer of the laminated film, the first insulating film and the laminated film are patterned to form a gate electrode of the first MISFET made of the laminated film in the first region. At the same time, in the second region, the first MISF formed in the first region
Forming a dummy gate electrode having the same structure as the ET gate electrode; and (b) forming a second insulating film on the semiconductor substrate and then exposing the refractory metal film in the second region until the refractory metal film is exposed. Polishing and removing the second insulating film and the first insulating film in a second region; (c) removing the refractory metal film and the barrier metal film in the second region; and (d) A silicide layer is formed on the surface of the silicon polycrystalline film in the second region by a self-alignment method, and a gate electrode of a second MISFET made of a laminated film of the silicon polycrystalline film and the silicide layer is formed in the second region. The barrier metal film is made of tungsten nitride, the refractory metal film is made of tungsten, and the silicide layer is made of cobalt silicide. Production method.