JP2003273228A - Semiconductor device and display driving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a display driving device which restrain current consumption and stabilize operation when a circuit like a shift register is constituted by using an a-SiTFT, and can improve display quality when a display driving device is constituted. <P>SOLUTION: Each transistor for constituting each stage RS (k) of a stage RS (1) to a stage RS (n) (n is a positive integer) which constitutes the shift register is formed of a thin film transistor, and Q50 is made to be a double gate structure. A prescribed voltage Vc is applied to a top gate terminal TG which voltage reduces a leakage current flowing across a drain and a source to a minimum when a 0 [V] is applied to a bottom gate terminal BG. Further, Q40 may be made to be a double gate structure, thereby enabling the restriction of the current consumption of the shift register and the stabilization of operation thereof. When the shift register is employed to the display driving device, display quality can be improved. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a thin film transistor and a display driving device using the same.

[0002]

2. Description of the Related Art Amorphous silicon TFT (Thin Film Transistor) (hereinafter referred to as "a-SiT")
FT ". ) Is used, for example, as a liquid crystal element forming each pixel of a liquid crystal display panel. The liquid crystal display panel is controlled by a gate driver and a source driver to display a desired image. Specifically, the gate driver sequentially selects and drives the a-Si TFTs that form the liquid crystal element. Then, the source driver applies a voltage corresponding to the display data to the liquid crystal capacitance which also constitutes the liquid crystal element, so that a display operation is performed and an image is displayed on the liquid crystal display panel.

In recent years, it has been studied to form various circuits by using a-SiTFT. For example, by forming a gate driver or a source driver or both of them in a display driving device by a-SiTFT, Techniques for reducing the module size and cost by integrating the driving device and the liquid crystal display panel have been developed and researched.

[0004]

However, for example, an a-Si TFT is not completely turned off even when 0 [V] is applied to the gate terminal, and has a characteristic that a leak current flows between the source and drain electrodes. . Therefore, a-Si TFT
When a display driving device is configured using the above, there is a problem that the current consumption of the circuit increases due to the leak current. Moreover, the circuit operation becomes unstable due to the leakage current, and as a result,
Inaccurate control of each liquid crystal pixel of the liquid crystal display panel,
There is a problem that the display quality is degraded.

An object of the present invention is to suppress current consumption and stabilize the operation when a circuit such as a shift register is formed of a-SiTFT, and improve the display quality when a display drive device is formed. It is to provide a semiconductor device and a display driving device which can be performed.

[0006]

In order to solve the above-mentioned problems, the invention according to claim 1 is the first invention to which an input signal is applied.
And a second transistor to which an inverted input signal is applied are connected in series, and the semiconductor device includes a first inverter circuit that outputs a predetermined output signal, the first transistor and the second transistor Is a thin film transistor, and at least the first transistor is a double-gate structure transistor having a first gate and a second gate that are arranged to face each other,
The first gate is used as a signal input terminal, and the second gate is provided with an applying means for applying a predetermined voltage for reducing a leak current when the first transistor is in an off state.

According to the invention described in claim 1, in a semiconductor device including an inverter circuit, which is formed by using thin film transistors, the first transistor has a double gate structure, and a predetermined voltage is applied to the second gate. Thus, leakage current when the first transistor is off can be suppressed, current consumption of the semiconductor device can be reduced, and circuit operation can be stabilized.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the semiconductor device further includes a second inverter which receives the input signal and outputs a signal which becomes the inverted input signal. A second gate circuit including a circuit, the second inverter circuit includes a third transistor to which the input signal is applied, and the third transistor has a double gate structure having a first gate and a second gate arranged to face each other. The first gate is a signal input terminal, and the second gate is provided with an applying means for applying a predetermined voltage for reducing a leak current when the third transistor is in an off state. I am trying.

According to the second aspect of the present invention, the circuit operation of the semiconductor device is further improved by providing the second inverter circuit and by configuring the third transistor as a double gate structure to suppress the leakage current. Can be stabilized.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, in the transistor having the double gate structure, the predetermined voltage applied to the second gate is the first gate. It is characterized in that the voltage flowing between the source and the drain of the transistor is a minimum voltage when a low level is applied to the transistor.

According to the invention of claim 3, the first,
The leakage current between the source and the drain in the off state of the double-gate structure transistor in the third transistor can be suppressed to a minimum, and the current consumption of the semiconductor device can be further reduced. The circuit operation can be further stabilized. The invention according to claim 4 is the semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is a shift register circuit, and one of the first transistors of the first inverter circuit is included. The side terminal is connected to the clock signal input terminal, and outputs the output signal based on the input signal according to the clock signal.

According to the invention described in claim 4, when the shift register circuit is formed by using the thin film transistors, it is possible to reduce current consumption of the shift register circuit and obtain stable circuit operation.

Further, a fifth aspect of the present invention comprises a shift register having a plurality of stages, each stage having the semiconductor device according to any one of the first to fourth aspects, and is provided in accordance with the clock signal. The display panel is driven by applying the output signal output from each stage to the scanning line of the corresponding display panel.

According to the fifth aspect of the present invention, when the display driving device is configured by using a plurality of stages of shift registers configured by using thin film transistors, the operation of the display driving device can be stabilized. The display quality of the display panel can be improved.

[0015]

DETAILED DESCRIPTION OF THE INVENTION A semiconductor device according to the present invention will be described in detail below. Note that, in the embodiments shown in FIGS. 1 to 13, as an example, a case where a shift register circuit is configured by a semiconductor device and a display driving device is configured by this and is applied to a liquid crystal display device will be described. First, FIG. 1 is a block diagram showing a configuration of a liquid crystal display device. The liquid crystal display device includes a liquid crystal display panel 11, a gate driver 12, and a source driver 13.

In the liquid crystal display panel 11, gate lines GL1, GL2, ... (Comprehensively referred to as "gate lines GL" hereinafter) extended in the row direction and data lines DL1 extended in the column direction. , DL2, ... (Hereinafter, collectively referred to as “data line DL”), the liquid crystal display element 111 is provided. The liquid crystal display element 111 includes a TFT 112 and a pixel capacitor 113. The gate terminal of each TFT 112 is connected to the gate line GL, and the source terminal is connected to the data line DL. The pixel capacitor 113 is the TFT 11
A pixel electrode connected to the second drain terminal and a liquid crystal sandwiched between counter electrodes facing the pixel electrode. A plurality of liquid crystal display elements 111 are arranged in a matrix to form a liquid crystal display panel 11.

A gate driver 12 which is a display driving device.
Is equipped with a shift register 121 and has a start signal Vst
Is input, the start signal Vst is sequentially shifted according to the input signals of the clock signals CK1 and CK2,
Scan signals are sequentially output to the gate line GL. This allows
The TFTs 112 connected to each gate line GL are sequentially turned on.

Although not shown, the source driver 13 converts the input display data into a gradation voltage and outputs it as a display data signal to the data line DL. The TFT 1 is driven by the scanning signal output from the gate driver 12.
When 12 is turned on, the display data signal is TFT
An image display operation is performed by being supplied to the pixel capacitor 113 via 112.

FIG. 2 is an example of a circuit configuration diagram of the shift register 121 constituting the gate driver 12. In the shift register 121, when the number of gate lines GL is n (n is a positive integer), there are n stages RS formed of shift circuits.
(1) to RS (n).

Each stage RS (k) (k is an integer from 1 to n) is
It has an input signal terminal IN, an output signal terminal OUT, a clock signal terminal CK, and a reset signal terminal RST. Step R
A start signal Vst is input to the input signal terminal IN of S (1) from an external circuit (not shown) such as a controller circuit. The output signal terminal OUT of the previous stage RS (k-1) (k is an integer of 2 to n) is connected to the input signal terminals IN of the stages RS (2) to RS (n), and the output signal out
(K-1) is input respectively.

The output signal terminal OUT is an output signal out.
(K) is output to each gate line GL.

The clock signal terminal CK has an odd number of stages RS.
The clock signal CK1 is input to (k), and the clock signal CK2 is input to the even-numbered stages RS (k) from an external circuit. The clock signals CK1 and CK2 are synchronization pulse signals,
The drive level of the stage RS (k) alternates. Last stage RS
The output signal terminal OUT of the next stage RS (k + 1) (k is an integer of 1 to n−1) is connected to the reset signal terminal RST of the stage RS (k) other than (n), and the output signal out (k +
1) (k is an integer from 1 to n-1) is input.
A signal is input from an external circuit to the reset signal terminal RST of the stage RS (n).

FIG. 3 shows each stage RS of the shift register 121.
It is an example of a specific circuit configuration of (k). Step RS (k)
Is the clock signal C input to the clock signal terminal CK
According to K1, it has a function of outputting a signal input to the input signal terminal IN to the output signal terminal OUT and a function of resetting the output by the signal input to the reset signal terminal RST, and It is composed of an inverter circuit. Further, Q1 to Q6 in FIG. 3 are composed of N-type a-Si TFTs (hereinafter collectively referred to as “TFT Q”).

In FIG. 3, the drain terminal D and the gate terminal G of Q1 are connected to the input signal terminal IN. Q
The drain terminal D of 2 is connected to the source terminal S of Q1, and the gate terminal G is connected to the reset signal terminal RST. The voltage Vss (low potential) is applied to the source terminal S. The voltage Vdd (high potential) is applied to the drain terminal D and the gate terminal G of Q3 (third transistor). The drain terminal D of Q4 is the source terminal S of Q3.
, And the gate terminal G is connected to the source terminal S of Q1. The voltage Vss is applied to the source terminal S. The drain terminal D of Q5 is a clock signal terminal CK
, And the gate terminal G is connected to the source terminal S of Q1. The source terminal S is connected to the output signal terminal OUT. The drain terminal D of Q6 (second transistor) is connected to the output signal terminal OUT, and the gate terminal G is connected to the source terminal S of Q3. And the source terminal S
Is applied with a voltage Vss.

The capacitance A is the source terminal S of Q1 and Q4, Q.
Wiring with the gate terminal G of 5 and Q1, Q4, Q5
Is the capacitance formed by the parasitic capacitance of
3 is the capacitance formed by the wiring between the source terminal S of 3 and the drain terminal of Q4, the gate terminal G of Q6, and the parasitic capacitance of Q3, Q4, and Q6. First, the structure and characteristics of the TFT Q will be described, and then the circuit operation of the stage RS (k) will be described.

FIG. 4 shows a TFT which constitutes each stage RS (k).
It is sectional drawing which shows the structure of Q. TFTQ is a glass substrate 4
1, gate electrode 42, gate insulating film 43, semiconductor film 4
4, a channel protection film 45, an impurity semiconductor film 46, a source electrode 47, and a drain electrode 48, which are laminated. The gate electrode 42 is formed on the glass substrate 41, and the gate insulating film 43 is formed so as to cover the gate electrode 42. A semiconductor film 44 is formed on the gate insulating film 43, and a channel protective film 45 is formed on the semiconductor film 44. Then, the impurity semiconductor film 46 is formed so as to cover the semiconductor film 44 from both ends of the channel protective film 45.
Is formed. A source electrode 47 is formed on one impurity semiconductor film 46, and a drain electrode 48 is formed on the other impurity semiconductor film 46.

FIG. 5 is a circuit diagram for measuring the VG-ID characteristic of the TFTQ. The TFT 51 is an N-type a-SiTF having the same structure and characteristics as the TFT Q shown in FIG.
T. The positive terminal of the variable power source 52 (VG) is connected to the gate terminal G of the TFT 51, and the negative terminal of the power source 52 is grounded. The drain terminal D of the TFT 51 is connected to one end of an ammeter 53, and the other end of the ammeter 53 is connected to the + pole of a power supply 54. The negative terminal of the power supply 54 and the source terminal S of the TFT 51 are grounded. Then, the drain current ID flowing through the TFT 51 is measured by the ammeter 53 when the supply voltage of the power source 52 is gradually increased from the negative voltage.

FIG. 6 is a diagram showing the VG-ID characteristics of the TFT 51 measured using the circuit diagram shown in FIG.
The horizontal axis represents the voltage VG applied to the gate terminal, and the vertical axis represents the logarithm of the drain current ID.

For example, N-type MOS made of single crystal silicon
In the case of an FET, as is well known, when VG is 0 [V] or less, the drain current ID becomes minute and does not substantially flow. Then, when VG is increased from 0 [V], the drain current ID is generated, and the current value is increased to V
When G exceeds a certain value, the drain current ID is saturated and becomes a substantially constant current.

On the other hand, a TFT which is an a-Si TFT
Similarly, 51 has the characteristic that when VG is increased from 0 [V], the drain current ID is also increased, and VG is saturated above a certain value to become a substantially constant current.
The drain current ID is not minimum when VG is 0 [V], and the drain current ID flows to some extent even when VG is 0 [V] or less. Then, VG is a voltage V of 0 [V] or less.
The drain current ID has the minimum value ID1 when G '[V], and the drain current increases conversely when VG further decreases. Here, the drain current ID when VG = 0 [V] is ID2.

Thus, even if VG is 0 [V], T
Since the drain current ID = ID2 flows through the FT51,
The TFT 51 is not turned off sufficiently. That is, dan RS
The TFT Q constituting (k) has 0 [V] at the gate terminal G.
Is not sufficiently turned off even if is applied, the signal supplied to the drain terminal D is output to the source terminal S side to some extent. As a result, the shift register 121
Operation becomes unstable, the control of the liquid crystal display element 111 of the liquid crystal display panel 11 becomes inaccurate, and this causes the deterioration of display quality. Furthermore, 0 to the gate terminal G of the TFT
Even when [V] is applied, since the drain current ID = ID2 flows through the TFT as a leak through current, there is a problem that the current consumption of the shift register 121 increases.

Next, FIG. 7 shows an operation timing chart of the shift register 121 constituted by each stage RS (k) shown in FIG. In the description, the stages RS (1) to RS (4) will be described as an example, and at the same time, the circuit operation of the stage RS (k) shown in FIG. 3 will be described.

First, in cycle 1, an odd number of stages RS
The “Hi” level signal is input to (k) as the signal CK1, and the “Low” level signal is input to the even-numbered stages RS (k) as the signal CK2. At this time, since the signal Vst is at the "Low" level, Q1 is in the off state and therefore Q4 is also in the off state. The output signals out (k) are all "Low".
Since it is at the level, Q2 is also in the off state.

Since the voltage Vdd is applied to the gate terminal G, Q3 is always on. Since Q3 is in the ON state and Q4 is in the OFF state, the capacitor B is in the charging state,
Q6 is on.

Here, since the capacitance A is not charged because Q1 is off, it is ideal that Q5 is off. However, as the characteristics shown in FIG.
Even if 0 [V] is applied to the gate terminal G, TQ is not completely turned off, and a leak current is generated. Therefore, in the odd-numbered stages RS (k), a weak signal level is output via the Q5, such as the signal P1a of the signal out (1) which is the output signal of the stage RS (1). k is 1
Is output as an odd number of n).

Next, when the signal Vst becomes "Hi" level, the signal CK1 becomes "Low" level, and the signal CK2 becomes "Hi" level, Q1 is turned on and the capacitor A is charged. As a result, Q4 and Q5 are turned on. Q
When 4 is turned on, the capacitor B is discharged and Q6 is turned off. Further, a weak signal level P1b as an output signal out (2) is input to the gate terminal G of Q2 from the next stage, but it does not reach the ON state of Q2, and Q2
Remains off. Although Q5 is in the ON state, the signal CK1 is at the "Low" level, so the output signal ou
t becomes the "Low" level.

Then, as described above, the signal C is generated in all even stages RS (k) due to the leakage current of Q5.
In response to the “Hi” level of K2, a weak signal level such as the signal P1b is output by the signal out (k) (k is 1 to n).
Is output as an even number.

Then, in cycle 2, the signal CK1 goes to "Hi" level, and the signals CK2 and Vst go to "Low" level. At this time, Q1 is turned off, but the capacitor A (1) maintains the charged state. Therefore, Q5
Is also in the ON state, the “Hi” level of the signal CK1 is output as the output signal out1 via Q5. At the same time, in response to the “Hi” level of the signal CK1, the stage RS
A weak signal level P2a is output as a signal out (k) (k is an odd number from 1 to n) from the odd-numbered stages RS (k) except (1).

The signal out (1) is sent to the next stage RS.
It is input to the input signal terminal IN of (2). Therefore, in the next stage RS (2), Q1 is turned on and the capacitance A
Is charged. Then, Q4 and Q5 are turned on.

Next, when the signal CK1 is at the "Low" level and the signal CK2 is at the "Hi" level, the capacitor A is in the charged state, so that Q5 is in the ON state, and the "Hi" level of the signal CK2 is the signal. It is output as out (2).
At the same time, in response to the “Hi” level of the signal CK2, the stage RS
The weak signal level P2b is output as the signal out (k) (k is an even number from 1 to n) from the even-numbered stages RS (k) except (2).

Then, the signal out (2) is sent to the next stage RS.
The signal is input to the input signal terminal IN of (3) and the reset terminal RST of the previous stage RS (1). That is, Q2 of the stage RS (1)
Is turned on and the capacitor A is discharged. Also, the RS
Q1 in (3) is turned on and the capacitor A is charged. This turns off Q4 and Q5 of stage RS (1). Then, Q4 and Q5 of the stage RS (3) are turned on, and the signal CK1 becomes "H" in cycle 3.
At the i "level, the output signal out (3) also becomes" Hi ".
It becomes a level. At the same time, an odd number of stages R except the stage RS (3)
From S (k), a weak signal level P3a is output signal o
It is output as ut (k) (k is an odd number from 1 to n).

As described above, each stage RS (k) has the signal Vs.
After the pulse of "Hi" level is applied as t,
Pulses are sequentially output from each stage RS (k) in synchronization with the signals CK1 and CK2. However, even when the output of each stage RS (k) should be originally at the “Lo” level, that is, even when the capacitance A is in the discharged state and 0 [V] is applied to the gate terminal G of Q5, Since Q5 is not completely turned off, signals of weak levels such as the signals P1a and P1b are output in synchronization with the signals CK1 and CK2.

The output signal out of each stage RS (k)
(K) is input to the gate terminal G of the TFT 112 via the gate line GL of the liquid crystal display panel 11. Therefore, at the timing different from the original scanning signal, the signal P1
By inputting a signal such as a to the gate terminal G of the TFT 112, the liquid crystal display element 111 is slightly driven at the timing when the liquid crystal display operation should not be performed, thereby disturbing the displayed image and displaying quality. The problem arises that

Therefore, the present invention is characterized in that a thin film transistor having a double gate structure and minimizing a leak current is used for the TFTQ of each stage RS (k).

The double gate structure and characteristics will be described below, and then the operation of the shift register 121 when using a TFT to which this structure is applied will be described.

FIG. 8 is a sectional view of a TFT having a double gate structure. The double gate structure has a configuration in which a top gate electrode 82 which is a first gate and a bottom gate electrode 42 which is a second gate are arranged to face each other with the semiconductor film 44 and the channel protective film 45 interposed therebetween. The cross-sectional view shown in FIG. 8 is the same as the cross-sectional view shown in FIG.
1 and a top gate electrode 82 are added,
The bottom gate electrode 42 is substantially the same as the gate electrode 42 in FIG. Here, the same components as those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

The interlayer insulating film 81 is composed of the channel protective film 45,
It is formed so as to cover the source electrode 47 and the drain electrode 48. Then, the top gate electrode 82 is formed on the channel protection film 45 via the interlayer insulating film 81.

FIG. 9 is a circuit diagram for measuring the VG-ID characteristic of the TFT 91. The TFT 91 is an N-type a-Si TFT having the double gate structure shown in FIG.
The circuit diagram shown in FIG. 9 is obtained by adding a top gate terminal TG to the circuit diagram shown in FIG. Therefore, the same components as those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

Top-bottom gate terminal BG of TFT 91
Is connected to the positive pole of the variable power source 52 (VG), and the negative pole of the power source 52 is grounded. And the top gate terminal T
A negative voltage 92 (Vc) is applied to G. Then, the drain current ID flowing when the supply voltage of the power supply 52 is gradually increased from the negative voltage is measured by the ammeter 53.

FIG. 10 is a diagram showing the VG-ID characteristic of the TFT 91 measured using the circuit diagram shown in FIG. The horizontal axis represents the voltage VG applied to the bottom gate terminal BG,
The vertical axis represents the logarithm of the drain current ID. Also,
The characteristic is shown when the voltage VTG of the top gate terminal TG is changed according to the value of the negative voltage Vc applied to the top gate terminal TG.

In the VG-ID characteristic shown in FIG. 10, V
When TG is set to 0 [V], the VG-ID characteristics of the TFT 51 shown in FIG. 6 are substantially the same. Then VTG
When the value of is increased to the negative voltage side (0 → Vc '→
Vc) The value of the gate voltage VG when the drain current ID reaches the minimum value ID1 shifts in the positive direction. This is because the voltage Vc applied to the top gate electrode 82 when applied to the bottom gate electrode 42 acts on the semiconductor film 44, and the voltage Vc is a negative voltage, so that the voltage Vc is almost equal to the voltage Vc.
This is because the voltage obtained by subtracting the voltage Vc from G acts on the semiconductor film 44. Therefore, the top gate terminal TG
The characteristics of the TFT 91 shift according to the voltage Vc applied to the.

Therefore, the voltage Vc applied to the top gate terminal TG is set to 0 at the bottom gate terminal BG of the TFT 91.
The drain current ID that flows when [V] is applied is set to a voltage value that is the minimum value ID1. This allows the TFT
It is possible to minimize the leak current when 0 [V] is applied to the bottom gate terminal BG 91.

Next, in the circuit of the stage RS (k) shown in FIG. 3, Q5 is Q50 having the same characteristics as the TFT 91.
FIG. 11 shows a circuit diagram when it is replaced with the (first transistor). 11, parts that are the same as the components of the circuit shown in FIG. 3 are given the same reference numerals, and detailed description thereof will be omitted.

Here, the top gate terminal TG of the double-gate structure Q50 has "Lo" at the bottom gate terminal BG.
The voltage Vc is always applied so that the drain current ID flowing when the w ″ level is input is minimized. The bottom gate terminal BG of Q50 is an input signal line Q1.
Source terminal S of is connected. Although not shown, the voltage Vc is supplied from a power supply circuit inside the gate driver 121 or a power supply circuit outside the liquid crystal display device, and is always applied as a constant voltage to the top gate terminal TG of Q50.

FIG. 12 is an operation timing chart of the shift register 121 using the stage RS (k) shown in FIG. Here, only the differences from the operation timing chart shown in FIG. 7 will be described.

As shown in FIG. 12, in FIG.
The low signal level P1a or the like generated in the output signal out (k) when the "Low" level is input to the gate terminal G and the pulse of the signal CK1 or CK2 is input to the drain terminal D is Q50. It disappears by adopting a double gate structure. This is because by applying a predetermined voltage Vc to the top gate terminal TG of Q50,
This is because the leak current that flows when the “Low” level is input to the gate terminal G is minimized. As a result, it is possible to prevent the generation of the weak signal level P1a or the like that is caused by the leak current.

Further, in the circuit of the stage RS (k) shown in FIG. 11, the output signal terminal OUT is an inverter formed by connecting Q50 and Q6 in series. Here, when Q50 is off and Q6 is on, the output signal o
ut becomes the "Low" level, but in order for this "Low" level to be sufficiently lowered to the potential of the voltage Vss, Q6
Must be in a sufficient on state.

Therefore, as shown in FIG. 13, Q4 in the circuit of FIG. 11 is replaced with Q40 having a double gate structure which is the second transistor, so that Q6 can be sufficiently turned on.

That is, in FIG. 11, when a "Low" level is input to the gate terminal G of Q4, and Q4 is not in a sufficiently off state and a leak current flows,
The electric charge charged in the capacitor B is gradually discharged by the leak current. Then, the voltage "Hi" at the gate terminal G of Q6
As it drops from the level, it will not be fully turned on. As a result, the “Low” level of the output signal out does not drop to the potential of the voltage Vss, and the signal input to the gate line GL becomes unstable. This becomes a cause of impairing the display quality of the liquid crystal display panel 11.

Therefore, as shown in FIG. 13, Q4 is replaced with Q40 (fourth transistor) having a double gate structure, and like Q50, the bottom gate terminal B of Q40 is replaced.
A predetermined voltage Vc that minimizes the drain current ID that flows when the "Low" level is input to G is applied to the top gate terminal TG. As a result, the state of Q40 when the "Low" level is input to the bottom gate terminal of Q40 becomes a sufficiently off state, and the charged state of the capacitor B can be maintained. Therefore, Q6 is sufficiently turned on, and the stable "Low" level of the output signal out is set to the voltage Vss.
It is possible to reduce the potential to the potential of and to supply a stable signal to the gate line GL.

The top gate electrode of Q40 has Q
Similar to 50, the voltage Vc that always minimizes the drain current ID that flows when the “Low” level is input to the gate terminal G is constantly applied.

In this way, Q40 and Q50 have a double-gate structure, and by applying a predetermined voltage to the top gate terminal TG, 0 is applied to each bottom gate terminal BG.
The leak current when [V] is applied can be minimized. As a result, the current consumption of the shift register 121 can be reduced.

Furthermore, since an accurate and stable signal can be supplied from the shift register 121 to the gate line GL, erroneous display on the liquid crystal display panel 11 can be prevented and a liquid crystal display device with good display quality can be realized.

In the above embodiment, Q40 and Q50 are transistors having a double gate structure, but the present invention is not limited to this, and further other transistors or all the transistors have a double gate structure. Alternatively, a predetermined voltage may be applied to the top gate terminal TG of each transistor to suppress the leak current when the transistor is off. As a result, the current consumption of the shift register 121 can be further reduced and the display quality can be further improved.

The semiconductor device of the present invention can be suitably applied to the display driving device as described above.
Needless to say, the present invention is not limited to this, and can be suitably applied to various digital circuits, for example, logic circuits such as AND circuits and OR circuits, counter circuits, decoder circuits, and the like.

[0066]

According to the first aspect of the invention, in a semiconductor device including an inverter circuit, which is formed by using thin film transistors, the first transistor has a double gate structure and a predetermined voltage is applied to the second gate. By doing so, it is possible to suppress the leak current when the first transistor is in the off state, reduce the current consumption of the semiconductor device, and stabilize the circuit operation.

According to the second aspect of the present invention, the second inverter circuit is provided, and the third transistor has a double gate structure so as to suppress the leak current, thereby further stabilizing the circuit operation of the semiconductor device. Can be made.

According to the invention of claim 3, the first and third aspects are provided.
In this transistor, the leak current between the source and drain of the double-gate structure transistor in the off state can be suppressed to a minimum, and the current consumption of the semiconductor device can be further reduced, and the circuit operation of the semiconductor device can be further reduced. Can be further stabilized.

According to the fourth aspect of the invention, when the shift register circuit is formed by using the thin film transistors, it is possible to reduce the current consumption of the shift register circuit and obtain a stable circuit operation.

According to the fifth aspect of the invention, when the display driving device is configured by using a plurality of stages of shift registers configured by using thin film transistors, the operation of the display driving device can be stabilized, The display quality of the display panel can be improved.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a liquid crystal display device.

FIG. 2 is a circuit configuration diagram of a shift register.

FIG. 3 is a circuit diagram of a shift register stage RS (k).

FIG. 4 is a cross-sectional view of an N-type a-Si TFT that constitutes a step RS.

FIG. 5 is a circuit diagram for measuring VG-ID characteristics of N-type a-Si TFTs.

FIG. 6 is a diagram showing VG-ID characteristics of an N-type a-Si TFT.

7 is an operation timing chart of the shift register shown in FIG.

FIG. 8 is a sectional view of an N-type a-Si TFT having a double gate structure.

9 is a circuit diagram for measuring VG-ID characteristics of the N-type a-Si TFT shown in FIG.

10 is a VG-ID of the N-type a-Si TFT shown in FIG.
The figure which showed the characteristic.

FIG. 11 is a circuit diagram of a stage RS (k) according to the present embodiment.

FIG. 12 is an operation timing chart of the shift register of this embodiment.

FIG. 13 is an operation timing chart of the shift register of this embodiment.

[Explanation of symbols]

11 LCD display panel 111 Liquid crystal display element 112 TFT 113 pixel capacity 12 Gate driver 121 shift register 13 Source driver 41 glass substrate 42 Gate electrode 43 Gate insulating film 44 Semiconductor film 45 channel protective film 46 Impurity semiconductor film 47 Source electrode 48 drain electrode 81 Interlayer insulation film 82 Top gate electrode

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/786 H01L 29/78 614 H03K 19/0948 613Z H03K 19/094 BF term (reference) 5C006 AF75 BB16 BC03 BF03 BF26 BF27 BF34 EB05 FA36 FA47 5C080 AA10 BB05 DD26 DD30 FF11 JJ02 JJ03 JJ04 JJ05 JJ06 5F038 AV06 CD04 CD06 DF01 EZ06 EZ20 5F110 AA06 AA09 BB02 BB03 CC07 DD02 EE30 GG02 GG15 NN12 5J056 AA05 BB17 BB49 CC01 CC18 DD29 DD52 EE06 FF07 FF08 GG09 KK03

Claims (5)

[Claims] 1. A semiconductor device including a first inverter circuit to which a first transistor to which an input signal is applied and a second transistor to which an inverted input signal is applied are connected in series and which outputs a predetermined output signal. In, the first transistor and the second transistor are thin film transistors, and at least the first transistor is
A double-gate structure transistor having a first gate and a second gate arranged to face each other, wherein the first gate serves as a signal input terminal, and the second gate has an off state when the first transistor is in an off state. 6. A semiconductor device comprising: an applying unit that applies a predetermined voltage that reduces the leak current of the semiconductor device. 2. The semiconductor device further includes a second inverter circuit to which the input signal is applied and which outputs a signal which becomes the inverted input signal, and the second inverter circuit is applied with the input signal. Equipped with a third transistor
The third transistor is a transistor having a double gate structure having a first gate and a second gate which are arranged to face each other, and the first gate serves as a signal input terminal, and the second gate has the third gate. The semiconductor device according to claim 1, further comprising an applying unit that applies a predetermined voltage that reduces a leak current when the transistor is in an off state. 3. In the double-gate structure transistor, the predetermined voltage applied to the second gate is
3. The semiconductor device according to claim 1, wherein when the low level is applied to the first gate, the voltage is such that the current flowing between the source and the drain of the transistor is a minimum. 4. The semiconductor device is a shift register circuit, wherein one side terminal of the first transistor of the first inverter circuit is connected to a clock signal input terminal,
4. The semiconductor device according to claim 1, wherein the output signal based on the input signal is output according to the clock signal. 5. A shift register having a plurality of stages, each stage having the semiconductor device according to claim 1, wherein the output is output from each stage according to the clock signal. A display drive device characterized in that a display panel is driven by applying a signal to a scan line of a corresponding display panel.