JP2003272930A - Laminated chip and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated chip and its manufacturing method by which the manufacturing step can be simplified and the manufacturing unit cost be also reduced. <P>SOLUTION: A terminal electrode pattern and a required component element pattern is coated with a silver paste on respective lamination members (S1), and the respective lamination members are laminated (S2). Then, the laminated lamination members are diced and baked to form a laminated chip (S3). Next, an external electrode formation part is plated twice by nickel (S4). At first plating, the external electrode formation part is formed as shown in Fig. 2 (A), and at second plating, one surface thereof is covered with a plating layer as shown in Fig. 2 (B). Then, a tin plating is applied by a specified thickness on the nickel-plated external electrode (S5) to complete a laminated chip. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer chip component having a multilayer structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a conventional multilayer chip component, when forming an external electrode, first, a conductive paste to be the external electrode is applied after firing of the chip component body, and further baked to form an external electrode pattern, and thereafter. The formed external electrode pattern was plated to form an external electrode.

[0003]

However, in the conventional method, in order to form the external electrodes, the coating process and the firing process must be performed separately from the manufacturing process of the chip component body (multilayer chip component). However, the manufacturing process was complicated and costly.

Further, in the case of the laminated chip part, the firing process at the time of forming the external electrodes has to be performed even though the influence of heat cannot be ignored, and the adverse effect has been a problem.

[0005]

The present invention has been made for the purpose of solving the above-mentioned problems.
An object of the present invention is to provide a laminated chip component and a manufacturing method thereof, which eliminates a coating step for forming external electrodes, eliminates a firing step, reduces manufacturing costs, and does not adversely affect the laminated chip body due to overheating. Then, for example, the following configuration is provided as one means for achieving the object and solving the problems described above.

That is, a laminated chip is formed by forming a conductive portion on at least an end of the external electrode forming portion of each laminated member of the laminated chip component and then laminating the laminated members on which the conductive portion is formed. It has an external electrode formed by plating the external electrode forming portion of the laminated member.

Further, for example, the conductive portion is formed by applying a conductive paste, and the respective laminated members are formed into a laminated chip by laminating and firing after forming the conductive portion.

Further, for example, the external electrode forming portion of the laminated multilayer chip portion is characterized by performing multi-layer plating to electrically connect the conductive portions of the laminated members in the laminated state. Alternatively, the multilayer plating is characterized in that at least nickel plating is performed and then tin plating is further performed.

Further, for example, the laminated member is a ceramic material, and is made of an insulating material, a dielectric material, a magnetic material, or the like.

Alternatively, a conductive pattern portion necessary for each laminated member of the laminated chip component is formed with a conductive portion for an external electrode at least at an end portion of the external electrode forming portion, and the laminated members having the conductive portion are laminated and laminated. A method of manufacturing a laminated chip component, which is in the form of a chip and in which an external electrode forming portion of the laminated chip is plated to form an external electrode.

Further, for example, the conductive portion is a method for manufacturing a laminated chip component in which a conductive paste is applied to form a laminated chip and necessary laminated members coated with the conductive paste are laminated and fired to form a laminated chip. Is characterized by.

Further, for example, the manufacturing of a laminated chip component in which the external electrodes are formed by multi-layer plating the external electrode forming portions of the laminated laminated chip members to electrically connect the conductive portions of the laminated members. It is a method.

Further, for example, the multilayer plating is characterized in that it is a method for manufacturing a multilayer chip component in which at least nickel plating is performed and then tin plating is further performed.

[0014]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram for explaining a laminated state of a laminated member of a laminated chip part according to an embodiment of the present invention, and FIG. 2 is for explaining an external electrode forming process of the embodiment. FIG. 3 is a flow chart for explaining the method of manufacturing the laminated chip component of the present embodiment, and FIG. 4 is a diagram showing an example of a completed chip component.

In this embodiment, an example applied to a multi-layer (laminated type) reactance component will be described. However, it goes without saying that it can be applied to all laminated chip components that require external electrodes. For example, it can be directly applied to various chip-type components such as a chip-type BPF, a chip-type resistor, and a chip-type fuse.

First, referring to FIG. 1, the structure of the laminated chip component of this embodiment before the external electrodes are formed will be described. In the following description, a case where eight rectangular laminated members are laminated to manufacture a component and external electrodes are formed on the side surfaces on the short side will be described as an example. However, the shape, the number of stacked layers, and the surface on which the external electrodes are formed are examples, and the present invention is not limited to the examples described below.

In FIG. 1, reference numeral 1 denotes a first-layer laminated member, and conductive pastes (for example, silver paste) 1a and 1b having a predetermined width are applied to both short sides of the front surface to form an external electrode pattern. The eighth layer (lowermost layer) of the laminated member 8 also has an external electrode pattern of the same shape formed at the same position as the first layer laminated member 1 on the surface on the front surface side of the laminated chip component.

Reference numeral 2 denotes a second-layer laminated member, and the first layer has a U-shape that is slightly narrower than the length of the conductive paste of the first-layer laminated member on both short sides to the long side. An end conductive pattern is formed by applying a conductive paste similar to the above. This end conductive pattern is applied to the third-layer conductive member 3 to the seventh-layer conductive member 7 by applying a conductive paste of the same shape at substantially the same position as that of the second-layer laminated member and similar end portions. Electrode patterns (3a, 3b; 4a, 4b; 5a, 5b; 6a,
6b; 7a, 7b).

Second layer laminated member 2 and seventh layer laminated member 7
No pattern is formed on the inside of the end conductive pattern, and the structure is almost the same. On the other hand, internal conductive patterns (3c, 4c, 5c, 6c) necessary for the chip structure are formed of a predetermined material on the third layer laminated member 3 to the sixth layer laminated member 6. In this example, since it is a reactance component, a conductive pattern is formed, and for example, the pattern can be formed with the same conductive paste (silver paste) as the conductive paste forming the end conductive pattern. Therefore, in this case, the formation of the end conductive pattern and the conductive pattern for component construction can be performed by applying the conductive pattern once in the same step. Therefore, the end conductive pattern can be formed in the same process as the conventional process.

The circles at the ends of the conductive patterns for component construction in the third-layer stacking member 3 to the sixth-layer stacking member 6 are through-hole forming portions, and in this portion, for the component construction of adjacent stacking members. It electrically connects to the end of the conductive pattern.

In this way, the laminated member on which the conductive pattern for component construction and the end conductive pattern are formed are laminated, diced, and then fired to form a laminated chip. In the present embodiment, for example, as shown in FIG. 2, multilayer plating is applied to the short-side surface of the laminated members, and then T is formed.
Form external electrodes.

The short side surface of the laminated members in the laminated state is
A part of the end conductive pattern is exposed at the stacking boundary portion of the stacking member. For example, a thickness of 20 μm to 30 μm
The laminated member layers and the end conductive pattern layers having a thickness of several μm or less are alternately arranged.

Each laminated member is formed into a sheet shape, and is made of, for example, a ceramic material including an insulating material, a dielectric material, and a magnetic material.
A dielectric green sheet or a ceramic green sheet is used. The material is not limited to this material as long as it can meet the requirements of chip components.

The end portion is directly or after being subjected to surface treatment such as surface polishing, first, metal plating (for example, nickel plating) of the first layer is performed. A state in which the first layer is plated is shown in FIG. In FIG. 2A, C is an end conductive pattern portion, and 50 is a first layer plated portion.

Subsequently, a second layer is plated with the same metal,
The plating layer is made thicker so that the end portion electrode pattern C of each layer of the laminated member
Make sure that a plating layer is formed between them. A state in which the plating of the second layer is performed is shown in FIG. Reference numeral 60 in FIG. 2B is a plated layer obtained by plating up to the second layer. It should be noted that in the above description, two layers are plated and the plating layer 6 is
Although 0 was formed, if it is possible to secure a sufficient thickness with one plating, it is sufficient to perform only once, and conversely, if the thickness is made thicker, the plating should be performed three times or more as many times as necessary. I'll do it.

Then, after that, tin plating is further performed on the surface to complete the external electrode formation. The state after the tin plating is shown in FIG. In FIG. 2C, reference numeral 70 denotes a tin plating layer on the surface. The plating layer 60 may be thick enough to close the space between the end electrode patterns, and the tin plating layer may be formed thick. In this case, the thick plating layer can be formed easily and inexpensively.

For example, when a green ferrite sheet is used, ferrite generally has a smaller insulation resistance value as compared with a dielectric or the like, and the plating is easy to stretch. By making use of this feature, the external electrodes connecting the end electrodes can be easily formed only by plating using the exposed portion of the end electrode pattern portion on the laminated member as a trigger.

In the above description, an example of forming the external electrode by plating has been described, but the method is not limited to plating as long as it is a method capable of forming a conductive layer without including a heating step (firing step). For example, it may be formed by vapor deposition.

The method of manufacturing the layered chip component of the present embodiment described above will be described below with reference to the flowchart of FIG.

First, in step S1, as shown in FIG. 1, a conductive paste, for example, a silver paste, is applied to each end member pattern forming portion on each laminated member (ceramic material green sheet). Similarly, a constituent element pattern for realizing the function of the chip component is applied to a necessary formation site. When forming a reactance element, for example, it is necessary to form a spiral conductive pattern. Therefore, for example, the same metal paste (for example, silver paste) as the end electrode pattern portion is used as a conductive pattern in a pattern shape unique to each laminated member. Apply to the site. That is, in the case of FIG. 1, all the necessary conductive patterns can be applied by one application, and the work load hardly increases.

Then, in step S2, step S
The laminated members coated with the electrode patterns and the like in 1 are laminated. Then, in step S3, the laminated members laminated are diced and fired to form laminated chips. In this state, for example, the end portion of the end electrode pattern is exposed on the side surface of one side as shown in FIG. 2 described above.

Next, in step S4, the external electrode forming portion is divided into two parts and nickel-plated. As described above, the first plating is performed as shown in FIG. 2A, and the second plating is performed to cover one surface of the external electrode forming surface with the plating layer as shown in FIG. 2B. State.

Then, in step S5, the external electrode portion plated with nickel is further plated with tin to a predetermined thickness. For example, the state shown in FIG. FIG. 4 shows an appearance example of the laminated chip component thus completed.

After manufacturing the laminated chip component in this manner,
In step S6, it is inspected whether or not the product has the characteristics within the standard, and when the standard is satisfied, the product is completed.

As described above, according to the present embodiment, the metal paste coating step for forming the external electrodes and the subsequent firing step, which have been conventionally required, are not required, so that the manufacturing method is simplified. It is possible to reduce the production unit price as well as to reduce the cost.

Furthermore, since the firing process for the external electrodes can be omitted, it is possible to eliminate the influence on the chip characteristics due to the heating of the laminated chip portion due to the firing process.

In the above description, the laminated members 1 and 8 of the first layer and the eighth layer and the laminated members 2 and 7 of the second layer and the seventh layer have different structures. A laminated member 2 of the seventh layer,
Alternatively, any one of the laminated members 1 or 8 of 7 or the first layer and the large 8 layers may be omitted.

[0039]

As described above, according to the present invention, the manufacturing process is simplified, which does not require the metal paste coating process for forming the external electrodes and the subsequent firing process which are conventionally required. It is possible to provide a laminated chip component and a method for manufacturing a laminated chip component that can reduce the manufacturing unit price.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a laminated state of a laminated member of a laminated chip component according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a process of forming external electrodes according to the present embodiment.

FIG. 3 is a flowchart for explaining a method of manufacturing a layered chip component according to the present embodiment.

FIG. 4 is a diagram showing an example of a chip component completed state according to the present embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 1st layer laminated member 1a, 1b, 8a, 8b Conductive paste (external electrode pattern) 2 2nd layer laminated member 3 3rd layer laminated member 4 4th layer laminated member 5 5th layer laminated member 6 Sixth layer laminated member 7 Seventh layer laminated member 8 Eighth layer laminated member 3a, 3b; 4a, 4b; 5a, 5b; 6a, 6b; 7
a, 7b end electrode pattern 3c, 4c, 5c, 6c internal conductive pattern 50 first plating layer 60 second plating layer 70 surface tin plating layer C end conductive pattern portion

Continued front page    F term (reference) 5E062 FG01 FG11                 5E070 AA01 CB13 CB18 EA01                 5E082 AA01 AB03 BB07 BC38 BC40                       FG26 GG10 GG11 LL02 MM22                       MM24

Claims (9)

[Claims] 1. A laminated chip shape is obtained by forming a conductive portion at least at an end portion of an external electrode forming portion of each laminated member of a laminated chip component and then laminating the laminated members having the conductive portion formed thereon to form a laminated chip shape. A laminated chip part having an external electrode formed by plating the external electrode forming portion of the laminated member. 2. The conductive portion is formed by applying a conductive paste, and each of the laminated members is formed into a laminated chip by laminating and firing after forming the conductive portion. Multilayer chip parts. 3. The external electrode forming portion of the laminated multilayer chip portion is subjected to multilayer plating to electrically connect the conductive portions of the laminated members in the laminated state. The laminated chip component according to claim 1 or claim 2. 4. The multilayer chip component according to claim 3, wherein the multilayer plating is performed by at least nickel plating and then tin plating. 5. The laminated member is a ceramic material,
The laminated chip component according to any one of claims 1 to 3, which is made of an insulating material, a dielectric material, a magnetic material, or the like. 6. A conductive pattern portion necessary for each laminated member of a laminated chip component and an external electrode conductive portion are formed at least at an end portion of the external electrode forming portion, and the laminated members on which the conductive portion is formed are laminated and laminated. A method of manufacturing a laminated chip component, which is in the form of a chip, and the external electrode forming portion of the laminated chip is plated to form external electrodes. 7. The conductive part is formed by applying a conductive paste, and a necessary laminated member coated with the conductive paste is laminated and fired to form a laminated chip. Manufacturing method of laminated chip component. 8. The external electrode is formed by performing multi-layer plating on the external electrode forming portion of the laminated multilayer chip member so as to electrically connect the conductive portions of each of the multilayer members. Item 5. A method for manufacturing a laminated chip component according to claim 5 or 6. 9. The method of manufacturing a multilayer chip component according to claim 7, wherein the multilayer plating is at least nickel plating and then tin plating.