JP2003270305A - Test method for semiconductor integrated circuit and transaction method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test method allowing an efficient and low-cost testing of a semiconductor device by selecting the most suitable tester among a plurality of testers with different architectures, and allowing easy correction of a test program, thus reducing a total development period. <P>SOLUTION: The test program is prepared using a statement-type or operation-description-type language not regulated by the architecture of the tester as a common tester language. For each description of the test program, whether executable or not is judged with a plurality of testers prepared in advance. Based on the judgment results, the tester with the lowest testing cost is selected among ones capable of executing every description. The test is performed with the selected tester by converting the test program into a program executable by that tester. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test technique for testing whether or not a semiconductor integrated circuit has desired functions and performances, a technique for manufacturing a semiconductor device, and further designing, manufacturing and evaluating a semiconductor integrated circuit. The present invention relates to a technology that is effective when applied, for example, a technology that can be used for a business model performed when a company that develops semiconductor integrated circuits selects a tester or a company that specializes in testing or through the Internet.

[0002]

2. Description of the Related Art FIG. 7 shows a procedure for developing a semiconductor integrated circuit, that is, a general procedure from design to manufacturing. When developing a semiconductor integrated circuit, first, a system design, which is an operation level design focusing on functional operation, is performed (step S
1). Next, a logic gate level logic design and a circuit design in which the logic level is reduced to an element level are performed (step S2), a mask is manufactured, and the mask is used to form a semiconductor integrated circuit on a wafer. The wafer manufacturing process is started (step S3). After that, the wafer manufactured in the previous step is tested in the probe inspection process, which is a wafer inspection process under the provisional inspection conditions as in the development stage of the semiconductor integrated circuit device, to determine pass / fail, and the wafer is divided into chips. Non-defective chips that have been determined to be non-defective in the wafer inspection process are selected and assembled into a package (step S
4). This assembly is debugged by the characteristic evaluation (step S5), and when the characteristic is determined to satisfy the desired value (step S6), the final test specifications are determined and the test program used in the selection process. Create
After being certified as an engineering sample, it is transferred to mass production (steps S7 to S10).

A tester is used for these product evaluations and tests. The tester is composed of a test head that is connected to the input / output terminals of the device under test and has a plurality of interface boards called pin electronics that inputs and determines signals to the device under test, the tester body, its controller, etc. (See FIG. 3). The architecture of such a tester includes a shared resource system in which a timing generation circuit and a pattern generation circuit are shared by a plurality of pins, a per-pin system in which a timing generation circuit is shared for each pin and a pattern generation circuit is shared, and a pin generation system for each pin. There is a system having a timing generation circuit and a pattern generation circuit (referred to as a full-per pin system in this specification).

Conventionally, many shared resource testers have been used, and recently, per-pin type testers have begun to be used. It is estimated that full-per pin testers will be used in the future. Each tester has a power supply that supplies power to the device under test, a DC measurement system that evaluates the DC characteristics of the input / output terminals of the device, and a DAC (Digital to Analog Converter) converter that generates the DC level supplied to the device. have.

By the way, these testers use the O
It is controlled by a test program running under S (Operating System). This test program is written in a so-called tester language. The tester language is
Different tester architectures are typically different accordingly. As the tester language, there was an assembler-type language called machine word in order to directly control hardware. On the other hand, a tester control language was devised as a highly programmable one, and FORTRAN format and BASIC format were also used.
Furthermore, the structured language PASCAL was also actively used for a while, but is now in the C language.

[0006]

As described above, the tester language is assembler → FORTRAN, BASIC → PASCAL so as to adapt to the progress of programming languages in the world.
→ Although it has evolved to C language, C language has problems that it is difficult to use as a tester language because the function definition is forced on the user and the number of lines of the test program is extremely large, and the readability of the program is poor. It became clear. So, test without thinking about tester language.
A GUI (Graphical User Interface) capable of expressing only the flow has been studied.

[0007] The GUI is used to build a test program by converting a general test item into an icon and connecting it as a flow. However, if you want to write a complicated test item independently, write it directly in C language. It seems necessary to improve the productivity of the test program at first glance, but in fact, there are some aspects that hinder the productivity of the test program and the conversion into the test program in other languages. Furthermore, once a test program has been created, it is not something that will never be modified, and there is a need to make changes such as modifications due to changes in the manufacturing process. The modification work may be performed by a person who is not the creator of the program. The problem that the C language has poor readability because the test program description is distributed and the change work cannot be performed smoothly has begun to be highlighted.

Finally, a major problem is tester development and test program conversion at the mass production stage. In mass production, the tester used in the design is not always applied due to the requirement of cost reduction, and it becomes a relatively inexpensive tester different from the relatively high-performance and expensive tester that must be used in the design stage. May need to be expanded or test programs converted. At that time, if the test program is generated in the GUI environment, it becomes an environment regulated by the tester and the tester cannot be deployed. Therefore, the expensive design tester has to be used for mass production, resulting in the test cost. Cause an increase in In particular, when using a per-pin tester in the design and using a shared resource tester in manufacturing, the result is to reassess the resource allocation, and in general it is often impossible to use, so it is necessary to introduce a new tester, It can also increase test costs.

A test facilitation technique called DFT (Design For Test) has also been proposed in which a test circuit for testing an internal circuit is incorporated on a semiconductor chip to enable efficient testing. However, DF
When T is applied, the chip area increases, so that the chip cost increases from a hardware standpoint. In addition, if a tester performs a sufficient test without applying the DFT, the cost required for the test becomes high, which leads to an increase in the chip cost. Therefore, it is necessary to decide which one should be adopted based on the trade-off between the two. However, the cost calculation is not simple, and in the past, the cost was often high.

On the other hand, in recent years, in the field of semiconductor devices, a company specializing in circuit design called a fabless company and a tool for evaluating the function of a semiconductor device designed by the fabless company on a computer such as a workstation are provided. EDA (Engineering
A company called a design automation vendor,
A mask maker that manufactures masks based on data designed by the Fabless Company, a company called Test House that converts semiconductor device test programs designed and created by the Fabless Company into executable programs by selected testers. , A company called Fab Company that manufactures semiconductor devices using the created mask, a company called Test Fab that undertakes the test by the tester owned by using the test program created by the test house, The horizontal division of labor in the development and manufacturing of semiconductor integrated circuits by these specialized companies is also progressing.

An object of the present invention is to provide a test technique capable of efficiently testing a semiconductor integrated circuit at low cost by selecting the most suitable one from a plurality of testers having different architectures. is there. Another object of the present invention is to provide a test technique that enables a person different from the program creator to easily modify the test program, thereby shortening the total development period. Still another object of the present invention is to provide a method of selecting a means capable of manufacturing a semiconductor integrated circuit at the lowest cost in consideration of the cost increase associated with DFT application and the cost associated with test by a tester. is there. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, the first invention of the present application creates a test program for a semiconductor integrated circuit designed by adopting a statement format or behavioral description format language that is not regulated by the tester architecture as a common tester language, and For each description of the program, it is judged whether or not it can be executed by a plurality of testers assumed in advance, and based on the judgment result, the one with the lowest test cost is selected from the testers capable of executing all the descriptions, and the test is executed. A program is converted into a program executable by the selected tester and a test is performed.

Here, the statement format or behavior description format language is the minimum basic operation (test item) of the tester.
And a condition (parameter) are enumerated to mean a language that can compose a statement in one line. In programming languages,
It can be said that languages such as FORTRAN and BASIC are statement formats. It should be noted that the common tester language does not exclude a functional language such as C language, and a functional description in a statement format may be performed even in a functional language. Further, the description of the test program created in the common tester language may include test items that can be executed only in any one tester.

According to the above means, the test program is created in the common tester language which is not regulated by the tester architecture, so that the versatility of the program is increased and the program is created without determining the tester to be used. Or to use a similar device test program created earlier. Also, since the language of statement format or behavioral description format is adopted as the common tester language, the contents of the program can be easily understood,
A person different from the person who created the program can easily modify the program.

In the step of determining a tester capable of executing each description of the test program, at least
It is classified into descriptions that can be executed by all testers, descriptions that can be executed by any tester, and descriptions that cannot be executed by any tester. It is desirable to change the display. The description that cannot be executed by any tester includes the case where the parameter is not within the specification range, not the test item itself.

Further, when verifying the logical function of the semiconductor integrated circuit designed by the virtual tester, it is desirable to perform the verification by a late method. Here, the late method means a pattern generation method opposite to a pattern generation method called a time driven or time event method. Specifically, the time event method is shown in FIG.
As shown in FIG. 8B, the logical change point is monitored and the timing information and the logical value of the change point are extracted to generate a pattern, whereas the late method is shown in FIG. As described above, the pattern is divided at a constant cycle, and a test pattern is generated as 1/0 information for the pattern step.

The second invention of the present application is such that the cost associated with DFT mounting and the test cost by the tester are calculated and compared, and the one with the lowest cost is selected. Here, the cost associated with mounting the DFT includes the cost required for designing the DFT or obtaining design data in addition to the cost increase due to the increase in the chip area. The calculation of the test cost by the tester includes the calculation of the cost derived from the test time and the test required time corresponding to the number of test items in addition to the price of the tester. As a result, the test cost of the newly developed semiconductor integrated circuit and hence the chip unit price can be reduced.

In the third invention of the present application, the type of tester owned by each test fab is registered in a database or the like, and the tester is written in a common tester language in a statement format or a behavioral description format that is not regulated by the tester architecture. Based on the test program created according to the test device, extract the testers that can do this, identify the tester with the lowest test cost, and
The test fab that owns the tester is selected from the database, the manufactured semiconductor device is tested and stored in the selected test fab, and is shipped upon request. . As a result, a semiconductor device development and manufacturing environment compatible with horizontal division of labor can be realized, and a new business form using the Internet can be created.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a procedure from creation of a test program for a semiconductor integrated circuit to selection of a tester when the present invention is applied. When creating a test program for a newly developed semiconductor integrated circuit, the engineer first creates a source test program that describes the test items for the semiconductor integrated circuit based on the design data on a common tester on a computer such as a workstation. It is created using a language (step S1). At this time, a GU that supports the creation of test programs in advance
A test program can be efficiently created by preparing an I-system editor and installing it in the workstation to be used.

Next, it is checked whether the source program has a syntax error or the like. At this time, if there is a check program whose syntax can be checked, it is used, and if there is no check program, the source program is manually checked for errors (step S).
2). In addition, the test program creator often defines multiple voltage settings etc. to make the test program easier to understand, but check the redundancy here and change the content appropriately. It is a good idea to add the functionality to the check program.

If there is an error in the source program, it is corrected and the error is checked again (steps S3 → S4 → S2). If there is no error, the process moves to step S5 and a usable tester is selected from the test items described in the source program and the conditions thereof. At this time, a tester is selected using a database in which the specifications of each tester as shown in FIG. 2 are registered as tester resources. In particular,
As mentioned above, the tester has a shared resource method, a per-pin method, a full-per-pin method, etc. Depending on the description of the test program, refer to the tester resource to realize with the shared resource tester or the per pin tester. Or determine if it can only be achieved with a full per pin tester. Further, in this step, at least the description that can be executed by all the testers, the description that can be executed by any tester, and the description that cannot be executed by any tester are classified, and each of them is different on the monitor. It is desirable to display the display color or change the background color.

Next, the created source program is converted into a program executable by the tester (step S6). At this time, prepare a conversion program that converts a program written in a common language in advance into a program written in a tester language specified for each tester, and use that to perform the conversion. You can It is possible to convert the source program to the test program after determining the tester. However, by converting the source program to the test program first, more accurate cost calculation and tester tester that can be tested at low cost can be performed. Selection is possible.

Thereafter, the required time of the tester is calculated for each converted test program (step S7). At this time, since the processing time of each test item by the tester can be generally grasped from the tester resource, the total required time can be calculated by obtaining the processing time of each test item and summing them. In addition, since the waiting time may be described in the test program in consideration of the stable time of the device, in that case, the waiting time is also added to calculate the required test time. The processing time for each test item is determined exclusively by the tester language in which the test program is written, and does not depend much on the type of tester used, so it is not necessary to calculate the test required time for each tester.

Next, the test cost is calculated (step S8). The test cost is determined by the purchase price of the tester used, the amortization date and the time the tester is used. Therefore, if the test required time calculated in step S6 is used, the tester cost by the test program is calculated. it can. Once the test cost is obtained, it can be compared with the target selling price of the LSI by the designer, so that the tester to be used can be determined (step S9). Also, at this time, the cost increase associated with mounting a DFT such as a test scan path or a BIST (built-in self-test) circuit on the semiconductor integrated circuit to be tested is also calculated, and a test using only the tester is selected without mounting the DFT. It may be possible to consider which is the lower cost than the cost required for. Further, instead of deciding the tester with priority on the cost, the tester may be decided with priority on the test time.

FIG. 3 shows a basic configuration common to the testers of each system. As shown in FIG. 3, the tester 100 includes a semiconductor device D as an electronic component that is a device under test.
A power supply unit 110 that supplies a power supply voltage to the UT, a pattern generator 140 that generates test data and an expected value that are input to the semiconductor device DUT, and a timing generator 150 that generates an application timing of a signal that is input to the semiconductor device DUT. A DC test circuit 170 for performing a DC test such as voltage level detection of an output pin, a controller 160 for controlling these circuits, and the like.

The power supply unit 110 and the DC test circuit 170 do not change like a test program when the tester changes, and there is no need to change their configurations according to the device under test, and they are common. It can be a circuit. In addition to the above, the tester 100 of FIG. 3 includes a driver 120 that inputs a signal to an input pin of the semiconductor device DUT to be tested, and a comparator that compares a signal output from the output pin of the semiconductor device DUT with an expected value signal. And 130 are provided. These are provided on an interface board 190 called pin electronics in the test head 180 shown in FIG.

Although only one interface board 240 is shown in FIG. 4, many such boards are provided in an actual tester. 4 shows an example of a structure having a plurality of jigs for mounting the device under test on the test head 180. 181 is a fixing board, 182 is a conversion board, and 183 is a conversion board. Is a performance board, 184 is a flock ring, 185 is a small board, and 186 is a socket into which the semiconductor device DUT which is the device under test is inserted.

FIG. 9 shows an example of common tester language commands used in the above-described embodiment and parameters (variables) attached to each command. As the format of the command statement, for example, command = parameters 1, 2, ... N is adopted such as “VS = vs, Rvr, Mir, ip, im”.
The number n such as the channel number of the unit used or the pin number designating the pin to be measured is, for example, “VS”.
It should be added to the command or parameter such as “n” or “Pn.” Such a format is a statement method description based on the electrical measurement method, and according to this format, the meaning of the command statement is the description content. 9, "DUT" and "device" refer to the device under test, and the terminator is a switcher that switches the level received by the comparator 130. The commands shown in Fig. 9 are merely examples, and are not all commands for describing the test program, and other commands can be defined in the same format as the exemplified commands.

FIGS. 10 to 19 show examples of description of test programs corresponding to each test item and their contents in a circuit form. Of these, FIGS. 10 to 16 are descriptions relating to the tester, and FIG. 10 shows descriptions and contents of the power supply to be supplied to the device under test, which correspond to the commands and parameters in the common tester language of FIG. From FIG.
The description of the power supply is the command VS and the specified voltage value Vc.
It can be seen that it is composed of c, the current limit range setting Iclamp, and variables such as the measurement instruction IM. The range of variables is specified.

FIG. 11 shows the description and contents of the DC tester for measuring applied voltage, and FIGS. 12 and 13 show the description and contents of the DC tester for measured applied voltage. FIG. 14 shows an example of the test pattern description, and FIG. 15 shows an example of the voltage application sequence. Although not shown, commands and parameters as shown in FIG. 9 are defined corresponding to FIGS. 11 to 15. 16 to 19 are examples of description relating to control instructions, FIG. 16 is an example of test number description and measurement instruction description, FIG. 17 is an example of waiting time description, test end description and branch instruction description, and FIG. Shows examples of loop instruction description, limit description, program object name description, and program end instruction description. FIG. 19 shows an example of the symbol definition of the pin number of the device under test.

Next, the business model invented by the present inventors will be described. In recent years, with regard to the development and manufacturing of LSIs, in addition to the conventional method in which one company consistently performs them, circuit design is performed by a design specialized company, and the circuit designed here is tested by a test specialized company. A horizontal division of labor method, in which masks are created based on design data after debugging and LSIs that use the created masks are manufactured by different companies, has begun to be implemented. The business model described below is effective in such a horizontal division of labor system.

FIG. 5 is a system configuration diagram for explaining the business model considered by the present inventor, and FIG. 6 is a flowchart showing the procedure of this business model. In FIG. 5, reference numeral 300 designates a circuit design specialist designing company called a fabless company which undertakes circuit designing and creates a test program for the designed semiconductor device, and 400 represents a function of the semiconductor device designed by the fabless company such as a workstation. A company called EDA Vendor that provides a tool for evaluation on the computer, 500 is a company called Test House that converts a test program created by Fabless Company into a program executable by a selected tester, and 600 is a test A test company called Test Fab, which uses a test program provided by House to test the circuit designed by the design company using its own tester, 700 is a mask made based on the data designed by Fabless Company. Do A wafer manufacturing company, 800 is a wafer manufacturing company called a fab company that manufactures semiconductor devices on a wafer using the created mask, and 900 is a related company that manufactures test boards, probe cards, jigs, etc. used for testing. Companies, and of these companies EDA vendor 4
Computers of each company except 00 are the Internet 20
It is connected via 0 to enable data transmission.

The business model considered by the present inventor centers on the test house 500. In developing and manufacturing an LSI, as shown in FIG. 6, the test house 500 first asks the EDA vendor 400, the designing company 300, and the wafer making company 800 a common tester language as described in the above embodiment. To provide necessary materials (step S11, reference numeral in FIG. 6).

Next, the EDA vendor 400 is the design company 30.
For 0, a tool (program) called a virtual tester for performing logic simulation of a circuit on a workstation based on logic design data such as a netlist is provided (step S12, reference numeral in FIG. 6). Further, the design company 300 designs an LSI having a desired logic function, and
The logical function is verified by the virtual tester provided by the DA vendor, and the test program using the common tester language is created (steps S13 and S14).

On the other hand, the test house 500 receives the data regarding the specifications of the testers owned by those companies from the plurality of test fabs 600 and stores it in the database (see FIG. 6), and the design company 300 stores it. The created test program is received via the Internet 200 (step S15, reference numeral in FIG. 6). Then, the test house 500 analyzes the received test program, selects a tester that can be executed, calculates the required test cost, and the test fab 600 that owns the test cost and the lowest cost tester. Is presented to the design company (step S16, reference numeral in FIG. 6).
Then, the fabless company 300 judges the information and selects and designates an appropriate test fab (step S17, reference numeral in FIG. 6).

The test house 500 receives the request, converts the test program and sends it to the test fab 600, and presents the specifications of the test board and the probe card to be used to the affiliated company 900. Then, the production of a jig is requested (step S18, reference numeral in FIG. 6). At this time, the test house 500 verifies the test board, performs circuit simulation on the jig to be used, and adjusts the signal timing in the test program in consideration of the delay due to the jig. . Also, the test house uses a virtual tester to verify that the converted test program can be tested without problems. Then, the verified test program is transmitted to the test fab 600 designated by the fabless company 300.

Next, a jig used for the test is created by the affiliated company 900, and the created jig and mask are sent to the test fab 600 (step S19,
6 reference numeral). On the other hand, the mask company 700, which has received a request from the design company, creates a mask, and the created mask is passed to the wafer creating company 800 to create a wafer (steps S20, S21, reference numerals in FIG. ).
The created wafer is tested by the wafer creation company 800.
The wafer is sent to the fab 600, and the test fab tests the received wafer with the test program provided by the test house 500 (step S22, reference numeral 1 in FIG. 6).
0). Then, they are assembled into finished products, and the finished products are selected based on the test result of step S22 and delivered to the fabless company 300, which the fabless company stores and ships to the market according to the order. (Steps S23 and S24).

According to such a method, it is possible to reduce the cost required when the development / manufacturing of a semiconductor integrated circuit is performed by horizontal division of labor, shorten the development period, and provide a new business opportunity. It has the advantage of being possible. In the above business model, proposal of common tester language, introduction of optimal test fab, adjustment of test program, conversion, etc. are performed in the test house, but other companies such as EDA vendors and test fabs It is also possible to do. Also,
An organization in which a test fab and a test house are integrated, an organization in which an EDA vendor and a test house are integrated, and the like are also conceivable, and the present invention can be applied to such cases.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. In the above description, the case where the invention made by the present inventor is mainly applied to the development of the semiconductor integrated circuit which is the field of application which is the background of the invention has been described, but the present invention is not limited thereto and the electronic component or the electronic It can be widely used in the development of products that are tested using testers such as equipment.

[0040]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, the most suitable one can be selected from a plurality of testers having different architectures, and the semiconductor integrated circuit can be tested efficiently and at low cost. In addition, a person different from the program creator can easily modify the test program, thereby shortening the total development period. Further, the semiconductor integrated circuit can be manufactured at the lowest cost in consideration of the cost increase associated with the DFT application and the cost associated with the test by the tester.

[Brief description of drawings]

FIG. 1 is a flowchart showing a procedure from creation of a test program for a semiconductor integrated circuit to selection of a tester when the present invention is applied.

FIG. 2 is an explanatory diagram showing a specification example of a plurality of testers registered in a database as a tester resource.

FIG. 3 is a block diagram showing a basic configuration common to testers of each method.

FIG. 4 is a perspective view showing a structure of a test head of a tester.

FIG. 5 is a system configuration diagram showing an example of a network system for explaining a business model considered by the present inventor.

FIG. 6 is a flowchart showing a procedure of a business model considered by the present inventor.

FIG. 7 is a flowchart showing a procedure from designing to manufacturing in the development of a semiconductor integrated circuit which is currently generally performed.

FIG. 8 is a diagram for explaining a pattern generation method of a late method and a time driven method.

FIG. 9 is an explanatory diagram showing an example of commands in a common tester language used in the embodiment and parameters (variables) attached to each command.

FIG. 10 is an explanatory diagram showing, as a circuit, a description example of a power supply and its contents in a description example of a test program corresponding to each test item.

FIG. 11 is an explanatory diagram showing, as a circuit, a description example of a voltage applied current measurement DC tester and a description example of a test program corresponding to each test item.

FIG. 12 is an explanatory diagram showing, as a circuit, a description example of a current applied voltage measurement DC tester and a description example of a test program corresponding to each test item.

FIG. 13 is an explanatory diagram showing, in a circuit form, another description example of the current applied voltage measurement DC tester among the description examples of the test program corresponding to each test item.

FIG. 14 is an explanatory diagram showing, as a circuit, a description example of a test pattern and its contents in a description example of a test program corresponding to each test item.

FIG. 15 is an explanatory diagram showing, as a circuit, a description example of a voltage application sequence and description contents of the description example of the test program corresponding to each test item.

FIG. 16 is an explanatory diagram showing an example of a test number description and a measurement instruction description among the description examples of the test program corresponding to each test item.

FIG. 17 is an explanatory diagram showing an example of a waiting time description, a test end description, and a branch instruction description among the description examples of the test program corresponding to each test item.

FIG. 18 is an explanatory diagram showing an example of a loop command description, a limit description, a program object name description, and a program end command description among the description examples of the test program corresponding to each test item.

FIG. 19 is an explanatory diagram showing a description example of the symbol definition of the pin number of the device under test among the description examples of the test program corresponding to each test item.

[Explanation of symbols]

100 tester 110 power supply unit 120 driver 130 comparator 140 pattern generator 150 timing generator 160 controller 170 DC test circuit 180 test heads 181 to 185 test jig 190 interface board (pin electronics) DUT device under test 200 internet 300 fabless company (Design Company) 400 EDA Vendor 500 Test House 600 Test Fab (Test Company) 700 Mask Maker 800 Fab Company (Wafer Making Company) 900 Jig Manufacturing Company (Associated Company)

Continued front page    (72) Inventor Katsumi Ogawa             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within F-term (reference) 2G132 AA00 AC03 AE08 AE14 AE27                       AF00 AG02 AL00

Claims (10)

[Claims] 1. A test program for testing a semiconductor integrated circuit is created using a desired language, and a tester having the lowest test cost is selected from testers capable of executing all the descriptions, and the test program is selected. A method for testing a semiconductor integrated circuit, comprising: converting a program into a program executable by the selected tester and performing a test. 2. The semiconductor integrated circuit according to claim 1, wherein the test cost is calculated based on a purchase price of the tester, an amortization period, and a test required time of a tester that executes the test program. Circuit testing method. 3. The test of the semiconductor integrated circuit according to claim 1, wherein the test required time is determined by determining the required time for each test item of the test program and adding them. Method. 4. The tester of the first method, wherein the plurality of testers share a timing generation circuit and a pattern generation circuit with a plurality of measurement pin functions, and a pattern generation circuit having a timing generation circuit for each measurement pin function. 4. A tester of a second method that shares the same, and a tester of a third method that has a timing generation circuit and a pattern generation circuit for each measurement pin function are included. Semiconductor integrated circuit test method. 5. The test program is verified by a check program.
A method for testing a semiconductor integrated circuit according to any one of 1. 6. The method of testing a semiconductor integrated circuit according to claim 1, wherein the conversion of the test program is performed by a conversion program. 7. In the determination as to whether or not the test program can be executed by a plurality of testers for each description of the test program,
Characterized by classifying into descriptions that can be executed by all testers, descriptions that can be executed only by at least one of the testers, and descriptions that cannot be executed by any of the testers, and display in different display colors. Claims 1 to 6
A method for testing a semiconductor integrated circuit according to any one of 1. 8. A test program is created using a desired language, and it is judged for each description of the test program whether or not it can be executed by any of a plurality of testers. While the tester capable of executing the description has the lowest test cost, the increased cost associated with mounting the test support circuit for facilitating the test on the semiconductor integrated circuit is calculated, and the increased cost and the determination are made. Compared with the test cost by the selected tester, select the one with lower cost, and if the test cost by the tester is lower, convert the test program into a program executable by the selected tester. A method for testing a semiconductor integrated circuit, which comprises performing a test by performing a test. 9. The increased cost associated with mounting the test support circuit on a semiconductor integrated circuit includes an increased cost due to an increase in chip size and a cost required to obtain design data of the test support circuit. Claim 5
A method for testing a semiconductor integrated circuit according to. 10. The type of tester owned by a plurality of test fabs connected via the Internet is registered in a database, and the device under test is written in a common tester language in a format not regulated by the architecture of the tester. The test program that can execute this is extracted based on the test program created according to the test program, the tester with the lowest test cost is identified, and the test fab that owns the tester is identified from the database. Is selected, and the manufactured semiconductor device is tested and stored in a selected test fab, and shipped, and shipped according to a request.