JP2003268588A - Deposition method for gold wiring - Google Patents
Deposition method for gold wiringInfo
- Publication number
- JP2003268588A JP2003268588A JP2002066674A JP2002066674A JP2003268588A JP 2003268588 A JP2003268588 A JP 2003268588A JP 2002066674 A JP2002066674 A JP 2002066674A JP 2002066674 A JP2002066674 A JP 2002066674A JP 2003268588 A JP2003268588 A JP 2003268588A
- Authority
- JP
- Japan
- Prior art keywords
- gold
- wiring
- current density
- plating
- gold wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、超高速集積回路及
び混成マイクロ波回路等の半導体集積回路用金配線の堆
積方法に関するものである。特に、プロセス時間の短縮
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for depositing gold wiring for semiconductor integrated circuits such as ultra high speed integrated circuits and hybrid microwave circuits. In particular, it relates to reduction of process time.
【０００２】[0002]
【従来の技術】超高速集積回路及び混成マイクロ波回路
等の半導体集積回路の配線では、配線抵抗低減の点から
抵抗率の低い金を用いた厚い配線が有効である。2. Description of the Related Art In wiring of semiconductor integrated circuits such as ultra high speed integrated circuits and hybrid microwave circuits, thick wiring made of gold having a low resistivity is effective from the viewpoint of reducing wiring resistance.
【０００３】金の堆積方法としては、スパッタ法、蒸着
法、及びメッキ法が一般的である。スパッタ法及び蒸着
法は、高真空状態で金を堆積する必要があるため、メッ
キ装置に比べ装置が高価となる。As a gold deposition method, a sputtering method, a vapor deposition method, and a plating method are generally used. Since the sputtering method and the vapor deposition method require gold to be deposited in a high vacuum state, the cost of the apparatus is higher than that of a plating apparatus.
【０００４】また、スパッタ法及び蒸着法では、ウエハ
だけでなくチャンバー（反応室）の壁にも金が堆積さ
れ、ウエハに堆積される金よりチャンバーの壁に堆積さ
れる金が圧倒的に多い。すなわち、金の利用効率が非常
に低い。一方、メッキ法はウエハのみに金が堆積される
ため、金の利用効率が非常に高い。Further, in the sputtering method and the vapor deposition method, gold is deposited not only on the wafer but also on the wall of the chamber (reaction chamber), and the amount of gold deposited on the wall of the chamber is overwhelmingly larger than the gold deposited on the wafer. . That is, the utilization efficiency of gold is very low. On the other hand, in the plating method, since gold is deposited only on the wafer, the utilization efficiency of gold is very high.
【０００５】さらに、スパッタ法及び蒸着法は、側壁へ
の付きまわりが悪いため、基板表面の凹凸が大きい場
合、断線等の問題が起きるが、メッキ法は側壁への付き
まわりに優れているため、このような問題はない。Further, since the sputtering method and the vapor deposition method have poor adhesion to the side wall, problems such as disconnection occur when the substrate surface has large irregularities, but the plating method has excellent adhesion to the sidewall. , There is no such problem.
【０００６】以上の点から、金の堆積法としてはメッキ
法が最も優れている。From the above points, the plating method is the most excellent method for depositing gold.
【０００７】[0007]
【本発明が解決しようとする課題】メッキ法で堆積した
金の膜はエネルギー的に不安定な状態にあり、室温でも
徐々に再結晶化し、安定な状態になる。このとき、金の
抵抗が変動する。これを慣用的にセルフアニールと呼
ぶ。図３にメッキ後の経過時間とメッキ金のシート抵抗
の関係を示す。ここで、膜厚２μｍ、電流密度４ｍＡ／
ｃｍ2である。図より、セルフアニール前後で約３０〜
４０％変化する。The gold film deposited by the plating method is in an energetically unstable state and gradually recrystallizes even at room temperature and becomes stable. At this time, the resistance of gold fluctuates. This is conventionally called self-annealing. FIG. 3 shows the relationship between the elapsed time after plating and the sheet resistance of plated gold. Here, the film thickness is 2 μm and the current density is 4 mA /
cm 2 . From the figure, about 30 ~ before and after self-annealing
40% change.
【０００８】また、セルフアニールが終了する時間は、
メッキ条件により異なるが、この場合約５００時間とな
っている。このような抵抗変動は、配線抵抗が評価のた
びに変化することを示しており、回路特性が評価のたび
に変動するという問題を引き起こす。従って、セルフア
ニール（抵抗変動）の影響を防止するため、一般に熱処
理をメッキ後に行う。この１工程追加により、工程時間
が長くなるという欠点があった。Also, the time for completing the self-annealing is
In this case, it takes about 500 hours, although it depends on the plating conditions. Such a resistance change indicates that the wiring resistance changes every evaluation, and causes a problem that the circuit characteristics change each evaluation. Therefore, in order to prevent the influence of self-annealing (resistance fluctuation), heat treatment is generally performed after plating. There is a drawback that the process time becomes long due to the addition of this one process.
【０００９】[0009]
【課題を解決するための手段】上記の課題を解決するた
め、本発明による金配線の堆積方法は、電解メッキによ
って膜厚１μｍ以上のメッキ金配線を堆積する金配線の
堆積方法において、形成されたメッキ金配線のセルフア
ニールの終了がほぼ１日以内になるような低電流密度で
メッキを行うことを特徴とする。In order to solve the above problems, the method for depositing gold wiring according to the present invention is a method for depositing gold wiring in which a plated gold wiring having a film thickness of 1 μm or more is deposited by electrolytic plating. It is characterized in that the plated gold wiring is plated at such a low current density that the self-annealing is completed within about one day.
【００１０】また、本発明は、前記膜厚がほぼ１μｍの
時、前記電流密度は１ｍＡ／ｃｍ2以下であることを特
徴とする。さらに、前記膜厚が２μｍ以下の時、前記電
流密度は１．５ｍＡ／ｃｍ2以下であることを特徴と
し、前記膜厚が４μｍ以下の時、前記電流密度は２ｍＡ
／ｃｍ2以下であることを特徴とする。Further, the present invention is characterized in that the current density is 1 mA / cm 2 or less when the film thickness is approximately 1 μm. Furthermore, when the film thickness is 2 μm or less, the current density is 1.5 mA / cm 2 or less, and when the film thickness is 4 μm or less, the current density is 2 mA.
/ Cm 2 or less.
【００１１】本発明によれば、膜厚１μｍ以上メッキ金
配線を堆積する場合、形成されたメッキ金配線のセルフ
アニールの終了がほぼ１日以内になるような低電流密度
でメッキを行うため、メッキ後に熱処理を行うことなく
配線を形成することが可能となる。これにより、半導体
集積回路用配線のプロセス時間を短縮し、低コスト化に
寄与するものである。According to the present invention, when a plated gold wiring having a film thickness of 1 μm or more is deposited, plating is performed at a low current density such that self-annealing of the formed plated gold wiring is completed within about one day. Wiring can be formed without heat treatment after plating. This shortens the process time of the semiconductor integrated circuit wiring and contributes to cost reduction.
【００１２】[0012]
【実施例】次に本発明の実施例（図１）について説明す
る。EXAMPLE Next, an example of the present invention (FIG. 1) will be described.
【００１３】（ａ）絶縁膜２を有する半導体基板１に、
先ず金と絶縁膜との密着性を向上するための薄い下地メ
タル層３と、メッキ金の種となる薄い種金層４をスパッ
タ法により連続形成する。薄い下地メタルは通常、ＷＳ
ｉＮやＷが用いられ、例えば３５０Å堆積する。また、
種となる薄い金層は例えば２０００Å堆積する。(A) On the semiconductor substrate 1 having the insulating film 2,
First, a thin base metal layer 3 for improving the adhesion between gold and an insulating film and a thin seed metal layer 4 as a seed of plated gold are continuously formed by a sputtering method. Thin base metal is usually WS
iN or W is used, for example, 350 Å is deposited. Also,
The thin seed gold layer is deposited, for example, 2000 liters.
【００１４】（ｂ）金配線を形成しない領域をレジスト
マスク５で覆う。レジストマスクの厚みは、メッキする
金の厚み以上とする。例えば５μｍとする。(B) The resist mask 5 covers the region where the gold wiring is not formed. The thickness of the resist mask is not less than the thickness of gold to be plated. For example, it is set to 5 μm.
【００１５】（ｃ）電解メッキにより、メッキ金６をレ
ジストマスク５の無い領域に例えば１〜４μｍ成長す
る。メッキ条件は、例えば１ｍＡ／ｃｍ2を用いる。こ
の条件を用いることにより、その後の熱処理が不要とな
る。(C) By electroplating, the plated gold 6 is grown in a region without the resist mask 5 by, for example, 1 to 4 μm. The plating condition is, for example, 1 mA / cm 2 . By using this condition, the subsequent heat treatment becomes unnecessary.
【００１６】（ｄ）フォトレジスト５を酸素プラズマ処
理（灰化）などにより除去する。(D) The photoresist 5 is removed by oxygen plasma treatment (ashing) or the like.
【００１７】（ｅ）フォトレジスト５で覆われていた領
域のメッキ金の種となる種金層４及び下地メタル層３を
ミリング法により除去する。このとき、メッキ金も若干
ミリングされるが、種金層４及び下地メタル層３が薄い
ので問題ない。これにより金配線７が形成される。(E) The seed metal layer 4 and the underlying metal layer 3 which are the seeds of the plated gold in the region covered with the photoresist 5 are removed by the milling method. At this time, the plated gold is also slightly milled, but there is no problem because the seed metal layer 4 and the base metal layer 3 are thin. As a result, the gold wiring 7 is formed.
【００１８】本発明は、半導体集積回路の金配線形成に
おいて、低電流密度のメッキを行うことにより、メッキ
後の熱処理を必要としない堆積方法を可能とする。The present invention enables a deposition method that does not require heat treatment after plating by performing low current density plating in forming gold wiring of a semiconductor integrated circuit.
【００１９】上述のように堆積させた金配線のメッキ堆
積時の条件を最適化し抵抗変動の終了時間を短くするこ
とにより、熱処理無しでも回路特性に悪影響を及ぼさな
いようにする。By optimizing the conditions at the time of depositing the gold wiring deposited as described above and shortening the end time of the resistance variation, the circuit characteristics are not adversely affected even without heat treatment.
【００２０】図２に、実施例で製造した金膜厚の違いに
よるメッキの電流密度とセルフアニール終了時間の関係
を示す。どの膜厚においても、電流密度の低下ととも
に、セルフアニール終了時間は短くなる。一方、同じ電
流密度で比較すると、膜厚が厚いほどセルフアニール終
了時間は短いことが分かる。FIG. 2 shows the relationship between the plating current density and the self-annealing end time depending on the difference in the gold film thickness manufactured in the example. For any film thickness, the self-annealing end time becomes shorter as the current density decreases. On the other hand, when compared at the same current density, it can be seen that the larger the film thickness, the shorter the self-annealing end time.
【００２１】図より１μｍ以上の厚みの場合、１ｍＡ／
ｃｍ2の電流密度以下でセルフアニール終了時間は約１
日以内となり、現実的に回路評価に影響しない時間とな
る。なお、膜厚が厚い場合、たとえば２μｍの場合に
は、１．５ｍＡ／ｃｍ2の電流密度でも、セルフアニー
ル終了時間は１日以内となる。また、例えば４μｍの場
合は２ｍＡ／ｃｍ2の電流密度でもセルフアニール終了
時間は１日以内となる。１μｍ以下の薄い膜の場合、セ
ルフアニール終了時間を１日以内に抑えることは非常に
難しい。From the figure, when the thickness is 1 μm or more, 1 mA /
If the current density is less than cm 2 , the self-annealing completion time is about 1
It will be within a day, and the time will not actually affect the circuit evaluation. When the film thickness is large, for example, 2 μm, the self-annealing completion time is within one day even at a current density of 1.5 mA / cm 2 . Further, for example, in the case of 4 μm, the self-annealing completion time is within 1 day even at a current density of 2 mA / cm 2 . In the case of a thin film having a thickness of 1 μm or less, it is very difficult to suppress the self-annealing end time within 1 day.
【００２２】[0022]
【発明の効果】以上述べたように、本発明による金配線
の堆積方法によれば、膜厚１μｍ以上メッキ金配線を堆
積する場合、形成されたメッキ金配線のセルフアニール
の終了がほぼ１日以内になるような低電流密度でメッキ
を行うため、メッキ後に熱処理を行うことなく配線を形
成することが可能となる。これにより、半導体集積回路
用配線のプロセス時間を短縮し、低コスト化に寄与する
ものである。As described above, according to the gold wiring depositing method of the present invention, when the plated gold wiring having a film thickness of 1 μm or more is deposited, the self-annealing of the formed plated gold wiring is completed for about one day. Since the plating is performed at such a low current density as to fall within the range, the wiring can be formed without performing heat treatment after the plating. This shortens the process time of the semiconductor integrated circuit wiring and contributes to cost reduction.
【図１】本発明による配線形成工程、（ａ）〜（ｅ）は
各工程を示す。FIG. 1 shows a wiring forming process according to the present invention, and (a) to (e) show each process.
【図２】金膜厚の違いによるメッキの電流密度とセルフ
アニール終了時間の関係を示す図。FIG. 2 is a diagram showing the relationship between the plating current density and the self-annealing end time depending on the difference in gold film thickness.
【図３】メッキ後の経過時間とともにメッキ金のシート
抵抗が変化することを示す図。FIG. 3 is a view showing that the sheet resistance of plated gold changes with the lapse of time after plating.
１ 半導体基板 ２ 絶縁膜 ３ 下地メタル ４ 種金層 ５ レジストマスク ６ メッキ金 ７ 金配線 1 Semiconductor substrate 2 insulating film 3 Base metal 4 kinds of gold layer 5 Resist mask 6 plated gold 7 gold wiring
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 21/3205 Ｈ０１Ｌ 21/88 Ｂ Ｆターム(参考） 4K024 AA11 AB08 AB19 BA07 BB11 CA06 DB01 FA05 GA16 4M104 BB09 BB18 BB28 DD37 DD52 DD65 HH20 5F033 HH13 HH19 HH28 HH32 MM05 MM08 PP15 PP27 QQ08 QQ14 WW02 WW08 XX14 XX33 XX34─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 21/3205 H01L 21/88 BF term (reference) 4K024 AA11 AB08 AB19 BA07 BB11 CA06 DB01 FA05 GA16 4M104 BB09 BB18 BB28 DD37 DD52 DD65 HH20 5F033 HH13 HH19 HH28 HH32 MM05 MM08 PP15 PP27 QQ08 QQ14 WW02 WW08 XX14 XX33 XX34
Claims (4)
ッキ金配線を堆積する金配線の堆積方法において、電解
メッキの電流密度は、形成されたメッキ金配線のセルフ
アニールの終了がほぼ１日以内になるような低電流密度
でメッキを行うことを特徴とする金配線の堆積方法。1. A method for depositing a gold wiring in which a plated gold wiring having a film thickness of 1 μm or more is deposited by electroplating, the current density of the electroplating is such that self-annealing of the formed plated gold wiring is completed within about one day. A method for depositing gold wiring, characterized in that plating is performed at such a low current density.
度は１ｍＡ／ｃｍ 2以下であることを特徴とする請求項
１記載の金配線の堆積方法。2. The current density when the film thickness is approximately 1 μm.
Degree is 1 mA / cm 2Claims characterized in that
1. The method for depositing gold wiring according to 1.
度は１．５ｍＡ／ｃｍ2以下であることを特徴とする請
求項１記載の金配線の堆積方法。3. The method for depositing gold wiring according to claim 1, wherein when the film thickness is 2 μm or less, the current density is 1.5 mA / cm 2 or less.
度は２ｍＡ／ｃｍ 2以下であることを特徴とする請求項
１記載の金配線の堆積方法。4. The current density is reduced when the film thickness is 4 μm or less.
2mA / cm 2Claims characterized in that
1. The method for depositing gold wiring according to 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002066674A JP2003268588A (en) | 2002-03-12 | 2002-03-12 | Deposition method for gold wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002066674A JP2003268588A (en) | 2002-03-12 | 2002-03-12 | Deposition method for gold wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003268588A true JP2003268588A (en) | 2003-09-25 |
Family
ID=29198344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002066674A Pending JP2003268588A (en) | 2002-03-12 | 2002-03-12 | Deposition method for gold wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003268588A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2021048210A (en) * | 2019-09-18 | 2021-03-25 | トヨタ自動車株式会社 | Manufacturing method of wiring board and the wiring board |
-
2002
- 2002-03-12 JP JP2002066674A patent/JP2003268588A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2021048210A (en) * | 2019-09-18 | 2021-03-25 | トヨタ自動車株式会社 | Manufacturing method of wiring board and the wiring board |
| JP7238712B2 (en) | 2019-09-18 | 2023-03-14 | トヨタ自動車株式会社 | Wiring board manufacturing method and wiring board |
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