JP2003264242A - Method for modeling integrated circuit and integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for modeling a transistor in which the true performance of a transistor fabricated finally can be approximated to a performance simulated using a simulation model. <P>SOLUTION: A system for modeling an integrated circuit including at least one insulated gate field-effect transistor comprises a generator means (MLB) for defining parameter representating of mechanical stresses applied to the active area of the transistor, and a processing means (MT) for determining at least several electric parameters (P) of the transistor while taking account of the stress parameters. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to integrated circuits, and more particularly to integrated circuit modeling and more particularly to insulated gate field effect transistors (MOSFETs).

[0002]

Many MOSFET simulations are currently available. For example, BSIM3v available at the College of Electronics and Computer Sciences, University of Berkeley, California
There are 3.2 models, especially Weidong Liu and others 1997-1
There is a user manual issued by 998.

This type of model is used by integrated circuit designers to determine carrier mobility, threshold voltage,
And required electronic characteristics such as drain current MOSFET
Define and simulate.

[0004]

There are cases in which the simulated performance using these simulation models does not match the true performance expected of the final MOSFET.

The present invention provides a solution to this problem.

[0006] It is an object of the present invention to provide transistor modeling to approximate the true performance of the final fabricated transistor to that simulated using simulation models.

Another object of the present invention is to make an integrated circuit including a MOSFET, the electronic properties of which can be tailored and improved in the functioning of the intended application, especially with regard to mobility.

The present invention is obtained by varying the electronic properties of a transistor, such as mobility, threshold voltage, or drain source resistance, as a function of mechanical stress applied to the channel of the transistor. Is. Mechanical stress is a result of the manufacturing process, especially for shallow trench isolation (ST
I) as a result of forming electrically insulating regions that extend the operating region of the transistor, such as regions.

[0009]

SUMMARY OF THE INVENTION The present invention comprises at least one
A method of modeling an integrated circuit including two insulated gate field effect transistors, wherein a parameter a _eq representing a mechanical stress applied to an operating region of the transistor is an electrical parameter of the transistor, such as carrier mobility, threshold. It provides methods that are defined and taken into account in determining voltage, drain / source access resistance.

In some simple situations, the method of the present invention allows for direct calculation of electrical parameters, taking into account stress parameters.

However, as a general rule, the present invention complements existing standard or non-standard simulation models. For example, it is done by modifying the input parameters of an existing model used in the existing model to determine more refined electrical parameters of the transistor.

For example, the low electric field mobility μ0 of carriers at room temperature is one of the parameters that the method of the present invention modifies to directly represent the mechanical stress. Once modified, this parameter μ0 can be used for existing models, such as the BSIM described above.
It is incorporated into the 3v3.2 model and is used to determine the effective carrier mobility μeff, a more refined parameter that specifically takes into account quadratic effects in the electrical behavior of transistors.

When the analysis is performed in this way, finally,
The electrical parameter μ _eff is determined and represents the effect of mechanical stress in the operating region of the transistor.

Similarly, the diffused drain / source resistance per unit width of the channel Rdsw is a parameter that can be easily determined by defining the mechanical stress using the method according to the invention. Incorporated continuously into existing models to determine the source resistance Rds.

The same applies to the parameters described below. For example, Vth0: Threshold voltage when gate / source voltage is 0 and channel width is large K1: First order effect coefficient K2: Second order effect coefficient K3: Narrow channel width coefficient K3b: K3 Base effect coefficient Dvt0 : First short-channel effect of threshold voltage
Coefficient Dvt0W: The first coefficient of the short channel effect with a short channel length at the threshold voltage Eta0: The drain-induced barrier that reduces the coefficient in the region below the threshold Etab: The body bias coefficient of the DIBL effect below the threshold These are determined once by the method according to the invention and once the mechanical stress is defined, they are incorporated into the BSIM3v3.2 model to determine the threshold voltage.

According to an embodiment of the invention, a "useful" operating area is defined as all or part of said operating area. The useful operating area may be part of the operating area within a rectangle, where the lateral dimension of the widthwise rectangle of the channel is equal to the width of the channel, and each end of the channel across the width of the channel is It is at a predetermined boundary distance from the corresponding side of the gate. The distance may be about 10 times the minimum distance required by the contact terminals in the operating area.

The stress parameter is preferably a geometric parameter a _eq which represents the distance in the longitudinal direction of the channel of the transistor between the gate of the transistor and the edge of the useful operating area.

The present invention thus represents a fairly simple one-dimensional geometric parameter, in this example distance, the effect of three-dimensional mechanical stress on the electrical parameter of a transistor.

If the useful operating area of the transistor is rectangular and the gate is located in the center of the useful operating area to define geometrically identical source and drain areas, the stress parameter a _eq is It is defined as the longitudinal distance a of the channel between the side surface and the corresponding edge of the source or drain region.

However, the transistor does not always have a rectangular useful operating area and a gate centrally located in the operating area. When the useful operating region of the transistor includes geometrically different source and drain regions, a first geometrical parameter a _s representing a first distance in the length direction of the channel between the gate and the end of the source region. Is defined.
A second geometrical parameter a _d is defined which represents the distance in the longitudinal direction of the channel between the gate and the drain region.

The stress parameter a _eq is defined by an equation using the first geometrical parameter and the second geometrical parameter.

For example, the stress parameter is 1 / (1 / 2a _s + 1 /
2a _d ).

The useful operating region of the transistor includes at least one source or drain region, where there is no obtuse angle on each side, and the source or drain region can be divided into n individual rectangular regions, where n is 1. If so, each region is defined by a width W _i and individual edges at a distance a _i from the gate in the length direction of the channel.

The corresponding geometrical parameter a _s or a _d is
Equal to W / {ΣW _i / a _i }, where W can be the channel width of the transistor.

On the other hand, if the useful operating region of the transistor comprises at least one source or drain region, at least one side of which has at least one obtuse angle, the corresponding parameter a _s or a _d is treated as infinity. .

Similarly, for the sake of simplicity, if the individual distances of the individual areas of the useful operating area are equal to the boundary distances that extend the rectangle of the useful operating area, the individual distances a _i are treated as equal to infinity. .

In one form of the present invention, the value of an electrical parameter determined with respect to a reference distance, such as the minimum distance required by the operating region, the value of the stress parameter of the transistor, the minimum distance required, etc. The electrical parameter P of the transistor is defined by an equation that is related to the value of the reference distance and the electrical parameter and that includes a coefficient that depends on the width and length of the channel of the transistor.

The stress parameter is the geometric parameter a _eq
, The relevant electrical parameter P is defined, for example, by

P = Pa _min (1 + CP _{L, W} (1-a _min / a _eq )) Pa _min is the value of the electrical parameter P determined for the minimum distance a _min required by the operating area. , CP _{L, W} are coefficients related to the parameter P.

In this case, the determination of the coefficient CP _{L, W} includes, for example, the following steps.

A plurality of reference transistors are generated, with different reference values Wref, Lr for the width and length of the channel
ef and different values for the stress parameters.

The value of the electrical parameter P is measured for each reference transistor produced.

Reference coefficient for each set of values Wref and Lref
CP _{Lref, Wref} is defined as the slope of the straight line of the formula Y = 1 + CP _{Lef, Wref} X, where Y = P / P _min and X = 1-a _min / a _eq .

The coefficient CP _{L, W} is the width of the channel of the transistor from the reference coefficient, possibly using interpolation
Determined taking into account W and length L.

The present invention further provides a system for modeling an integrated circuit that includes at least one insulated gate field effect transistor.

According to one aspect of the present invention, the system includes a generating means for defining a parameter representing a mechanical stress applied to an operating region of the transistor, and the electrical parameter of the transistor in consideration of the stress parameter. Processing means.

In one form of the invention, the generating means delimits the useful operating region as part or all of the operating region and the stress parameter is between the gate of the transistor and the end of the useful operating region. _Is a geometric parameter a _eq representing the distance in the length direction of the gate of the transistor of FIG.

In one form of the invention, the useful operating area of the transistor is rectangular, the gate is at the center of the useful operating area for delimiting the geometrically identical source and drain areas, and the generating means is , Stress parameter a
_{Denote eq} as the lengthwise distance of the channel between the side of the gate and the corresponding edge of the source or drain region.

In another form of the invention, the useful operating region of the transistor comprises geometrically different drain and source regions and the generating means comprises a channel length between the gate and the edge of the source region. A first geometrical parameter a _s representing a first distance in the vertical direction and a second geometrical parameter a _d representing a longitudinal distance of the channel between the gate and the end of the drain region. Then, the generating means defines the stress parameter by an equation connecting the first geometric parameter and the second geometric parameter.

In one form of the invention, the processing means defines the electrical parameter of the transistor by an equation containing the following values:

The value of the electrical parameter determined for the reference distance such as the minimum distance required by the operating region, the value of the stress parameter of the transistor, the value of the reference distance such as the required minimum distance, the electrical in relation to the parameters electrical parameter P of coefficients associated depending on the width and length of the channel of the transistor, wherein P = Pa _min (1 + CP
_{L, W} (1-a _min / a _eq )), Pa _min
Is the value of the electrical parameter P determined for the minimum distance a _min required by the operating region, and CP _{L, W} is a coefficient related to the parameter P.

The modeling device, in which a plurality of reference transistors are generated, has different reference values Wref, Lref for the width and length of the channel and different values for the stress parameter.

The processing device further comprises: A measuring means for measuring the value of the electric parameter P for each generated reference transistor.

For each set of values Wref and Lref, the equation Y =
1 + CP _{Lef, Wref} The first calculation means for calculating the reference coefficient CP _{Lref, Wref} defined as the slope of the straight line. Where Y = P / P
_min and X = 1-a _min / a _eq .

The coefficients CP _{L, W} are the reference coefficients CP _{Lref, Wref}
From the second calculation means, taking into account the width W and the length L of the channel of the transistor by means of interpolation if possible.

To make a transistor, the present invention also adjusts the shape of the operating region of the transistor as a function of, for example, room temperature low field carrier mobility, threshold voltage, and the like.

In other words, it is possible to use the modeling method according to the invention to determine the relevant electrical parameters for a given geometrical parameter of the operating region. As a result, it is possible to determine the geometrical parameters of the operating region of the transistor which, in turn, create the required values for the relevant electrical parameters in order to produce the integrated circuit.

In other words, the present invention also relates to a method of manufacturing an integrated circuit comprising at least one insulated gate field effect transistor, the parameter being used to represent the mechanical stress applied to the operating region of the transistor. A shape of the operating region is defined, defining a required value of at least one electrical parameter of the transistor determined by a modeling method according to the method described above, and providing a method of defining the stress parameter.

Thus, the profile of the useful area of the transistor can be tailored to optimize the transistor in terms of mobility, which would further reduce drain / source resistance, which is particularly beneficial in the case of MOSFETs. is there.

In one form, the useful operating region is defined as all or part of the operating region, and the stress parameter is such that the channel length of the transistor between the gate of the transistor and the edge of the useful operating region is defined. It is a geometric parameter a _eq that represents the distance in the vertical direction.

Therefore, if the transistor is an NMOS transistor and the geometrical parameter a _eq is more than twice the minimum distance a _min required for the contact terminals of the operating area, the length of the operating area is required. An improvement in carrier mobility is particularly obtained compared to a transistor equal to the minimum distance.

Similarly, for transistors above 80%, the geometric parameters are more than twice the minimum distance.
When including at least one block including a plurality of NMOS transistors, the entire block of the integrated circuit is considered to have an advantage in terms of the moving area.

These advantages are also obtained when the transistor is a PMOS transistor, especially in terms of mobility. In this case, the geometrical parameter a _eq is preferably less than twice the required minimum distance.

Similarly, with respect to the moving region, this advantage is at least 1 including a plurality of PMOS transistors for 80% or more in which the geometric parameter is more than twice the minimum distance.
Applies to integrated circuits that include two blocks.

The present invention provides an integrated circuit including at least one insulated gate field effect transistor.

In accordance with one aspect of the invention, the operating region of a transistor includes a useful operating region defined as part or all of the operating region, the channel of the transistor between the gate of the transistor and the edge of the useful operating region. The distance a _{eq in the} length direction is different from the minimum distance required by the contact terminals in the operating area of the integrated circuit.

[0057] In one embodiment, the transistor is an NMOS transistor, greater than twice the distance a _eq is the minimum distance a _{mi n.}

In one form, the transistor is a plurality of NMOSs.
Including at least one block including a transistor,
Over 80% of NMOS transistors have geometrical parameters that are more than twice the minimum distance.

[0059] In one embodiment, the transistor is a PMOS transistor, the distance a _eq is less than twice the minimum distance a _{mi n.}

In one form of the invention, the integrated circuit comprises at least one block in which the transistor comprises a plurality of PMOS transistors, wherein 80% or more of the PMOS transistors have a geometrical parameter less than twice the minimum distance. With.

In any of the above-mentioned modes, the useful operation area is a part of the operation area included in the rectangle, and the lateral dimension of the rectangle in the width direction of the channel is equal to the width of the channel. Each end of the channel in the direction is at a predetermined boundary distance from the corresponding side of the gate, for example the boundary distance is on the order of about 10 times the required minimum distance a _min .

[0062]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a generating means MLB for creating a stress parameter representative of the mechanical stress applied to the operating region of a transistor from a transistor layout schematic. In material terms, the generating means is a subtractor known to those skilled in the art to subtract from the transistor layout schematic the dimensional parameters of the transistor, such as the length and width of the channel, as well as the information at the connection. be able to.

Once this stress parameter is determined,
As will be described in detail later, the processing means MT implemented as software in the microprocessor determines at least some of the electrical parameters P of the transistors that define the stress parameters, for example.

The electrical parameter P can be a low electric field carrier mobility μ0 at room temperature, for example a threshold voltage Vth0 in a long channel with a gate / source voltage of 0, or scattered source / source voltage per unit width of the channel. It can be drain resistance.

These electric parameters P are for explaining the stress applied to the operating region of the transistor, and the standard B such as BSIM3 v3.2 of Berkeley University mentioned above.
Can be included in the SIM simulation model. This model is based on effective mobility μ _eff , drain / source resistance R
Used to calculate other more advanced parameters such as ds and threshold voltage Vth. On the other hand, the parameters obtained from the BSIM model also define the stress applied to the operating region of the transistor.

It has been found that all three-dimensional stresses applied to the operating region can be explained using stress parameters, which are actually one-dimensional parameters. The one-dimensional parameter is more precisely the geometric parameter a _eq , which represents the distance in the length direction of the transistor channel between the gate of the transistor and the edge of the operating region.

As shown in FIG. 2, the operating region of the PMOS transistor is rectangular. The gate GR is located in the center of the operating region and defines geometrically equivalent source and drain regions S and D. The stress parameter a _eq is defined as the distance a in the channel length L direction between the side surface FLC of the gate and the source or drain region, here the end BRD of the source region.

Supplementally, this distance a is the minimum distance a required to form the contact terminal CT of the source or drain region.
It can be different from _min .

FIG. 3 shows the mobility μ0 and the value a _{min for the} value a.
Shows a modification of the function of the ratio of the distance a to the mobility μ0 with respect to. Supplementally, the mobility μ0 increases for a of the NMOS transistor (curve C1NMOS) and decreases for a of the PMOS transistor (curve C1PMOS). On the other hand, for PMOS transistors, mobility increases when a is less than a _min .

When the operating region of the transistor comprises geometrically different source and drain regions, the first geometrical parameter a _s is the first longitudinal parameter of the channel between the gate and the edge of the source region. Defined to represent distance.

The second geometrical parameter a _d is defined to represent the distance along the length of the channel between the gate and the edge of the drain region. This stress parameter a _eq is defined by the following equation.

A _eq = 1 / (1 / 2a _s + 1 / 2a _d ) Formula (1)

Not only can the source and drain regions be geometrically different, but also FIG. 4 (a) or FIG.
It can be irregular as in the case of (a) and FIG.

The geometrically irregular source and drain regions have an acute angle ANGF as shown on the right side of FIGS. 4 (a) and 5 (a), and on the right side of FIG. 5 (a) and It is distinguished from those with obtuse angle ANGO as shown in FIG.

Here, referring to FIG. 4A, the source region S and the drain region D are shown. There is no obtuse angle on each of these flanks, and the acute angle at the right end of the relevant region is defined here as the angle equal to 90 °.

The source region S is divided into n individual regions RG _i (where n = 4). Each region RG _i has its respective width W _i and its respective end at a distance a _i from the gate GR in the direction of the channel length L.
Has BEL _i .

The geometrical parameter a _s is defined by the equation described later.

[0078]

[Equation 1] Formula (2)

Here, W is the entire width of the channel.

Similarly, the drain region D is divided into four regions. Each region has its own width W _i and its extreme ends are at respective distances b _i from the corresponding sides of the gate GR.

The geometric parameter a _d is defined by the equation described later.

[0082]

[Equation 2] Formula (3)

From the viewpoint of modeling, T in FIG.
The MOS transistor is equivalent to the TMOS transistor shown in FIG.

Further, the stress parameter a _eq is defined by the above equation (1). From a modeling perspective,
The TMOS transistor of FIG. 4 (a) is equivalent to the TMOS transistor of FIG. 4 (c) which has a regular and rectangular operating region with the center gate.

First of all, it must be pointed out that
When parameter a_eqIs the parameter a _minSignificantly compared to
Can be larger or significantly smaller
That is.

Irregular source or drain surfaces with obtuse angle ANGO are further described with reference to FIGS. 5 (a) -7. As shown in FIGS. 5 (a) and 6, the obtuse angle ANGO (here, angle 270 °) is located at the edge of the side of the relevant region, which means that the side of the relevant region extends outside the channel. It means that.

For this kind of source and drain regions, the corresponding geometrical parameters a _s or a _d are infinite.

From the viewpoint of modeling, a TMOS transistor equivalent to the TMOS transistor of FIG. 5A is shown in FIG. 5B and has an infinite parameter a _s and a parameter a defined by the equation (3). _{has d} .

Finally, from the viewpoint of modeling, FIG.
The TMOS transistor equivalent to the transistor in (a) is the TMOS transistor of FIG. 7, where a _eq is still defined by the above equation, but since a _s is infinite, it will be 2 a _d in this example.

In FIG. 6, the source and drain regions are
Both have obtuse angle ANGOs. As a result, two parameters
Since a _s and a _d are infinite, the parameter a _eq of the equivalent TMOS transistor (FIG. 7) is still theoretically defined by equation (1), and since a _s and a _d are both infinite,
In fact it becomes infinite.

If the operating area ZA of the TMOS transistor is particularly complicated, for example, as shown in FIG. 8, the "useful" operating area ZA
It is preferred to delimit U within the operating region of the transistor. The useful operating area is contained within the rectangular area and its edge BLZ
, Each of which is at a predetermined boundary distance from the side surface of the gate corresponding to the direction of the width W of the channel, where the distance is 10 a _min .

Further, the lateral dimension of this rectangular region is the width direction of the channel, that is, actually the length of the end BLZ (the end BLY of the side surface).
Direction) but equal to the width W of the channel.

The value 10 a _min here is a compromise between, for example, the expected improvement in mobility and the simplicity of modeling. If this value exceeds 10 a _min , the improvement in mobility will be
It becomes much smaller as shown by C1NMOS.

Now that the useful operating area ZAU has been defined, the procedure is as described above, with the source and drain regions being n.
Are divided into three individual areas, where the three individual areas are
Determining the range of the _three individual transistors T ₁ , T ₂ , T ₃ .

Furthermore, an individual distance a _i or b _i is considered equal to infinity if it equals the boundary distance 10 a _min .

The parameters a _s and a _d of the TMOS transistor, which are limited to the useful operating area, are determined as described above.

Therefore, the parameter a _s defined by the above equation (2) is actually substantially defined by the equation described later.

A _s = W / (W ₁ / a ₁ ) Formula (4)

This is because the distances a ₂ and a ₃ are infinite.

Similarly, the parameter a _d is simply defined by the following equation.

A _d = W / (W ₃ / b ₃ ) Formula (5)

This is because the distances b ₁ and b ₂ are infinite.

The equivalent parameter a _eq is also defined by the above equation (1).

Once the geometrical parameter a _eq is obtained, the processing means determines the relevant electrical parameter of the transistor P.

In this embodiment, the electrical parameter P
Is defined by the following equation.

P = Pa _min (1 + CP _{L, W} (1-a _min / a _eq )) Formula (6)

Where Pa _min is the value of the electrical parameter P determined for the minimum distance a _min required by the operating region, CP _{L, W} is related to the electrical parameter P and the width W of the channel of the transistor and It is a coefficient depending on the length L.

This equation gives the mobility μ0 for the particular case of FIG.
Indicated by. The curve C2NMOS is actually a straight line,
This equation has been described for an NMOS transistor. Straight line
C2PMOS describes this equation for PMOS transistors.

The procedure shown in FIG. 10 is preferably used to determine the coefficient CP _{L, W} associated with the parameter P.

A plurality of test or reference transistors are created (step 100). There are different reference values W _ref , L _ref for the width and length of the channel and different values for the stress parameter a _eq .

A conventional measurement system, MMS, of the type known in the industry, for each reference transistor created,
It is used to measure the value of the relevant electrical parameter P (step 101). For example, mobility or threshold voltage can be measured on a reference transistor by the Hammer method known in the art.

The first calculating means MC1 is, for each pair of values W _ref and L _ref , the reference coefficient CP which is the slope of the straight line of this equation.
_{Determine Lref and Wref} .

Here, Y = 1 + CP _{Lref, Wref} X, and Y = P /
Pa _min , X = 1-a _min / a _eq .

Finally, the second calculating means MC2 uses the reference coefficient CP.
_Determine the coefficients CP _{L and W} from _Lref and _Wref (step 103),
Transistor channel width using interpolation if possible
Define W and length L.

The present invention is used to make integrated circuits that include MOS transistors. The area around the operating area of the transistor is
For example, it is adjusted as a function of mobility (FIG. 11).

In this case, as shown in FIG. 11, the simulation model according to the invention described above is applied for the required mobility (step 110) and for the selected channel width and length of the transistor. By doing so, the value of the stress parameter a _eq is obtained. The periphery of the operating area of the transistor can be defined.

FIG. 12 shows two inputs (NAND
2 shows a layout diagram of a basic NAND gate cell CL1 with 2 gates).

The cell is conventionally two PMOS transistors.
It includes PMOS1 and PMOS2 and two NMOS transistors NMOS1 and NMOS2. The first input IN1 of the cell CL1 is incorporated into the gate of the two transistors PMOS1 and NMOS1, and the second input IN2 of the cell is the two transistors PMOS2 and NMOS2.
It is included in the gate GR2 by. Output OUT of cell CL1
Are taken from the common source region of transistors PMOS1 and PMOS2.

FIG. 12 shows that the lengths of the channel of the source and drain regions of the transistor in the length direction are made equal to the minimum distance a _min . Similarly, the spacing between the gates is made equal to the minimum value min.

As a result, a cell of this kind is created, which applies the high-density standard.

On the other hand, for the PMOS transistor, the stress parameter a _eq is larger than the parameter a _{min and} smaller than twice the parameter.

The same applies to NMOS transistors. As a result, this type of cell CL1 is not optimized in terms of mobility, especially as compared to the same type of cell CL2, as shown in FIG.

FIG. 13 shows that the source regions of the transistors PMOS1 and PMOS2 are divided by the distance min. In addition, these source and drain regions are a _min
Is equal to. As a result, the stress parameter a _eq for these two PMOS transistors is equal to a _min .

Similarly, the width of the source region of the NMOS transistor is increased to 2 a _min . As a result, the stress parameter a _eq for the two NMOS transistors is more than twice the required minimum distance a _min .

Therefore, cell CL2 has a higher mobility than cell CL1.

The cell CL3 is also a NAND2 cell and has a considerably high mobility. The operating area of the transistors PMOS1 and PMOS2 has a constriction between the contact terminals, the width of this limitation is the distance a
_Because it is smaller than _min .

As a result, the stress parameter a _eq for the two PMOS transistors is the minimum distance a _min required.
Smaller than

The operating region of the NMOS transistor has an obtuse angle, which makes the parameter a _eq infinite.

The present invention is not limited to the above described embodiments, but includes all modifications of the invention.

More specifically, the parameter P is determined by the reference value Pa, which is the value of the parameter for the reference value a _min.
Described using _min . Different reference values may be used without changing the general principles and advantages of the invention, eg it is the value of the parameter for a reference distance other than a _min .

Further, the electric parameter P is the above-mentioned equation (6).
Not limited to.

The value of the parameter P for the reference distance,
Other equations, including channel width and length dependent factors, can also be considered for parameters such as threshold voltage.

Therefore, the threshold voltage is calculated.
In order to have P = Pa_min+ CP2_{L, W}(1-a _min/ a_eq) Is used
Can be, for example here CP2_{L, W}Is the two constants Pa
_minAnd CP_{L, W}It is obtained from the product of

In this case, to correct the threshold voltage of the BSIM3v3.2 model, for example, only the parameter Vth0 (threshold voltage when the gate / source voltage is zero and the channel width is large) is imposed. Here, the modification of the multiplier defined by the equation (6) is performed by changing the parameter Vth0,
Requires previous modification of K1, K2, K3, K3b, Dvt0, Dvt0w, Eta0, Etab.

[Brief description of drawings]

1 is a schematic diagram of a modeling system enabling the use of a modeling method according to the present invention.

FIG. 2 MO focusing on the geometrical parameters of the present invention
Schematic of the S-transistor.

FIG. 3 is a schematic diagram of two curves illustrating the advantages of the present invention with respect to transistor carrier mobility.

FIG. 4 is a diagram schematically showing the derivation of a geometrical parameter representing a stress applied to an operating region of a first type MOS transistor.

FIG. 5 schematically shows the derivation of two other geometrical parameters, which represent the stresses exerted on the operating area of two other types of MOS transistors.

FIG. 6 schematically shows the derivation of two other geometrical parameters representing the stresses exerted on the operating areas of two other types of MOS transistors.

FIG. 7 schematically shows the derivation of two other geometrical parameters, which represent the stresses exerted on the operating regions of two other types of MOS transistors.

FIG. 8 is a diagram showing how to define a useful operating region within the operating region of a MOS transistor.

FIG. 9 schematically shows two other curves illustrating the relationship between carrier mobility and geometrical parameters representing stress.

FIG. 10 is a diagram schematically illustrating a method in which the modeling system determines the slope of the curve shown in FIG. 9.

FIG. 11 is a diagram showing a schematic flow chart of an application example of a method for producing a MOS transistor according to the present invention.

FIG. 12 schematically shows three different geometries of basic cells of an integrated circuit, which give different mobilities.

FIG. 13 schematically shows three different geometries of basic cells of an integrated circuit, which give different mobilities.

FIG. 14 schematically shows three different geometries of basic cells of an integrated circuit, which give different mobilities.

[Explanation of symbols]

MLB stress parameter generation means MT processing means GR gate S source D drain ZAU useful operating area ZA operating area FLC side BRD edge

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Claims (42)

[Claims] 1. A method of modeling an integrated circuit including at least one insulated gate field effect transistor, the method comprising: defining and taking into account a parameter a _eq representing a mechanical stress exerted on an operating region of the transistor. A method of modeling an integrated circuit for determining at least some electrical parameters of a transistor. 2. A useful operating region is defined as all or a portion of the operating region, and the stress parameter is a length direction of a channel of the transistor between a gate of the transistor and an end of the useful operating region. The method according to claim 1, which is a geometrical parameter representing the distance of 3. The useful operating area of the transistor is rectangular, the gate is centrally located in the useful operating area to define geometrically identical source and drain regions, and the stress parameter a _eq. The method of claim 2, wherein is defined as the longitudinal distance a of the channel between the side of the gate and the corresponding end of the source or drain region. 4. A useful geometry of the transistor comprises a geometrically distinct source and drain regions, the first geometry representing a first distance along a length of a channel between a gate and an edge of the source region. A geometrical parameter a _s and a second geometrical parameter a _d representing the distance in the length direction of the channel between the gate and the drain region are defined, and the stress parameter
The a _eq is defined by an equation using the first geometric parameter and the second geometric parameter.
The method described in. 5. The stress parameter is 1 / (1 / 2a _s + 1 / 2a _d ).
The method of claim 4, defined as equal to. 6. The useful operating region of the transistor includes at least one source or drain region, each side having no obtuse angles, and the source or drain region can be divided into n individual rectangular regions, n Is greater than or equal to 1 and each region comprises a width W _i and an individual edge at a distance a _i from the gate in the lengthwise direction of the channel, the corresponding geometrical parameter a _s or a _d being W / { 6. The method according to claim 4 or 5, wherein ΣW _i / a _i } and W is the channel width of the transistor. 7. The useful operating region of the transistor comprises at least one source or drain region, at least one side of which has at least one obtuse angle and the corresponding parameter a _s or a _d is treated as infinity. The method according to claim 4 or 5. 8. The useful operating area is defined as a part of the operating area contained within a rectangle, the lateral dimension of the rectangle in the width direction of the channel being equal to the width of the channel and of the channel in the width direction of the channel. 8. A method according to any one of claims 2 to 7, wherein each end is at a predetermined border distance 10a _min from the corresponding side of the gate. 9. The method according to claim 8, wherein if the individual distances a _i are equal to the boundary distance, they are treated as equal to infinity. 10. The method of claim 8 or 9, wherein the boundary distance is about 10 times the minimum distance required for contact terminals in the useful operating area. 11. A value of an electrical parameter determined with respect to a reference distance such as a minimum distance required for the operating region, a value of a stress parameter of the transistor, a minimum distance required, and the like. 11. The electrical parameter of the transistor is defined by an equation comprising a value of the reference distance and a coefficient related to the electrical parameter and dependent on a channel width and length of the transistor. The method according to one. 12. The reference distance is a minimum distance a _min required for the operation area, and the electric parameter P is expressed by an equation P = Pa _min (1 + CP _{L, W} (1-a
_min / a _eq )), Pa _min is the value of the electrical parameter determined for the minimum distance a _min required in the operating region, and CP _{L, W} is the coefficient associated with the parameter P. The determination of the coefficient CP _{L, W} is such that a plurality of reference transistors are generated, having different reference values Wref, Lref for channel width and length, and different values for the stress parameter, The value of the parameter P is measured for each generated reference transistor, and for each set of values Wref, Lref, the reference coefficient CP _{Lref, Wref} is defined as the slope of the straight line of the formula Y = 1 + CP _{Lef, Wref} X, where Y = P / P _min and X = 1-a _min / a _eq , the coefficient taking into account the channel width W and length L of the transistor from the reference coefficient, possibly using interpolation. Decided by putting, done by The method of claim 11. 13. The electrical parameter includes room temperature low field carrier mobility, threshold voltage, and drain / source resistance.
Method described in one. 14. The method according to claim 1, wherein the electrical parameters determined in view of the stress parameters are incorporated into a standard transistor model (BSIM). 15. A system for modeling an integrated circuit including at least one insulated gate field effect transistor, the generating means defining a parameter representative of a mechanical stress applied to an operating region of the transistor, and the stress parameter. And processing means for determining at least some electrical parameters of said transistor in view of the above. 16. The generating means delimits a useful operating region as part or all of the operating region, the stress parameter being a gate of a transistor between a gate of the transistor and an end of the useful operating region. 16. The method according to claim 15, which is a geometrical parameter a _eq representing a lengthwise distance of the. 17. The transistor useful operating area is rectangular, the gate is at the center of the useful operating area for delimiting geometrically identical source and drain regions, and the generating means is The stress parameter a _eq is
17. The system of claim 16, delimited as the longitudinal distance of the channel between the side of the gate and the corresponding end of the source or drain region. 18. The useful operating region of the transistor includes geometrically different drain and source regions, and the generating means includes a first longitudinal direction of a channel between the gate and an edge of the source region. The first geometrical parameter a _s representing the distance and the second geometrical parameter a _d representing the distance in the length direction of the channel between the gate and the end of the drain region are defined, and the generating means The system of claim 16, wherein the stress parameter is defined by an equation connecting the first geometric parameter and the second geometric parameter. 19. The stress parameter is 1 / (1 / 2a _s + 1 / 2a
_19. The system of claim 18, defined as equal to _d ). 20. The useful operating region of the transistor includes at least one source or drain region, each side having no obtuse angles, and the source or drain region can be divided into n individual rectangular regions, n Is greater than or equal to 1 and each individual region comprises a width Wi and an individual edge at a distance ai from the gate in the longitudinal direction of the channel, and the corresponding geometrical parameter a _s or a _d is W / {ΣW _20. The system according to claim 18 or 19, wherein is equal to _i / a _i } and W is the channel width of the transistor. 21. The useful operating region of the transistor comprises at least one source or drain region, at least one side of which has at least one obtuse angle, the corresponding parameter a _s or a _d being treated as infinity. ,
20. The system according to claim 18 or 19. 22. The useful operating area is defined as a part of the operating area contained within a rectangle, wherein the lateral dimension of the rectangle in the width direction of the channel is equal to the width of the channel and of the channel in the width direction of the channel. 22. The system of any one of claims 16-21, wherein each end is at a predetermined boundary distance from the corresponding side of the gate. 23. The system of claim 22, wherein if the individual distances a _i are equal to the boundary distance, they are treated as equal to infinity. 24. The system of claim 22 or 23, wherein the boundary distance is about 10 times the minimum distance required for contact terminals in the useful operating area. 25. A value of an electrical parameter determined with respect to a reference distance such as a minimum distance required for the operating region, a value of a stress parameter of the transistor, a minimum distance required, etc. 25. The electrical parameter of the transistor is defined by an equation comprising a value of the reference distance and a coefficient related to the electrical parameter and dependent on a channel width and length of the transistor. The system according to one. 26. The reference distance is a minimum distance a _min required for the operation area, and the electric parameter P is expressed by an equation P = Pa _min (1 + CP _{L, W} (1-a
_min / a _eq )), Pa _min is the value of the electrical parameter determined for the minimum distance a _min required in the operating region, and CP _{L, W} is the coefficient associated with the parameter P. The determination of the coefficient CP _{L, W} is such that a plurality of reference transistors are generated, having different reference values Wref, Lref for channel width and length, and different values for the stress parameter, The value of the parameter P is measured for each generated reference transistor, and for each set of values Wref, Lref, the reference coefficient CP _{Lref, Wref} is defined as the slope of the straight line of the formula Y = 1 + CP _{Lef, Wref} X, where Y = P / P _min and X = 1-a _min / a _eq , the coefficient taking into account the channel width W and length L of the transistor from the reference coefficient, possibly using interpolation. Decided by putting, done by The system of claim 25. 27. The system of claim 15, wherein the electrical parameters include room temperature low field carrier mobility, threshold voltage, and drain / source resistance. 28. The method according to claim 15, wherein the electrical parameters determined in consideration of the stress parameters are incorporated into a standard transistor model (BSIM). 29. A method of making an integrated circuit including at least one insulated gate field effect transistor, the shape of an operating region of the transistor being determined using a parameter representative of mechanical stress applied to the operating region of the transistor. A method for defining a required value of at least one electrical parameter of a transistor defined and determined by a modeling method according to the method according to any one of claims 1 to 14 and defining the stress parameter. 30. A useful operating region is defined as all or a portion of the operating region, and the stress parameter is such that the stress parameter is in a longitudinal direction of a channel of the transistor between the gate of the transistor and an end of the useful operating region. 30. The method of claim 29, which is a geometrical parameter representing the distance of. 31. The method of claim 29 or 30, wherein the electrical parameters include room temperature low field carrier mobility, threshold voltage, and drain / source resistance. 32. A method according to claim 30 or 31, wherein the transistor is an NMOS transistor and the geometrical parameter a _eq is more than twice the minimum distance a _min required for the contact terminals of the active area. 33. The method of claim 32, wherein the transistor comprises at least one block including a plurality of NMOS transistors for 80% or more, wherein the geometric parameter is at least twice the minimum distance. 34. The method according to claim 30 or 31, wherein the transistor is a PMOS transistor and the geometrical parameter a _eq is less than twice the minimum distance required for the contact terminals of the active area. 35. The method of claim 34, wherein the integrated circuit includes at least one block that includes a plurality of PMOS transistors for 80% or more with a geometric parameter that is at least twice the minimum distance. 36. An integrated circuit including at least one insulated gate field effect transistor, the operating area of the transistor including a useful operating area defined as part or all of the operating area, the gate of the transistor and the useful operation. The longitudinal distance a _eq of the transistor channel to the edge of the region is different from the minimum distance required for the contact terminals of the operating region of the integrated circuit. 37. The integrated circuit of claim 36, wherein the transistor is an NMOS transistor and the distance a _eq is greater than twice the minimum distance a _min . 38. The integrated device of claim 37, wherein the transistor comprises at least one block including a plurality of NMOS transistors, wherein 80% or more of the NMOS transistors have a geometric parameter greater than or equal to twice the minimum distance. circuit. 39. The integrated circuit of claim 36, wherein the transistor is a PMOS transistor and the distance a _eq is less than twice the minimum distance a _min . 40. The integrated device of claim 39, wherein the transistor comprises at least one block including a plurality of PMOS transistors, wherein 80% or more of the PMOS transistors have a geometric parameter less than or equal to twice the minimum distance. circuit. 41. The useful operation area is a part of an operation area included in a rectangle, and a lateral dimension of the rectangle in a width direction of the channel is equal to a width of the channel, and each of the channels in the width direction of the channel. 41. The integrated circuit of any one of claims 36-40, wherein the edge is at a predetermined boundary distance from the corresponding side of the gate. 42. The boundary distance is the minimum distance a required
_42. The integrated circuit according to claim 41, which is about 10 times _min .