US7480604B2 - Method of modeling and producing an integrated circuit including at least one transistor and corresponding integrated circuit - Google Patents
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- US7480604B2 US7480604B2 US10/339,640 US33964003A US7480604B2 US 7480604 B2 US7480604 B2 US 7480604B2 US 33964003 A US33964003 A US 33964003A US 7480604 B2 US7480604 B2 US 7480604B2
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Definitions
- the present invention relates to integrated circuits, and in particular to modeling integrated circuits such as insulated-gate field-effect transistors (MOSFETs).
- MOSFETs insulated-gate field-effect transistors
- MOSFET simulation models are currently available, for example the BSIM3v3.2 model available from the Department of Electrical Engineering and Computer Sciences, University of Berkeley, Calif., and described in particular in the 1997-1998 user manual by Weidong Liu and others, which is herein incorporated by reference.
- This kind of model is used by integrated circuit designers to define and simulate MOSFET in terms of their required electrical characteristics, for example carrier mobility, threshold voltage, drain current, etc.
- the present invention aims to provide a solution to this problem.
- Another object of the present invention is to produce integrated circuits including MOSFET whose electrical performance, in particular in terms of mobility, can be adjusted and improved as a function of the intended applications.
- One embodiment of the present invention provides a system for modeling an integrated circuit including at least one insulated-gate field-effect transistor.
- the system includes generator means and processing means.
- the generator means defines a parameter representing mechanical stresses applied to an active area of the transistor, and the processing means determines at least one of the electrical parameters (P) of the transistor at least partially based on the stress parameter.
- the generator means defines a useful active area as some or the whole of the active area, and the stress parameter is a geometrical parameter a eq representing a distance in the direction of the length of the channel of the transistor between the gate of the transistor and the edge of the useful active area.
- Another embodiment of the present invention provides a method of modeling an integrated circuit including at least one insulated-gate field-effect transistor.
- a parameter (a eq ) representing mechanical stresses applied to an active area of the transistor is defined, and the parameter (a eq ) is taken into account when determining at least one electrical parameter (P) of the transistor.
- a useful active area (ZAU) is defined as some or the whole of the active area (ZA)
- the stress parameter is a geometrical parameter a eq representing a distance in the direction of the length of the channel of the transistor between the gate of the transistor and the edge of the useful active area.
- FIG. 1 shows generally a modeling system according to a preferred embodiment of the present invention
- FIG. 2 is a diagram of a MOS transistor
- FIG. 3 shows two curves illustrating the advantages of a preferred embodiment of the present invention in terms of transistor carrier mobility
- FIGS. 4 a to 4 c show the derivation of a geometrical parameter representing stresses applied to the active area of a first type of MOS transistor
- FIGS. 5 a , 5 b , 6 and 7 show the derivation of two other geometrical parameters representing stresses applied to the active areas of two other types of MOS transistor;
- FIG. 8 shows the definition of a useful active area within an active area of an MOS transistor
- FIG. 9 shows two other curves illustrating a relationship between carrier mobility and the geometrical parameter representing stresses
- FIG. 10 shows in more detail how the modeling system determines the slope of the curves shown in FIG. 9 ;
- FIG. 11 shows a general flowchart of one exemplary application of a method in accordance with a preferred embodiment of the present invention.
- FIGS. 12 to 14 show three different geometrical configurations of a base cell of an integrated circuit, providing different mobilities.
- the present invention stems from the observation that some electrical parameters of a transistor, for example the mobility, threshold voltage or drain/source resistance, vary as a function of mechanical stresses applied to the channel of the transistor.
- the mechanical stresses are a result of the fabrication process, in particular the forming of electrically insulative regions delimiting the active area of the transistor, for example shallow trench isolation (STI) regions.
- STI shallow trench isolation
- Preferred embodiments of the present invention therefore provide a method of modeling an integrated circuit including at least one insulated-gate field-effect transistor.
- a parameter representing mechanical stresses applied to an active area of the transistor is defined and is taken into account when determining at least some electrical parameters of the transistor, for example the carrier mobility, threshold voltage, drain/source access resistance, etc.
- the method could model some electrical parameters directly, taking account of the stress parameter.
- preferred embodiments of the present invention advantageously complement existing standard or non-standard simulation models, for example by correcting some input parameters of existing models that are used in the existing models to determine more sophisticated electrical parameters of the transistors.
- the low-field mobility ⁇ 0 of the carriers at room temperature is one parameter that the method of the present invention can correct directly to allow for mechanical stresses.
- this parameter ⁇ 0 is injected into an existing model, for example the BSIM3v3.2 model previously cited, where it is used to determine the effective carrier mobility ⁇ eff , which is a more sophisticated parameter taking account in particular of secondary effects in the electrical behavior of the transistor.
- the electrical parameter ⁇ eff is determined allowing for the effect of mechanical stresses on the active area of the transistor.
- the stray drain/source resistance per unit width of the channel Rdsw is a parameter that can easily be determined using the method according to the present invention allowing for the mechanical stresses, and which is subsequently injected into an existing model to determine the drain/source resistance Rds.
- a “useful” active area is defined as a portion or the whole of the active area of the transistor.
- This useful active area can be the portion of the active area contained within a rectangle whose lateral dimension in the direction of the width of the channel is equal to the width of the channel, and each edge of which extending in the direction of the width of the channel is at a predetermined limit distance from the corresponding flank of the gate, which distance can be of the order of ten times a minimum distance required for a contact terminal in the active area. This is explained in detail later.
- the stress parameter is then preferably a geometrical parameter a eq representing a distance in the direction of the length of the channel of the transistor between the gate of the transistor and the edge of the useful active area.
- an extremely simple and unidimensional geometrical parameter in this instance a distance, allows for the effect on the electrical parameters of the transistor of three-dimensional mechanical stresses.
- the stress parameter a eq can then be the distance in the direction of the length of the channel between one flank of the gate and the corresponding edge of the source or drain region.
- transistors do not always have rectangular active areas and gates centered in the active areas. Also, if the useful active region of the transistor includes geometrically different source and drain regions, a first geometrical parameter a s representing a first distance in the direction of the length of the channel between the gate and the edge of the source region is advantageously defined.
- a second geometrical parameter a d representing a distance in the direction of the length of the channel between the gate and the edge of the drain region is also defined.
- the stress parameter a eq is then defined by a relationship between the first and second geometrical parameters.
- the stress parameter a eq can be made equal to 1/(1 ⁇ 2a s +1 ⁇ 2a d ).
- the useful active area of the transistor includes at least one source or drain region each lateral side of which is free of obtuse angles, and if it is possible to divide the source and drain region into n individual rectangular regions, n being greater than or equal to 1, each individual region is defined by an individual width W i and by an individual distance a i in the direction of the length of the channel between the gate and an individual edge of the individual region.
- W is the width of the channel of the transistor.
- the useful active area of the transistor includes at least one source or drain region at least one lateral side of which has at least one obtuse angle, then the corresponding parameter a s or a d can be considered to be equal to infinity.
- an individual distance a i of an individual region of the useful active area is equal to the limit distance delimiting the rectangle of the useful active area, then the individual distance a i is considered to be equal to infinity, for example.
- an electrical parameter P of the transistor is determined from an equation involving: the value of the electrical parameter determined for a required minimum distance of the active area, the value of the stress parameter of the transistor, the value of the required minimum distance, and a coefficient associated with the electrical parameter and depending on the width and the length of the channel of the transistor.
- determining the coefficient CP L,W includes the following steps, for example:
- the present invention further provides a system for modeling an integrated circuit including at least one insulated-gate field-effect transistor.
- the system preferably includes generator means adapted to define a parameter representing mechanical stresses applied to the active area of the transistor and processing means adapted to determine at least some of the electrical parameters of the transistor taking account of the stress parameter.
- the generator means is adapted to define a useful active area as some or the whole of the active area and the stress parameter is a geometrical parameter a eq representing a distance in the direction of the length of the channel of the transistor between the gate of the transistor and the edge of the useful active area.
- the useful active area of the transistor is rectangular and the gate is centered in the useful active area to define geometrically identical source and drain regions.
- the generator means defines the stress parameter a eq as the distance in the direction of the length of the channel between a flank of the gate and the corresponding edge of the source or drain region.
- the useful active area of the transistor includes geometrically different source and drain regions.
- the generator means defines a first geometrical parameter a s representing a first distance in the direction of the length of the channel between the gate and the edge of the source region and a second geometrical parameter a d representing a distance in the direction of the length of the channel between the gate and the edge of the drain region.
- the generator means defines the stress parameter a eq by an equation linking the first geometrical parameter and the second geometrical parameter.
- the processing means defines an electrical parameter of the transistor by an equation involving: the value of the electrical parameter determined for a reference distance, for example a required minimum distance of the active area, the value of the stress parameter of the transistor, the value of the reference distance, for example the required minimum distance, and a coefficient associated with the electrical parameter and depending on the width and the length of the channel of the transistor.
- the modeling device then includes a plurality of reference transistors having different reference values Wref, Lref for the channel width and length and different values for the stress parameter.
- processing means advantageously includes:
- the present invention preferably also adjusts the geometry of the active area of the transistor as a function of a required value of an electrical parameter, for example the carrier mobility, threshold voltage, etc.
- the present invention also provides a method of producing an integrated circuit including at least one insulated-gate field-effect transistor, in which the geometry of an active area of the transistor is defined using a parameter representing mechanical stresses applied to the active area, allowing for a required value of at least one electrical parameter of the transistor determined by a modeling method as defined hereinabove and allowing for the stress parameter.
- the geometry of an active area of a transistor can be adjusted to optimize the transistor in terms of mobility, for example, which will have the further consequence of reducing the drain/source resistance, which is doubly beneficial in the case of a MOSFET.
- a useful active area is defined as some or the whole of the active area and the stress parameter is a geometrical parameter a eq representing a distance in the direction of the length of the channel of the transistor between the gate of the transistor and the edge of the useful active area.
- the transistor is an NMOS transistor and the geometrical parameter a eq is more than twice a minimum distance a min required for a contact terminal in the active area, an improvement in carrier mobility in particular is obtained, compared to a transistor in which the length of the active area is equal to the required minimum distance.
- the integrated circuit includes at least one block including a plurality of NMOS transistors for more than 80% of which the geometrical parameter a eq is more than twice the minimum distance, the whole of the block of the integrated circuit is considered to have an advantage in terms of the mobility criterion in particular.
- the transistor is a PMOS transistor.
- the geometrical parameter a eq is then preferably less than twice the required minimum distance.
- this advantage with regard to the mobility criterion in particular also applies to an integrated circuit including at least one block including a plurality of PMOS transistors of which more than 80% have their geometrical parameter a eq less than twice the required minimum distance, for example.
- the present invention also provides an integrated circuit including at least one insulated-gate field-effect transistor.
- the active area of the transistor includes a useful active area defined as a portion or the whole of the active area of the transistor and the distance a eq in the direction of the length of the channel of the transistor between the gate of the transistor and the edge of the useful active area is different from a required minimum distance a min for a contact terminal on the active area.
- the transistor is an NMOS transistor and the distance a eq is greater than twice the minimum distance a min .
- the integrated circuit includes at least one block including a plurality of NMOS transistors and more than 80% of the NMOS transistors have their geometrical parameter a eq greater than twice the minimum distance a min .
- the transistor is a PMOS transistor and the distance a eq is less than twice the minimum distance a min .
- the integrated circuit includes at least one block including a plurality of PMOS transistors and more than 80% of the PMOS transistors have their distance a eq less than twice the minimum distance a min .
- the useful active area can be the portion of the active area within a rectangle whose lateral dimension in the direction of the width of the channel is equal to the width of the channel and each edge of which in the direction of the width of the channel is at a predetermined limit distance from the corresponding flank of the gate, for example of the order of ten times the required minimum distance a min .
- FIG. 1 shows generally a modeling system according to a preferred embodiment of the present invention.
- generator means MLB produces a stress parameter representing mechanical stresses applied to the active area of a transistor from the layout diagram of the transistor.
- the generator means can consist of an extractor (known to the person skilled in the art) which extracts from transistor layout diagrams dimensional parameters of the transistor, for example the length and the width of the channel, as well as information on connections.
- processing means MT determines at least some of the electrical parameters of the transistor P allowing for the stress parameter.
- the electrical parameter P can be the low-field carrier mobility ⁇ 0 at room temperature, the threshold voltage Vth 0 at zero gate/source voltage and for a long channel, or the stray source/drain resistance Rdsw per unit width of the channel.
- These electrical parameters P that take account of the stresses applied to the active area of the transistor can then be injected into a standard BSIM simulation model, such as the BSIM3v3.2 model from the University of Berkeley previously cited.
- the model can then be used to calculate other, more sophisticated parameters, such as the effective mobility ⁇ eff , the drain/source resistance Rds, and the threshold voltage Vth.
- the parameters obtained from the BSIM model also allow for stresses applied to the active area of the transistor.
- the stress parameter a eq is defined as the distance a in the direction of the length L of the channel between a flank FLC of the gate and the corresponding edge BRD of the source or drain region, here the source region. Note that this distance a can be different from a minimum distance a min required for producing a contact terminal CT in the source or drain region.
- FIG. 3 shows the variation of a function of the distance a of the ratio between the mobility ⁇ 0 for the value a and the mobility ⁇ 0 for the value a min .
- the mobility ⁇ 0 increases with a for an NMOS transistor (curve C 1 NMOS) and decreases with a for a PMOS transistor (curve C 1 PMOS).
- the mobility would increase if a were less than a min .
- a first geometrical parameter a s is preferably defined representing a first distance in the direction of the length of the channel between the gate and the edge of the source region.
- a second geometrical parameter a d is preferably defined representing a distance in the direction of the length of the channel between the gate and the edge of the drain region.
- the source and drain regions be geometrically different, but they can also be irregular, as is the case in FIG. 4 a or in FIGS. 5 a and 6 .
- Geometrically irregular source and drain areas having acute angles ANGF as shown in FIG. 4 a and on the right-hand side of FIG. 5 a , are distinguished from those having obtuse angles ANGO, as shown on the left-hand side of FIG. 5 a and in FIG. 6 .
- FIG. 4 a shows a source region S and a drain region D, each lateral side of which is free of obtuse angles and defines with the perpendicular edge of the area concerned an acute angle ANGF, here an angle equal to 90°.
- Each individual region RG i has an individual width W i and an individual edge BEL i at an individual distance a i in the direction of the length L of the channel from the gate GR.
- the drain region D is divided into four individual regions having the individual width W i and whose extreme edge is at an individual distance b i from the corresponding flank of the gate GR.
- FIG. 4 a TMOS transistor is then equivalent to the FIG. 4 b TMOS transistor.
- the stress parameter a eq is then defined by equation (I) above. From the modeling point of view, the FIG. 4 a TMOS transistor is then equivalent to the FIG. 4 c TMOS transistor having a regular and rectangular active area with a centered gate GR.
- the parameter a eq can be very much greater than the parameter a min or much less than the parameter a min .
- Irregular source or drain surfaces having obtuse angles ANGO are described next with reference to FIGS. 5 a to 7 .
- an obtuse angle ANGO here an angle of 270°
- the corresponding geometrical parameter a s or a d is preferably then taken as equal to infinity.
- the TMOS transistor that is geometrically equivalent from the modeling point of view to the FIG. 5 a TMOS transistor is that shown in FIG. 5 b with the parameter a s equal to infinity and the parameter a d defined by the above equation III.
- the TMOS transistor finally equivalent from the modeling point of view to the FIG. 5 a transistor is the FIG. 7 TMOS transistor in which a eq is still defined by the above equation I but in this instance is equal to 2a d , since a s is equal to infinity.
- the source and drain regions both have obtuse angles ANGO. Consequently, the two parameters a s and a d are equal to infinity and the parameter a eq of the equivalent TMOS transistor ( FIG. 7 ) is, in theory, still defined by the above equation I and is in practice equal to infinity, since a s and a d are themselves equal to infinity.
- the active area ZA of a TMOS transistor is particularly complex, as is the case in FIG. 8 for example, it is then preferable to define a “useful” active area ZAU inside the active area of the transistor, which is contained within a rectangle each of whose edges BLZ in the direction of the width W of the channel is at a predetermined limit distance from the corresponding flank of the gate, which distance is here equal to 10a min .
- the lateral dimension of this rectangle is equal to the width W of the channel.
- the value 10a min is a good compromise between the improvement in mobility that can be hoped for, for example, and the simplicity of the modeling. Beyond this value 10a min , the improvement in mobility is very slight, as shown in the curve C 1 NMOS in FIG. 3 .
- the procedure is then as previously described, possibly dividing the source and drain regions into n individual regions, here three individual regions defining three individual transistors T 1 , T 2 , T 3 .
- an individual distance a i or b i is then preferably considered equal to infinity if it is equal to the limit distance 10a min .
- the parameters a s and a d of the TMOS transistor limited to the useful active area are then determined as previously described.
- a d W/ ( W 3 /b 3 ) (V) since the distances b 1 and b 2 are equal to infinity.
- the processing means determines the electrical parameter of the transistor P.
- the procedure shown in FIG. 10 is advantageously used to determine the coefficient CP L,W associated with the parameter P.
- test or reference transistors are produced (step 100 ) with different reference values W ref and L ref for the width and the length of the channel and different values for the stress parameter a eq .
- Conventional measuring systems MMS are then used to measure the value of the electrical parameter P of concern for each reference transistor produced (step 101 ). For example, a mobility or a threshold voltage can be measured on a reference transistor using the known Hammer method.
- Second calculation means MC 2 determines (step 103 ) the coefficient CP L,W from the reference coefficients CP Lref , W ref , allowing for the width W and the length L of the channel of the transistor, possibly using interpolation.
- the present invention can also be used to produce integrated circuits including MOS transistors in which the geometry of the active area of the transistors can be adjusted as a function of a required value of an electrical parameter of the transistor, for example the mobility ( FIG. 11 ).
- step 111 for a required mobility (step 110 ) and for a chosen channel width and length for the transistor, application (step 111 ) of the simulation model according to the present invention described above delivers the value of the stress parameter a eq .
- the geometry of the active area of the transistor can then be defined (step 112 ).
- FIG. 12 shows a diagram of the layout diagram of a basic NAND gate cell CL 1 with two inputs (NAND 2 gate).
- the cell conventionally includes two PMOS transistors PMOS 1 and PMOS 2 and two NMOS transistors NMOS 1 and NMOS 2 .
- the first input IN 1 of the cell CL 1 is taken to the gates GR 1 of the two transistors PMOS 1 and NMOS 1 and the second input IN 2 of the cell is taken to the gates GR 2 of the two transistors PMOS 2 and NMOS 2 .
- the output OUT of the cell CL 1 is taken from the common source region of the transistors PMOS 1 and PMOS 2 .
- FIG. 12 shows that the respective lengths in the direction of the length of the channel of the source and drain areas of the transistors are made equal to the minimum distance a min . Likewise, the spacing between the gates is made equal to a minimum value min. Consequently, this kind of cell is produced applying a high density criterion.
- the stress parameter a eq is greater than the parameter a min and less than twice that parameter.
- FIG. 13 shows that the source regions of the transistors PMOS 1 and PMOS 2 are separated by the distance min. Also, the length of these source and drain regions has been made equal to a min . Consequently, the stress parameter a eq for these two PMOS transistors is equal to a min .
- the width of the source regions of the NMOS transistors has been increased to 2a min . Consequently, the stress parameter a eq for the two NMOS transistors is more than twice the required minimum distance a min .
- the cell CL 2 therefore, has a higher mobility than the cell CL 1 .
- the cell CL 3 ( FIG. 14 ), which is also a NAND 2 cell, has an even higher mobility. This is because the active areas of the transistors PMOS 1 and PMOS 2 have a constriction between the contact terminals and the width of this restriction is less than the distance a min . Consequently, the stress parameter a eq for the two PMOS transistors is less than the required minimum distance a min .
- the active areas of the NMOS transistors have obtuse angles, which makes the parameter a eq equal to infinity.
- the present invention is not limited to the embodiments and applications described above, and encompasses all variants thereof.
- the determination of the parameter P has been described above using a reference value Pa min which is the value of the parameter for the reference value a min .
- a different reference value could be used, for example the value of the parameter for a reference distance other than a min .
- the definition of the electrical parameter P is not limited to the above equation VI.
- Other equations involving the value of the parameter P for the reference distance and the coefficient depending on the width and the length of the channel could be envisaged for some parameters, such as the threshold voltage.
- the correction of the threshold voltage Vth in the BSIM3v3.2 model entails correcting only the parameter Vth 0 (threshold voltage at zero gate/source voltage and for a large channel width), whereas using a multiplier correction defined by equation VI would necessitate previous correction of the parameters Vth 0 , K 2 , K 2 , K 3 , K 3 b , Dvt 0 , Dvt 0 w , Eta 0 , Etab.
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Abstract
Description
-
- Vth0: threshold voltage at zero gate/source voltage and for a large channel width,
- K1: first order body effect coefficient,
- K2: second order body effect coefficient,
- K3: narrow channel width coefficient,
- K3 b: K3 substrate effect coefficient,
- Dvt0: first coefficient of short channel effect on threshold voltage,
- Dvt0W: first coefficient of short channel effect on threshold voltage for a short channel length,
- Eta0: drain-induced barrier lowering (DIBL) coefficient in the subthreshold region, and
- Etab: body bias coefficient for the DIBL effect in the subthreshold region.
Once determined by the method according to the present invention allowing for mechanical stresses, such parameters are injected into the BSIM3v3.2 model to determine the threshold voltage Vth.
where W is the width of the channel of the transistor.
P=Pa min(1+CP L,W(1−a min /a eq))
in which Pamin is the value of the electrical parameter P determined for the required minimum distance amin of the active area and CPL,W is the coefficient associated with the parameter P.
-
- reference transistors are produced having different reference values Wref, Lref for the width and the length of the channel and different values for the stress parameter,
- the value of the electrical parameter P concerned for each reference transducer produced is measured,
- a reference coefficient CPLref,Wref is determined for each pair of values Wref, Lref, being the slope of a straight line whose equation is Y=1+CPLref,Wref X, in which Y=P/Pamin and X=1−amin/aeq, and
- the coefficient CPL,W is determined from the reference coefficients CPLref,Wref allowing for the width W and the length L of the channel of the transistor, possibly using interpolation.
-
- measuring means for measuring the value of the electrical parameter P for each reference transistor produced,
- first calculator means for calculating for each pair of values Wref, Lref a reference coefficient CPLref,Wref defined as the slope of the straight line of the equation Y=1+CPLref,Wref X, in which Y=P/Pamin and X=1−amin/aeq, and
- second calculator means for calculating the coefficient CPL,W from the reference coefficients CPLref,Wref taking account of the width W and the length L of the channel of the transistor, possibly using interpolation.
a eq=1/(½a s+½a d) (I)
in which W is the total width of the channel.
a s =W/(W 1 /a 1) (IV)
since the distances a2 and a3 are equal to infinity.
a d =W/(W 3 /b 3) (V)
since the distances b1 and b2 are equal to infinity.
P=Pa min(1+CP L,W(1−a min /a eq)) (VI)
in which Pamin is the value of the electrical parameter P determined for the required minimum distance amin of the active area and CPL,W is a coefficient associated with the electrical parameter P and depending on the width W and the length L of the channel of the transistor.
Y=1+CP Lref,Wref X
Claims (75)
1/(½a s+½a d).
1/(½a s+½a d).
1/(½a s+½a d).
1/(½a s+½a d).
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Also Published As
Publication number | Publication date |
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EP2363818A3 (en) | 2013-09-25 |
US20030173588A1 (en) | 2003-09-18 |
EP1327944A1 (en) | 2003-07-16 |
US20090055152A1 (en) | 2009-02-26 |
JP2003264242A (en) | 2003-09-19 |
US7996202B2 (en) | 2011-08-09 |
FR2834575A1 (en) | 2003-07-11 |
JP5148354B2 (en) | 2013-02-20 |
EP2363818A2 (en) | 2011-09-07 |
FR2834575B1 (en) | 2004-07-09 |
JP2008252105A (en) | 2008-10-16 |
JP4145147B2 (en) | 2008-09-03 |
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