JP2003264236A - Semiconductor memory and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a Ta<SB>2</SB>O<SB>5</SB>dielectric film is preferably formed on a Cu electrode when an effective MIM structure capacitor is formed by applying LSI for mix installment, but since Cu has a large diffusion coefficient and low heat resistance or oxidation resistance, electric characteristics of the capacitor deteriorate. <P>SOLUTION: Since diffusion and oxidation of Cu can be controlled by inserting an anti-reaction layer of Ta between a Cu-interconnect and a Ta<SB>2</SB>O<SB>5</SB>dielectric film, leak current density of the capacitor can be reduced. Since deficiency of oxygen in the Ta<SB>2</SB>O<SB>5</SB>dielectric film can be repaired while controlling oxidation of an underlying layer by performing post-heat-treatment of the Ta<SB>2</SB>O<SB>5</SB>dielectric film in an inert atmosphere, variation in the capacitance of the capacitor due to hysteresis and voltage can be reduced. Since an MIM structure capacitor employing a Ta<SB>2</SB>O<SB>5</SB>film having a high permittivity can be formed on the Cu-interconnect, a high integration, low cost LSI for mix installment can be realized. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oxide dielectric capacitor which is effective when applied to a semiconductor device in which a digital logic device, a high frequency analog device and a memory are mounted together.

[0002]

2. Description of the Related Art For the purpose of application to mobile and digital home electronics related LSIs, it is considered to mount a digital logic device, a radio frequency (RF) analog device and a memory together in one chip. Digital logic devices are composed of MOS transistors, but RF analog devices and memories also require elements such as capacitors.

In order to make the above different devices into one chip, it is necessary to integrate the manufacturing processes. For example, a technique for forming a capacitor used for an analog device or a memory while ensuring compatibility with a logic process is essential.

In logic devices, the use of copper (Cu) as a wiring material has been studied in order to reduce wiring resistance. Therefore, in order to integrate the manufacturing process, it is necessary to form a capacitor on the Cu wiring. In particular, Cu wiring is MIM (Metal-Insul).
If it is used as an electrode of an attor-metal structure capacitor, the additional process can be minimized.

Further, if a high dielectric material such as tantalum pentoxide (Ta ₂ O ₅ ) is applied as the capacitor dielectric film, the capacitor area can be reduced, so that high integration of the LSI can be realized.

That is, a highly integrated and low cost embedded LSI
In order to realize the above, it is desirable to use Cu wiring used in a digital logic device as an electrode of a MIM structure capacitor used in an RF analog device or a memory, and to use Ta ₂ O ₅ as a capacitor dielectric film.

Since the Ta ₂ O ₅ film is an oxide, it must be formed in an oxidizing atmosphere. Further, in order to improve the electrical characteristics of _{the Ta} 2 _{O 5} film, it is necessary to perform heat treatment after the formation of _{the Ta} 2 _{O 5} film.

[0008]

M using Cu as an electrode
Problems in forming an IM structure capacitor will be described.

The first problem is that Cu has a large diffusion coefficient.
That's a good thing. Therefore, Ta_TwoO ₅During film formation and
Cu diffuses into the capacitor dielectric film during the post heat treatment,
The leakage current of the capacitor may increase. The second
The problem is that Cu has low heat resistance and oxidation resistance.
It Ta_TwoO₅During the formation of the film and the post heat treatment, Cu is
Once formed, a high resistance layer is formed in series with the capacitor
Therefore, the high frequency characteristics of the capacitor may deteriorate.
It

Under the above circumstances, the first problem to be solved by the present invention is that even when a material having a large diffusion coefficient called Cu is used as the electrode of the MIM structure capacitor, the leakage current due to the diffusion of Cu. It is to suppress the increase of. For this purpose, it is necessary to insert a reaction preventive layer between Cu and Ta ₂ O ₅ . One of the objects of the present invention is to provide a suitable material for the reaction-preventing layer.

A second problem to be solved by the present invention is
Ta ₂ O ₅ having high electrical characteristics while suppressing Cu oxidation
Forming a film. One of the means for preventing the oxidation of Cu is to prevent oxygen from reaching the Cu electrode. The reaction prevention layer described in the first problem can also serve as a diffusion prevention layer for oxygen. That is, it is necessary to select, as the diffusion prevention layer, a material capable of suppressing the diffusion of both Cu and oxygen.

The second means for preventing the oxidation of Cu is
Ta_TwoO₅Film formation and post heat treatment are performed under conditions of low oxidizability.
Is to be done in. However, Ta_TwoO₅The film is oxide
Therefore, if oxygen vacancies are formed in the film, the electrical characteristics will be poor.
Down. Therefore, Ta_TwoO ₅Film formation conditions and post heat treatment
The conditions should be examined after considering the characteristics of the above reaction preventive film.
Need to That is, one of the objects of the present invention is to select
Suitable Ta on the reaction prevention film_TwoO₅Film formation conditions and post heat
It is to provide processing conditions.

Here, the problems to be solved by the present invention will be summarized. In order to form an effective MIM structure capacitor by applying it to a semiconductor device in which a digital logic device and a high frequency analog device or a memory are mounted together, it is necessary to use Cu as an electrode and use a Ta ₂ O ₅ film as a dielectric film. desirable. However, Cu has a problem that it has a large diffusion coefficient and low heat resistance and oxidation resistance. Therefore, selection of the material of the diffusion prevention layer inserted between the Cu electrode and the Ta ₂ O ₅ film,
The formation of a Ta ₂ O ₅ film and optimization of heat treatment conditions are issues.

[0014]

In order to solve the above problems, the present invention uses the following means.

The MIM capacitor structure of the present invention includes a first step of forming a Ta film on the Cu electrode, a second step of forming a _{the Ta} 2 _{O 5} film on the Ta layer, the _Ta 2 _{O 5}
A third step of heat treating the film in an inert atmosphere.

The Ta film formed in the first step is Cu
And has a function as an oxygen diffusion preventing layer. In a MIM structure capacitor, it is known to insert a diffusion prevention layer between Cu and a capacitor dielectric film. For example, Japanese Patent Laid-Open No. 2001-237375 and US Pat.
No. 0, and US Pat. No. 6,168,991 B1. However, in these known examples, Ti, W, etc. are listed as materials for the diffusion prevention layer in addition to Ta, and the purpose of the diffusion prevention layers in these prior art documents is to prevent diffusion of Cu. Also, regarding the function of reaction prevention,
It is limited to metallic materials such as Cu, and the diffusion prevention of oxygen is not considered or described.

The object of the present invention is to provide a material suitable as a reaction-preventing layer of a capacitor using Cu as an electrode and Ta ₂ O ₅ as a dielectric film, and to show an optimum forming method thereof. The main focus of the invention is different from the literature.

The following are three reasons why Ta is suitable.

The first reason is the capacitor dielectric film.
Ta_TwoO₅And adaptability. Ta _TwoO₅Formation time and
The surface of the reaction preventive layer should be prevented from being oxidized during the subsequent heat treatment.
I can't avoid it. Ta or Ta compound as reaction preventing layer
If selected, Ta_TwoO₅Was formed
Therefore, the capacitor characteristics do not change significantly. this
Therefore, Ta or TaN is used as the material of the reaction prevention layer.
Limited.

The second reason is compatibility with Cu which is an electrode. Comparing Ta and TaN, it is considered that the performance of preventing Cu diffusion is equivalent. However, TaN has a weaker adhesiveness with Cu than Ta, so that peeling may occur during post heat treatment of the Ta ₂ O ₅ film. For this reason,
Ta is more preferable as the reaction preventing layer of the MIM capacitor having the Ta ₂ O ₅ / Cu structure.

The third reason is the resistivity. The resistivity of Ta is about 10 μΩcm, while that of TaN is about 200.
μΩcm, which is larger than one digit. As the series resistance of the capacitor increases, the high frequency characteristic deteriorates. For this reason, it is desirable to use Ta having a low resistivity, especially for a high frequency analog device.

In the present invention, in addition to these basic physical properties, Ta or TaN was formed on a Cu electrode, and Ta ₂ O ₅ was formed as a dielectric film to compare the electrical characteristics of capacitors. As a result, the leakage current is smaller when Ta is used as the reaction prevention layer than when TaN is used.
Clarified that the capacity is large. Detailed data will be described later.

In Japanese Patent Laid-Open No. 2001-237375, Table 1 lists materials having a diffusion preventing function and compares the diffusion resistance temperatures. WN has a high diffusion resistance temperature of 700 ° C., and the examples also describe a method of forming a capacitor using WN as a diffusion prevention layer. From this table, it is easy to select TaN having the same diffusion resistance temperature of 700 ° C. or a material having a higher diffusion resistance temperature as the diffusion prevention layer. However, since the diffusion resistance temperature of Ta is described as 500 ° C. in this table,
Regarding the suitability of Ta as a diffusion preventing material between Cu and Ta ₂ O ₅ which is the main point of the present invention, it came to be in the classification of materials which are rather unsuitable than the optimum material. It cannot be easily inferred from the prior literature of 2001-237375.

As a method of forming the Ta ₂ O ₅ film, a chemical vapor deposition method (CVD method) and a sputtering method can be mentioned. In order to suppress the oxidation of the base, it is necessary to form the Ta ₂ O ₅ film at a low temperature. In the CVD method, a Ta ₂ O ₅ film is deposited on a heated substrate by using Ta organic metal such as pentoethoxy tantalum and oxygen as raw materials. A temperature of 400 ° C. or higher is necessary in order to sufficiently decompose the organic compound of Ta and reduce the amount of carbon remaining in the film.
Therefore, the base is easily oxidized in the formation of the Ta ₂ O ₅ film by the CVD method. On the other hand, in the case of the sputtering method, since the Ta ₂ O ₅ film having high insulation can be formed even when the substrate temperature is 300 ° C. or lower, the oxidation of the underlayer can be suppressed.

Therefore, it is desirable that the Ta ₂ O ₅ film forming step of the _second step is performed by a sputtering method at a forming temperature of 300 ° C. or lower. However, ALCVD
Method (Atomic Layer Chemical V
A formation method capable of lowering the temperature, such as apor Deposition) may be used.

In order to repair oxygen vacancies in the Ta ₂ O ₅ film and improve the capacitor characteristics, it is necessary to carry out a post heat treatment after forming the film. The higher the post heat treatment temperature is, the more the chemical reaction is activated.

Therefore, it is desirable that the heat treatment step of the Ta ₂ O ₅ film in the third step be performed at a higher temperature than the heat treatment step of the Ta ₂ O ₅ film in the _second step.

The post heat treatment is preferably performed in an inert atmosphere in order to suppress the oxidation of the underlayer. If oxygen in the formation of the Ta ₂ O ₅ film is only to be sufficiently supplied, it contains sufficient oxygen in the Ta ₂ O ₅ film. Therefore, the oxygen deficiency can be repaired even by the heat treatment in the inert atmosphere. However, the oxygen partial pressure in the post-heat treatment atmosphere may not be zero. The higher the oxygen partial pressure, the lower the temperature will be Ta ₂
Oxygen deficiency in the O ₅ film can be repaired. However, the underlying Ta
When the entire film is oxidized, the Cu electrode starts to be oxidized. Therefore, it is necessary to select an oxygen partial pressure at which at least a part of Ta remains. Further, if the post-heat treatment temperature is raised, the oxidizing power becomes stronger, so it is necessary to lower the oxygen partial pressure.

Next, the oxidation of the underlying Ta will be described.

Even if the substrate temperature is lowered by the sputtering method to suppress the oxidation of the underlayer, it is inevitable that Ta is oxidized by several nm. If Ta is oxidized, Ta ₂ O ₅
Since the film is formed, the capacitance of the capacitor is reduced. However, in order to form a Ta ₂ O ₅ film containing sufficient oxygen, it is inevitable that the underlying Ta is oxidized.

In addition to this, the underlying Ta is oxidized during the post heat treatment of the Ta ₂ O ₅ film. Even if the post heat treatment is performed in an inert atmosphere, the surface of the underlying Ta film is oxidized by the oxygen contained in the Ta ₂ O ₅ film. If oxygen is included in the atmosphere of the post heat treatment, the film thickness of oxidized Ta becomes large. T
Since the capacitance of the capacitor decreases as the film thickness of the a ₂ O ₅ film increases, it is desirable that the film thickness of oxidized Ta be small. However, if post-heat treatment is performed to the extent that oxygen deficiency in the Ta ₂ O ₅ film is repaired, it is unavoidable that the underlying Ta is oxidized.

For this reason, the surface of the Ta film is oxidized by 5 nm or more by the Ta ₂ O ₅ film forming step of the _second step and the Ta ₂ O ₅ film heat treatment step of the third step. As a result, Ta ₂ formed by the sputtering method
O ₅ and film, Ta is a two-layer structure of _Ta 2 _{O 5} film is formed by oxidation. The problem can be solved by using the above means.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION In order to demonstrate the effect of the present invention,
Cu as an electrode and Ta as a dielectric film_TwoO ₅Using M
An IM capacitor was formed and electrical characteristics were evaluated.

First, the process of forming a capacitor will be described with reference to FIG.

A film thickness of 5 nm is formed on the silicon substrate 1 by the DC sputtering method using a Ta metal target.
The TaN film 2 and the Ta film 3 having a film thickness of 25 nm were formed.
The TaN film 3 was formed by reactive sputtering in a mixed atmosphere of Ar and N ₂ .

Next, Cu having a thickness of 100 nm was used as an electrode.
A film 4 and a Ta film 5 having a film thickness of 25 nm as a reaction preventing layer were sequentially formed (FIG. 1A).

Next, a T 2 film having a thickness of 20 nm is formed by RF sputtering using a Ta ₂ O ₅ oxide target.
An a ₂ O ₅ film 6 was formed (FIG. 1 (b)). The formation conditions are
The formation temperature is 100 ° C., and the ratio of Ar gas and O ₂ gas is 1 :.
It is 1.

After forming the Ta ₂ O ₅ film 6, a post heat treatment was performed. The condition of the post heat treatment is 450 ° C. in N ₂ gas stream for 3 minutes.

After the post heat treatment, the Au upper electrode 7 is vapor-deposited,
The capacitor was completed (FIG. 1 (c)). The electrical characteristics will be described with reference to FIGS.

FIG. 2 is a diagram for explaining a change in leakage current density due to heat treatment in a capacitor in which a Ta ₂ O ₅ film is directly formed on a Cu electrode. When the heat treatment is not performed after forming the Ta ₂ O ₅ film (as-depo.), The leakage current density is very large. Further, even if the post heat treatment is performed in N ₂ at 450 ° C., the leakage current density remains large and hardly changes. It is considered that this is because the Cu film was oxidized during the formation of the Ta ₂ O ₅ film, and at the same time Cu having a large diffusion coefficient was diffused into the Ta ₂ O ₅ film.

FIG. 3 shows a capacitor in which a Ta film is formed as a reaction preventing layer between a Cu electrode and a Ta ₂ O ₅ film.
It is a figure explaining the change by heat treatment of a leak current density.

Compared to FIG. 2, the leakage current density when the heat treatment is not performed after the formation of the Ta ₂ O ₅ film (as-depo.) Is smaller by 6 digits or more. Further, the post-heat treatment at 450 ° C. in N ₂ reduces the leak current density particularly in the low voltage region. The reason that the leakage current density was greatly reduced by inserting Ta as the reaction preventing layer is considered to be that the oxidation and diffusion of the Cu electrode were prevented. Also, the reason why the leakage current density was reduced by the post heat treatment is considered to be that the oxygen deficiency in the Ta ₂ O ₅ film was repaired.

That is, it is clear that the leakage current density of the capacitor can be greatly reduced by inserting Ta as a reaction preventing layer between the Cu electrode and the Ta ₂ O ₅ film and subjecting the Ta ₂ O ₅ film to post heat treatment. became.

Next, it will be explained that the post heat treatment of the Ta ₂ O ₅ film is effective not only for the leakage current density but also for the voltage dependence of the capacitor capacitance.

FIG. 4 shows a capacitor in which a Ta film is formed as a reaction preventing layer between a Cu electrode and a Ta ₂ O ₅ film.
Formed is a diagram illustrating a Ta ₂ O ₅ film thickness dependency of the capacitance immediately after.

The voltage was changed from + 2V → -2V → + 2V and the capacitance of the capacitor was measured.

The smaller the film thickness of Ta ₂ O ₅ , the larger the capacity. However, hysteresis is observed at any film thickness. In addition, the smaller the film thickness of Ta ₂ O _5, the larger the hysteresis, and the change in the capacitance depending on the voltage also increases.
The occurrence of this hysteresis and the change of the capacitance due to the voltage cause deterioration of the device characteristics.

FIG. 5 shows a capacitor in which a Ta film is formed as a reaction preventing layer between a Cu electrode and a Ta ₂ O ₅ film.
Is a diagram illustrating a Ta ₂ O ₅ film thickness dependence of capacitance after heat treatment. Similar to FIG. 4, the voltage is + 2V → -2V →
The capacitance was measured while changing to + 2V.

As in the case of not performing the post heat treatment shown in FIG. 4, in FIG. 5, the smaller the film thickness of Ta ₂ O ₅ , the larger the capacity. However, by performing a post heat treatment,
Hysteresis disappears and the change in capacitance with voltage also decreases. It is considered that this is because the oxygen deficiency in the Ta ₂ O ₅ film was repaired by the post heat treatment.

That is, it is clear that by inserting a reaction preventive layer between the Cu electrode and the Ta ₂ O ₅ film and post-heat treating the Ta ₂ O ₅ film, the hysteresis of the capacitance and the change due to the voltage can be greatly reduced. became.

Next, the film thickness that is oxidized on the surface of the Ta film which is the reaction preventing layer will be described.

FIG. 6 shows a capacitor in which a Ta film is formed as a reaction preventing layer between a Cu electrode and a Ta ₂ O ₅ film.
Is a diagram illustrating a _Ta 2 _{O 5} film thickness dependency of the SiO ₂ equivalent thickness after the heat treatment.

The SiO ₂ converted film thickness is obtained by calculating the film thickness of the dielectric film from the capacitance of the capacitor assuming that the dielectric constant of the dielectric film of the capacitor is 3.82.

As shown in FIG. 6, by setting the Ta ₂ O ₅ film thickness on the abscissa and the SiO ₂ converted film thickness on the ordinate, the relative permittivity of the dielectric film can be obtained from the slope and The oxide film thickness of the underlayer can be obtained from the axis intercept.

From the inclination of FIG. 6, the relative permittivity of the dielectric film is found to be about 30. Further, from the section of FIG. 6, the oxide film thickness of the underlying layer is determined to be about 0.8 nm. T which is a reaction prevention layer
It is considered that when the a film is oxidized, a Ta ₂ O ₅ layer is formed on the film surface. Ta ₂ O formed by this oxidation
Assuming the relative permittivity of ₅ layers is about 30, the film thickness is about 6 nm.
Is required.

That is, Ta is formed on the Ta film which is the reaction preventing layer.
By forming a ₂ O ₅ film and performing a post heat treatment at 450 ° C. in an N ₂ atmosphere, the underlying Ta film is oxidized to about 6 nm.
It was revealed that the Ta ₂ O ₅ film of No. ₁ was newly formed.

As the film thickness of the Ta ₂ O ₅ film increases, the capacitance of the capacitor decreases, so it is desirable that the film thickness of oxidized Ta be small. However, if post-heat treatment is performed to the extent that oxygen deficiency in the Ta ₂ O ₅ film is repaired, it is unavoidable that the underlying Ta is oxidized.

As is clear from the above experimental results, Cu
Diffusion and oxidation of the Cu electrode is suppressed by inserting a reaction-preventing layer between the electrode and _{the Ta} 2 _{O 5} film, _Ta 2 _{O 5}
The oxygen deficiency in the Ta ₂ O ₅ film is repaired by post-heat treatment of the film, and as a result, the leakage current density of the capacitor is reduced, and in addition, the capacitance hysteresis and the change due to voltage are reduced.

[0059] In addition, a reaction preventing layer Ta result film is oxidized, and _{the Ta} 2 _{O 5} film formed by sputtering, Ta has a two-layer structure of _Ta 2 _{O 5} film is formed by oxidizing It becomes a dielectric film.

Next, a capacitor using TaN as a reaction preventing layer was formed and the electrical characteristics were compared.

First, the step of forming a capacitor will be described with reference to FIG.

Since the steps up to the formation of the Cu film 4 are the same as those in FIG. 1, they are omitted here.

After forming the Cu film 4, a TaN film 8 having a film thickness of 25 nm was formed as a reaction preventing layer.

Next, a T film having a thickness of 20 nm is formed by RF sputtering using a Ta ₂ O ₅ oxide target.
The a ₂ O ₅ film 6 was formed. The formation condition is that the formation temperature is 10
At 0 ° C., the ratio of Ar gas and O ₂ gas is 1: 1.

After forming the Ta ₂ O ₅ film 6, a post heat treatment was performed. The condition of the post heat treatment is 450 ° C. in N ₂ gas stream for 3 minutes.

After the post heat treatment, the Au upper electrode 7 is vapor-deposited,
The capacitor was completed (Fig. 7).

Although the Ta film is used as the reaction preventing layer in FIG. 1, it is different in that the TaN film is used as the reaction preventing layer in FIG.

The results of comparing the electrical characteristics will be described with reference to FIGS. 8 and 9.

FIG. 8 is a diagram comparing the effective electric field dependence of the leakage current density in a capacitor using Ta as a reaction preventing layer with a capacitor using TaN as a reaction preventing layer.

As is clear from FIG. 8, the leakage current density is smaller when Ta is used as the reaction preventing film than when TaN is used.

FIG. 9 is a diagram comparing the Ta ₂ O ₅ film thickness dependence of the SiO ₂ converted film thickness of a capacitor using Ta as a reaction preventing layer with a capacitor using TaN as a reaction preventing layer.

As is clear from FIG. 9, when Ta is used as the reaction preventing film, SiO is more effective than when TaN is used.
_{2 The} converted film thickness is small. In other words, the capacity is large.

As is clear from the above experimental results, Ta
_As the reaction preventing layer of the MIM capacitor having the ₂ O ₅ / Cu structure, Ta is preferable to TaN.

The effects of the present invention have been described above by showing the concrete experimental results. The film forming conditions and heat treatment conditions are as follows.
It goes without saying that changes can be made without departing from the scope of the present invention.

For example, the method of forming the Ta ₂ O ₅ film is not limited to the sputtering method, and the CVD method may be used. However, the formation temperature is 300 ° C in order to suppress the oxidation of the base.
The following is desirable.

The heat treatment temperature of the Ta ₂ O ₅ film is 45.
The temperature is not limited to 0 ° C., and may be higher than the formation temperature of the Ta ₂ O ₅ film. However, at a low temperature, the repair of oxygen vacancies in the Ta ₂ O ₅ film is insufficient, and at a high temperature, the oxidation of the underlayer becomes large.

The heat treatment atmosphere for the Ta ₂ O ₅ film is preferably an inert atmosphere, but the oxygen partial pressure may not be 0. However, if the underlying Ta film is entirely oxidized, the Cu electrode will be oxidized.
It is necessary to control the oxygen partial pressure to the extent that a part of it remains.

The upper electrode can be selected from Cu, Pt, and Ru, but Cu is preferable in view of the symmetry with the lower electrode. Further, like the lower electrode, it is necessary to insert a reaction preventive layer between the Ta ₂ O ₅ film and the upper electrode. The material of the reaction prevention layer on the upper electrode side can be arbitrarily selected as long as it can prevent the diffusion of Cu, but in view of symmetry, Ta is preferable. In this case, Cu / Ta / Ta ₂ O ₅ /
It has a Ta / Cu structure.

(Embodiment 1) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

The first embodiment will be described with reference to FIG. This is because, for example, a MISFET (Metal I
nsulator Semiconductor Fi
The present invention is applied to a method of manufacturing a semiconductor integrated circuit device in which an eldeffect transistor is formed.

First, an element isolation region, a MISFET, and a plug connected to the semiconductor region of the MISFET are formed on a single crystal silicon substrate. In this embodiment, the steps up to this point and the drawings are omitted, and FIG. 10 shows the steps after the plug formation. That is, the element isolation region, the MISFET, the plug connected to the semiconductor region of the MISFET, and the like are formed in the lower portion of FIG.

First, a silicon nitride film is deposited on the entire surface of a semiconductor substrate by, for example, a plasma CVD method to have a film thickness of about 1
An etch stopper film 9 of 00 nm is formed. The etch stopper film 9 is for avoiding damage to the lower layer and deterioration of the processing dimensional accuracy due to over-digging when forming a groove portion or a hole for forming a wiring in the upper insulating film. It is a thing.

Next, CVD is performed on the surface of the etch stopper film 9.
A silicon oxide (SiOF) film to which fluorine is added is deposited by the method, and the insulating film 10 having a thickness of about 400 nm is deposited. When a SiOF film is used as the insulating film 10, the SiOF film
Since the film is a low dielectric constant film, it is possible to reduce the overall dielectric constant of the wiring of the semiconductor integrated circuit device and improve the wiring delay.

Next, the etch stopper film 9 and the insulating film 1
0 is processed using a photolithography technique and a dry etching technique to form a wiring groove (groove portion).

Next, in order to remove the reaction layer on the surface of the plug exposed at the bottom of the wiring groove, surface treatment of the semiconductor substrate is performed by sputter etching in an argon (Ar) atmosphere. The sputter etching amount at this time is P-TE.
OS (Plasma Tetraethylortho
Silicate) Approximately 2 nm to 18 n in terms of oxide film
The thickness is about m, preferably about 10 nm. Although the case where the reaction layer on the surface of the plug is removed by sputter etching in an argon atmosphere has been described in the first embodiment, the reducing property such as hydrogen (H ₂ ) or carbon monoxide (CO) can be used. If the reaction layer can be sufficiently removed by annealing in a gas or a mixed atmosphere of a reducing gas and an inert gas, this annealing may be replaced with the sputter etching. In the case of annealing treatment, loss of the insulating film 10 due to sputter etching,
It is possible to prevent charging damage to the gate oxide film due to electrons.

Next, for example, a TaN film to be the barrier conductive film (first conductive film) 11a is deposited on the entire surface of the semiconductor substrate. The film thickness of the barrier conductive film 11a is set to about 2 nm to 18 nm, preferably about 10 nm on the surface of the insulating film 10 excluding the inside of the wiring groove.

Next, for example, a Ta film to be the barrier conductive film (second conductive film) 11b is deposited on the entire surface of the semiconductor substrate. The film thickness is about 10 nm to 40 nm, preferably about 2 nm on the surface of the insulating film 10 excluding the inside of the wiring groove.
It should be about 5 nm.

The barrier conductive films 11a and 11b may be deposited by a sputtering method, or a CVD (Chemical Vapor) using an inorganic or organic material.
It may be deposited by the Deposition method.

Next, a Cu seed film is deposited (not shown).
No). This seed film increases the temperature of the semiconductor substrate from about 0 ° C to 1 ° C.
Keep at about 00 ℃, preferably about 100 ℃,
10 ^-2Long-distance sputtering under pressure below about Pa
It is deposited by the ring method. The film thickness is inside the wiring groove
On the surface of the barrier conductive film 11b excluding
nm to about 200 nm, preferably about 150 nm
To be In this embodiment, the seed film
Illustrates the case of using long-distance sputtering method for deposition
However, by ionizing Cu sputtering atoms,
Ionization sputtering method to increase the directivity of tattering
May be used. The seed film is deposited by the CVD method.
You may go.

Next, a semiconductor substrate having a Cu seed film deposited thereon
A Cu film is formed on the entire surface of the plate so as to be embedded in the wiring groove,
The buried film and the seed film are combined to form a conductive film (third layer).
Conductive film) 11c. Even if the Cu embedded film is
For example, it is formed by electrolytic plating. As a plating solution,
For example, sulfuric acid (H_TwoSO_Four) To 10% copper sulfate (CuS
O _Four) And an additive to improve the coverage of the copper film
Use one. Electroplating is used to form the conductive film 11c.
When used, the growth rate can be electrically controlled, so wiring
Improving the coverage of the conductive film 11c inside the groove
You can

Although the case where the electroplating method is used for depositing the conductive film 11c is illustrated in the present embodiment, the electroless plating method may be used. When the electroless plating method is used, it is not necessary to apply an electric charge, so that the damage to the semiconductor substrate due to the electric field application can be reduced as compared with the case where the electrolytic plating method is used.

Further, subsequent to the step of forming the conductive film 11c, the copper film is fluidized by an annealing treatment, whereby the filling property of the conductive film 11c in the wiring groove can be further improved.

Next, the excess barrier conductive films 11a and 11b and the conductive film 11c on the insulating film 10 are removed, and the barrier conductive films 11a and 11b and the conductive film 1 are formed in the wiring trench.
The buried wiring 11 is formed by leaving 1c. The barrier conductive films 11a and 11b and the conductive film 11c are removed by polishing using the CMP method.

Then, after polishing abrasive grains and copper adhering to the surface of the semiconductor substrate are removed by two-step brush scrub cleaning using, for example, a 0.1% aqueous ammonia solution and pure water, the embedded wiring 11 and the insulating layer are insulated. A silicon nitride film is deposited on the film 10 to form a barrier insulating film 12a.
For depositing this silicon nitride film, for example, plasma CV is used.
The D method can be used, and the film thickness is about 50 nm. The barrier insulating film 12a has a function of suppressing diffusion of copper forming the conductive film 11c of the embedded wiring 11.
As a result, it is possible to prevent the diffusion of copper into the insulating film 10 and the insulating film 12b described later together with the barrier conductive films 11a and 11b, maintain their insulating properties, and improve the reliability of the semiconductor integrated circuit device. . The barrier insulating film 12a also functions as an etch stopper layer when etching is performed in a later step.

Next, an insulating film 12b having a film thickness of about 400 nm is deposited on the surface of the barrier insulating film 12a. The insulating film 12b is, for example, a SiOF film such as a fluorine-added CVD oxide film. When the SiOF film is used as the insulating film 12b, it is possible to reduce the overall permittivity of the wiring of the semiconductor integrated circuit device, and it is possible to improve the wiring delay.

Next, a silicon nitride film is deposited on the surface of the insulating film 12b by, for example, a plasma CVD method, and an etch stopper film 12c having a film thickness of about 50 nm is deposited. This etch stopper film 12c avoids damaging the lower layer and degrading the processing dimensional accuracy due to excessive digging when forming a groove or hole for forming a wiring in the insulating film 12d described later. It is for.

Then, for example, a SiOF film is deposited on the surface of the etch stopper film 12c to form an insulating film 12d,
The barrier insulating film 12a, the insulating film 12b, the etch stopper film 12c, and the insulating film 12d are combined to form the insulating film 12. The insulating film 12d is deposited by the CVD method and has a film thickness of, for example, about 300 nm. This insulating film 12
Similarly to the insulating film 12b, d has a function of lowering the overall dielectric constant of the wiring of the semiconductor integrated circuit device, and can improve the wiring delay.

Next, the embedded wiring 11 which is a lower layer wiring
Then, a connection hole (groove portion) 13a for connecting the embedded wiring 14 which is an upper layer wiring formed in a later step is formed. The connection hole 13a is formed by a photolithography process.
A photoresist film having the same shape as the connection hole pattern for connecting to the embedded wiring 11 is formed on the insulating film 12d,
A contact hole pattern is formed by a dry etching process using this as a mask. Then, the photoresist film is removed and a photolithography process is performed on the insulating film 12d.
A photoresist film having the same shape as the wiring groove pattern is formed, and the wiring groove (groove portion) 13b is formed by a dry etching process using the photoresist film as a mask (FIG. 10A).

Subsequently, sputter etching is performed to remove the reaction layer on the surface of the embedded wiring 11 exposed at the bottom of the connection hole 13a. The sputter etching amount at this time is about 2 nm to 18 nm in terms of the P-TEOS oxide film.
The thickness is preferably about 10 nm.

Next, a barrier conductive film (first conductive film) 14a made of, for example, a TaN film is deposited on the entire surface of the semiconductor substrate including the inside of the connection hole 13a and the wiring groove 13b. The thickness of the barrier conductive film 14a is set to about 2 nm to 18 nm, preferably about 10 nm on the surface of the insulating film 12 excluding the insides of the connection holes 13a and the wiring grooves 13b.

Next, a Ta film, which will be the barrier conductive film (second conductive film) 14b, is deposited by the same process as the process of depositing the barrier conductive film 11b.

The barrier conductive films 14a and 14b may be deposited by a sputtering method or a CVD method using an inorganic or organic material.

Then, for example, a copper film or a copper alloy film is deposited as a seed film (not shown). When the seed film is a copper alloy film, the alloy should contain about 80% by weight or more of Cu. The long distance sputtering method can be used for depositing the seed film. Alternatively, an ionization sputtering method may be used, or CV
The D method may be used.

Next, in the same step as the step of depositing the conductive film 11c, a Cu film is formed so as to be embedded in the wiring trench on the entire surface of the semiconductor substrate on which the Cu seed film is deposited,
The buried film and the seed film are combined to form a conductive film (third layer).
Conductive film) 14c. When the electroplating method is used to form the embedded film, the growth rate of the conductive film 14c can be electrically controlled, so that the coverage of the conductive film 14c inside the connection hole 13a and the wiring groove 13b can be improved. . In addition, although the case where the electrolytic plating method is used for depositing the conductive film 14c is illustrated in the present embodiment, the electroless plating method may be used. When the electroless plating method is used, it is not necessary to apply an electric field, and therefore damage to the semiconductor substrate due to the electric field application can be reduced as compared with the case where the electrolytic plating method is used.

Further, subsequent to the step of forming the conductive film 14c, the copper film is fluidized by an annealing process, so that the filling property of the conductive film 14c in the connection hole 13a and the wiring groove 13b is further improved. You can also

Then, the excess barrier conductive films 14a and 14b and the conductive film 14c on the insulating film 12d are removed,
The buried wiring 14 is formed by leaving the barrier conductive films 14a and 14b and the conductive film 14c inside the connection hole 13a and the wiring groove 13b. Barrier conductive film 14a,
The removal of 14b and the conductive film 14c is performed by polishing using the CMP method (FIG. 10B).

Then, polishing abrasive particles and copper adhering to the surface of the semiconductor substrate are removed by two-step brush scrub cleaning using, for example, a 0.1% aqueous ammonia solution and pure water.

Subsequently, sputter etching for removing the reaction layer on the surface of the buried wiring 14 is performed. The amount of sputter etching at this time is about 2 nm to 18 nm, preferably about 10 nm in terms of P-TEOS oxide film. Next, the Ta film 15 is deposited by the DC sputtering method using a Ta metal target. This T
The a film has a function as a diffusion prevention layer that suppresses diffusion of the conductive film 14c made of Cu. Further, it has a function of preventing the conductive film 14c made of Cu from being oxidized at the time of depositing the Ta ₂ O ₅ film 16 to be formed later and at the time of post-heat treatment.

In this embodiment, the case where the DC sputtering method is used for depositing the Ta film 15 has been exemplified.
The CVD method may be used. The film thickness of the Ta film 15 is
The thickness is about 10 nm to 50 nm, preferably about 25 nm.

Next, the Ta film 15 is processed into a desired shape by using the photolithography technique and the dry etching technique.

Next, a Ta ₂ O ₅ film 16 is deposited. The Ta ₂ O ₅ film 16 keeps the temperature of the semiconductor substrate about 0 ° C. to 30 ° C.
The temperature is maintained at about 0 ° C., preferably about 100 ° C., and the deposition is performed by the DC reactive sputtering method using a Ta metal target in a mixed atmosphere of Ar and O ₂ .

In this embodiment, the Ta ₂ O ₅ film 1 is used.
Although the case of using the DC reactive sputtering method for the deposition of 6 has been illustrated, other sputtering methods may be used,
The CVD method may be used. The film thickness of the Ta ₂ O ₅ film 16 is about 5 nm to 20 nm, preferably about 10 nm.
So that

Next, the Ta ₂ O ₅ film 16 is subjected to post heat treatment. The heat treatment is performed under a temperature condition of 300 ° C. or lower. Here, the heat treatment temperature is set to 300 ° C. or lower because Ta ₂ O
_This is because oxygen deficiency in the Ta ₂ O ₅ film can be repaired if the temperature is higher than the deposition temperature of the ₅ film. However, in order to obtain a Ta ₂ O ₅ film having good electrical characteristics, the temperature is preferably 400 ° C. or higher. The heat treatment atmosphere is preferably an inert atmosphere in order to suppress the oxidation of the underlying Ta.
For example, in a N ₂ gas atmosphere, a processing temperature of 300 ° C.
The conditions of 500 degreeC and processing time 1 minute-10 minutes can be illustrated.

Next, the Ta film 17 is deposited by the same process as the process of depositing the Ta film 15. This Ta film 17
Has a function of suppressing diffusion and oxidation of the Cu film 18 to be formed later.

Next, the Cu film 18 is deposited by the DC sputtering method using a Cu metal target.

In this embodiment, the case where the DC sputtering method is used for depositing the Cu film 18 is illustrated.
It can also be formed by a method similar to that of the conductive films 11c and 14c.

Next, the Cu film 18, the Ta film 17, and the Ta ₂ O ₅ film 16 are processed into a desired shape by using the photolithography technique and the dry etching technique.

Ta film 15, Ta ₂ O ₅ film 16, Ta film 1
7 and the Cu film 18 are processed to form a lower electrode (conductive film 14c) made of Cu and a reaction prevention layer (T
a film 15), a dielectric layer made of _{Ta 2 O 5 (Ta 2 O} 5
The MIM structure capacitor including the film 16), the reaction preventing layer (Ta film 17) made of Ta, and the upper electrode (Cu film 18) made of Cu is completed.

Here, the Ta film 15, Ta ₂ O ₅ film 16,
A procedure for processing the Ta film 17 and the Cu film 18 will be added.

In the present embodiment, after processing the Ta film 15, the Ta ₂ O ₅ film 16, the Ta film 17, and the Cu film are formed.
The film 18 is formed, and then the Ta ₂ O ₅ film 16 and the Ta film 1 are formed.
7 and the step of collectively processing the Cu film 18 is illustrated, but the present invention is not limited to this as long as it is processed into a shape that does not lose the function as a capacitor. However, the Ta film 15
Needs to be processed into a shape larger than the conductive film 14c made of Cu. This is a conductive film 14 made of Cu.
This is because when c is exposed, it diffuses into the insulating film. Further, the Cu film 18 is formed of the Ta film 17 by the Ta ₂ O ₅ film 1.
Must be separated from 6. This is because if some of them are in contact with each other, Cu diffuses into the Ta ₂ O ₅ film 16.

Further, in this embodiment, Ta ₂ O is used.
_Although the process of collectively processing the _five films 16, the Ta film 17, and the Cu film 18 is illustrated, it may be processed one layer at a time,
It may be processed by dividing into one layer and two layers. Further, the processed shapes may be different from each other.

Through the above steps, the semiconductor integrated circuit device of this embodiment is substantially completed. A plan view of the structure shown in the cross-sectional view of FIG. 10 is shown in FIG.

According to the first embodiment, Cu wiring and Ta ₂ O are used.
By inserting a reaction preventive layer made of Ta between the ₅ dielectric films, Cu diffusion and oxidation can be suppressed, so that the leakage current density of the capacitor can be reduced. Also,
By post-heat treating the Ta ₂ O ₅ dielectric film in an inert atmosphere, oxygen vacancies in the Ta ₂ O ₅ dielectric film can be repaired while suppressing the oxidation of the underlying layer. The change can be reduced. As a result, a highly integrated and low cost mixed LSI can be realized.

Needless to say, according to the present invention, not only the above-described embodiments but also various means mentioned in the section of means for solving the problems in the present specification can be applied.

(Second Embodiment) The second embodiment of the invention is RF
1 is an example of a semiconductor integrated circuit in which an analog device and a CMOS logic device are integrated in one chip, and is a cross-sectional structure diagram of a logic part, an analog part, and a memory part.
In the second embodiment of the present invention, 112 in FIG.
Reference numerals 113 and 114 correspond to the MIM capacitor according to the first embodiment of the invention. Here, the description will be given on the assumption of the CMOS structure, but it goes without saying that the present invention can be applied to a so-called BiCMOS structure in which bipolar transistors and CMOS are mixed. In FIG. 11, a logic part, an analog part, and a memory part are formed on one P-type silicon substrate P-SUB. One P
The N-well region 10 is provided inside the silicon substrate P-SUB.
2, 103, 104 are formed in an island shape, and N well regions 105, 106,
107 and P-well regions 108, 109, 110 are formed as shown. In addition, N well regions 105, 1
A PMOS transistor is formed at 06 and 107, and an NMOS transistor is formed at P well regions 108, 109, and 110, and a feeding portion to the N well and P well regions is shown adjacent to the transistor. Further, the resistance component formed by the polycrystalline silicon wiring layer 115 is shown in the analog portion, and the gate oxide film 128, the silicide layer 126, the side spacers 127, the silicon nitride film 1 are shown in other areas.
25 etc. are shown in the figure.

In FIG. 11, if the transistor is silicidized like the logic portion, the leak current in the diffusion layer region may increase. Therefore, if a silicided transistor is used in a memory cell, the data retention characteristic of the memory cell may be deteriorated. In such a case, the memory cell may be formed without siliciding the NMOS transistor formed in the P well region 110 as shown in FIG. Also, although not particularly shown,
Since the resistance value of the polycrystalline silicon wiring layer 115 becomes large without silicidation, the polycrystalline silicon wiring 115
A so-called polymetal structure in which tungsten W or the like is laminated may be used. Further, the polycrystalline silicon wiring layer 115
A transistor structure in which only the upper portion is selectively silicified and the diffusion layer region is not silicidized may be used. Of course, as long as the leakage current does not adversely affect the retention characteristics, the silicide may be formed similarly to the transistor in the logic portion. In that case, an additional mask for preventing silicidation is not required, and the cost can be further reduced.

The well structure shown in FIG. 11 is a so-called triple well structure, which includes a logic section, an analog section,
The memory portions are designated as N well regions 102, 103, 10 respectively.
Separated in 4. As a result, the logic area, the analog area, and the memory area can be electrically separated from each other, so that mutual interference can be avoided and stable operation can be achieved. Further, it is possible to set the potentials of the N well and the P well that are suitable for the respective operating voltages. Of course, when the triple well structure is not required, a simpler structure without the N well regions 102, 103, 104 may be used, or only the memory part or only the memory part and the analog part may be the N well. Various modifications can be made as necessary, such as separating the regions 103 and 104 or surrounding the two regions with the same N well region.

In FIG. 11, the broken line shown on the substrate is the Cu wiring layers (120 to 124) and their contact layers.
The positions of (116 to 119) are shown. The MIM capacitors 112, 113, 114 are used in the logic section, the analog section, and the memory section, respectively. For example, by providing a capacitor in the wiring connected to the power supply in the logic unit, the capacitance of the power supply can be increased to stabilize the power supply. Of course, this can also be used for the analog section and the memory section. Further, it can be applied to a capacitor element in an analog section and a memory cell in a memory section as described later.

In the conventional 1T1C type memory cell,
Polycrystalline silicon, which has excellent heat resistance and the like, is mainly used as the lower electrode, and a metal having an oxidation resistance such as TiN is used as the upper electrode to form the memory capacitor.
Therefore, it has been difficult to use the Cu wiring layer used in the logic for the electrode of the capacitor. The MIM capacitor of this embodiment has, for example, C of the third layer as the lower electrode.
The u wiring layer 122 is used.

After forming a Cu wiring layer, a reaction preventing layer is formed.
To form a Ta film. Then, Ta _TwoO₅Shaped dielectric film
And heat-treat. Then, a Ta film is formed as a reaction preventing layer.
Is formed, and an upper electrode is further formed. At this time
The pole is between the Cu wiring layer 123 and the Cu wiring layer 122 of the fourth layer.
It is formed in the layer of the via hole 118 in between. in this way,
If a Cu wiring layer is used for the lower electrode of the capacitor, the logic
Capacitor piece in the clock section, analog section, and memory section
No special process is required for forming the other electrode.
In addition, in the memory section, 1T having the conventional three-dimensional structure
Unlike the 1C type memory cell, the capacitor has a planar structure.
Therefore, the Cu wiring layer of logic can be used easily, and
The flat structure makes it easy to process and yield
A capacitor can be formed well.

In the second embodiment, since the capacitor has a simple planar structure, the process cost can be reduced because it is easy to process. In addition, the Cu wiring layer is MI
By using it for the electrode of the M capacitor, the capacitors of the memory part, the logic part, and the analog part can be formed with the same structure and the same material, and the cost can be reduced and the reliability and the yield can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

[0133]

According to the present invention, a MIM structure capacitor using a Ta ₂ O ₅ film having a high dielectric constant can be formed on Cu wiring. Therefore, a highly integrated and low cost embedded LSI can be realized.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view of a process of forming a capacitor in which a Ta film is formed as a reaction preventing layer between a Cu electrode and a Ta ₂ O ₅ film.

FIG. 2 is a diagram illustrating a change in leakage current density due to heat treatment in a capacitor in which a Ta ₂ O ₅ film is directly formed on a Cu electrode.

FIG. 3 is a diagram illustrating a change in leakage current density due to heat treatment in a capacitor in which a Ta film is formed as a reaction preventing layer between a Cu electrode and a Ta ₂ O ₅ film.

FIG. 4 is a diagram for explaining the Ta ₂ O ₅ film thickness dependence of the capacitor capacitance immediately after formation in a capacitor in which a Ta film is formed as a reaction preventing layer between a Cu electrode and a Ta ₂ O ₅ film.

FIG. 5 is a diagram illustrating the Ta ₂ O ₅ film thickness dependence of the capacitor capacitance after heat treatment in a capacitor in which a Ta film is formed as a reaction preventing layer between a Cu electrode and a Ta ₂ O ₅ film.

FIG. 6 shows the S after heat treatment in a capacitor in which a Ta film is formed as a reaction preventing layer between a Cu electrode and a Ta ₂ O ₅ film.
The iO ₂ equivalent thickness of _Ta 2 _{O 5} film thickness dependence is a diagram for explaining.

FIG. 7 is a T-layer formed as a reaction preventing layer between a Cu electrode and a Ta ₂ O ₅ film, prepared for comparison with the first embodiment of the present invention.
It is a longitudinal cross-sectional view of a capacitor having an aN film formed thereon.

FIG. 8 is a diagram comparing the effective electric field dependence of the leakage current density in a capacitor using Ta as a reaction prevention layer with a capacitor using TaN as a reaction prevention layer.

FIG. 9 shows a capacitor using Ta as a reaction preventing layer.
SiO_TwoTa of converted film thickness_TwoO ₅Prevent film thickness dependence
It is a figure compared with the capacitor which used TaN as a stop layer.
It

FIG. 10 is a vertical sectional view of a step for explaining the first embodiment of the present invention.

FIG. 11 is a vertical sectional view of a step for explaining the second embodiment of the present invention.

FIG. 12 is a plan view of a step for explaining the first embodiment of the present invention.

[Explanation of symbols]

1 ... Silicon substrate, 2 ... TaN film, 3 ... Ta film, 4 ... C
u film, 5 ... TaN film, 6 ... Ta ₂ O ₅ film, 7 ... Au electrode, 8 ... Ta film, 9 ... Etch stopper film, 10 ... Insulating film, 11a ... Barrier conductive film (first conductive film) , 11b
... barrier conductive film (second conductive film), 11c ... conductive film (third conductive film), 11 ... buried wiring, 12a ... barrier insulating film, 12b ... insulating film, 12c ... etch stopper film, 12d ... Insulating film, 12 ... Insulating film, 13a ... Connection hole (groove portion), 13b ... Wiring groove (groove portion), 14a ... Barrier conductive film (first conductive film), 14b ... Barrier conductive film (second conductive film) ), 14c ... Conductive film (third conductive film), 1
4 ... Embedded wiring, 15 ... Ta film, 16 ... Ta ₂ O
₅ film, 17 ... Ta film, 18 ... Cu film 101 ... P-type silicon substrate, 102 ... N well region, 1
03 ... N well region, 104 ... N well region, 105 ...
N well region, 106 ... N well region, 107 ... N well region, 108 ... P well region, 109 ... P well region, 110 ... P well region, 111 ... Element isolation oxide film,
112 ... MIM capacitor, 113 ... MIM capacitor, 114 ... MIM capacitor, 115 ... Polycrystalline silicon wiring layer, 116 ... Via hole, 117 ... Via hole,
118 ... Via hole, 119 ... Via hole, 120 ... First layer Cu wiring layer, 121 ... Second layer Cu wiring layer, 12
2 ... Cu wiring layer of 3rd layer, 123 ... Cu wiring layer of 4th layer, 124 ... Cu wiring layer of 5th layer, 125 ... Silicon nitride film, 126 ... Silicide layer, 127 ... Side spacer, 128 ... Gate oxidation film.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/8242 H01L 27/06 101D 27/04 102A 27/06 27/092 27/10 461 27/108 ( 72) Inventor Kenichi Takeda 1-280, Higashi Koikekubo, Kokubunji, Tokyo, Central Research Laboratory, Hitachi, Ltd. (72) Inventor Hiroshi Miki 1-280, Higashi Koikeku, Kokubunji, Tokyo (72) Inventor, Central Research Laboratory, Hitachi Hisamoto Dai 1-280, Higashi Koigokubo, Kokubunji, Tokyo Metropolitan Research Center, Hitachi Ltd. F-term (reference) 5F038 AC05 AC10 AC15 AV06 EZ14 EZ15 EZ16 EZ17 EZ20 5F048 AB01 AC03 AC10 BA01 BB08 BC06 BE02 BF06 BF16 DA23 5F058 BA11 BC03 BF02 BF02 5F082 BC01 BC09 BC13 DA03 DA09 EA12 EA32 EA45 5F083 AD21 AD48 GA09 JA06 JA37 JA38 JA39 JA40 MA06 MA17 M A19 NA01 NA08 PR22 PR33 ZA12

Claims (10)

[Claims] 1. A method of forming a semiconductor device having an oxide dielectric capacitor, comprising: a first step of forming a Ta film on a Cu electrode; and a second step of forming a Ta ₂ O ₅ film on the Ta film. A method of manufacturing a semiconductor device, comprising: a step; and a third step of heat-treating the Ta ₂ O ₅ film in an inert atmosphere or a trace oxygen atmosphere. 2. The Ta ₂ O ₅ film forming step of the _second step is carried out by sputtering in an oxygen atmosphere at a temperature of 30.
The method for manufacturing a semiconductor device according to claim 1, wherein the formation temperature is 0 ° C. or lower. 3. The heat treatment step of the Ta ₂ O ₅ film in the third step is carried out at a higher temperature than the step of forming the Ta ₂ O ₅ film in the _second step. A method of manufacturing a semiconductor device according to item 1. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the Ta film has a thickness of 6 nm or more. 5. The Ta of the second step_TwoO₅Film former
And Ta of the third step_TwoO ₅Membrane heat treatment process
Causes the surface of the Ta film to be oxidized by 5 nm or more.
The half according to any one of claims 1 to 3, characterized in that
A method for manufacturing a conductor device. 6. An oxygen atmosphere and a heat treatment time that do not completely oxidize the Ta film in the heat treatment in the trace oxygen atmosphere in the third step of heat-treating the Ta ₂ O ₅ film in an inert atmosphere or in a trace oxygen atmosphere. The method for manufacturing a semiconductor device according to claim 5, wherein 7. The Cu electrode is Cu embedded in an insulating film.
The method of manufacturing a semiconductor device according to claim 1, wherein the method is a damascene wiring. 8. A semiconductor device having a capacitor having a lower electrode made of Cu damascene wiring, a dielectric film made of a Ta oxide film, and an upper electrode made of Cu, wherein the lower electrode and the dielectric film, and the upper electrode and the dielectric film. A semiconductor device having a Ta film between body films, wherein the Ta film surface has a Ta oxide film on the Ta film side at an interface between the Ta film and the dielectric film. 9. The semiconductor device according to claim 8, wherein the Ta film has a function of preventing oxygen from the Ta oxide film from being transmitted to Cu of the lower and upper electrodes. 10. The semiconductor device according to claim 8, wherein the Ta film has a thickness of 10 nm to 50 nm.