JP2003263364A - Cache allocation system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a cache allocation system having a main memory having a vast storage capacity and a cache memory having a smaller capacity and a high access speed, capable of shortening a program execution time without mounting a complicated cache algorithm on a CPU chip. <P>SOLUTION: A CPU core 3 has a normal mode for performing fixed cycle processing and a measuring mode for splitting the main memory 1 and setting cache effectiveness accessed through the cache memory 2 in each split unit and cache ineffectiveness accessed by bypassing the cache memory 2. The measuring mode sets the cache effectiveness and the cache ineffectiveness so that the execution time of a fixed cycle processing program by the CPU core 3 becomes minimum. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a vast main memory having a relatively slow access speed, and a cache memory having a much smaller capacity but a faster access speed, and a code in the main memory. / A cache allocation method capable of shortening program execution time in a device that repeats processing at a fixed operation cycle (fixed cycle) while accessing data without implementing a complicated cache algorithm on a CPU chip Is.

[0002]

2. Description of the Related Art FIG. 6 shows, for example, Japanese Unexamined Patent Publication No. 8-147218.
It is a block diagram which shows the conventional cache control apparatus shown by the publication. In FIG. 6, 101 is a plurality of processing means provided in the computer system, 102 is a storage device accessed by the processing means 101, 103 is a cache memory, and 104 is in response to an access request from the processing means 101 to the storage device 102. It is a cache control device that controls the cache memory 103. The cache memory 103 is
It has a plurality of occupied areas 111 provided respectively corresponding to the plurality of processing means 101, and a shared area 112 shared by the plurality of processing means 101.

The cache control device 104 stores the cache memory 1 in a plurality of occupied areas 111 and shared areas 112.
No. 03 storage area is allocated, and the corresponding occupying area 111 and shared area 112 are searched for corresponding data in response to access requests input from each of the plurality of processing means 101. Inspection means 114
And a first order operation means 115 for operating the replacement priority order of the data stored in the area including the corresponding occupied area 111 and the shared area 112 according to the search result, and the fact that the corresponding data does not exist. In response to the input of the inspection result, the replacement unit 116 that performs the data replacement process according to the replacement priority in the continuous region including the corresponding occupied region 111 and the shared region 112, and the changing unit that changes the local queue of the distribution unit 113. 121 and 121. The allocating means 113 has a plurality of occupied areas 11
It has a plurality of local queues 117 corresponding to 1 and a shared queue 118 corresponding to a shared area.

Next, the operation will be described. Distribution means 1
13, the storage area of the cache memory 103 becomes the occupied area 111 corresponding to each of the plurality of processing units 101.
And the shared area 112 and the search means 114.
Is configured to perform a search process for the corresponding occupied area 111 and shared area 112 in response to an access request from the processing unit 101. In accordance with this search result, the corresponding occupation area 11 is operated by the first order operation means 115.
The replacement priority order in the shared area 112 is manipulated together with 1, and the replacement process by the replacement means 116 is performed based on this replacement priority order. In this case, since the corresponding occupied area 111 and the shared area 112 are treated as a continuous area, the replacement processing
The data protruding from the occupied area 111 is the shared area 11
It is absorbed by 2. Therefore, in addition to allocating the occupied area 111 and a predetermined storage area to each processing means 101,
Since the shared area 112 can be distributed according to the access frequency of each processing means 101, the minimum hit rate is guaranteed for each processing means 101 and the hit rate of the processing means 101 with high access frequency is improved. It becomes possible.

[0005]

Since the conventional cache control device is constructed and operates as described above, it is necessary to add a special hardware circuit to the caching. Further, even if a processing procedure that is rarely accessed from the viewpoint of the processing means as a whole, an occupied area is fixedly assigned to each process in advance, so that use of the occupied area in the cache memory is wasted, which is inefficient. There was a problem. Further, even when focusing on one processing procedure, the code / data to be accessed by that processing procedure is large, and each code / data is accessed only once, for example, in the loop processing in the normal processing. In the processing that is not performed, even if the code / data accessed at the top of the loop is stored in the cache,
It will be replaced by the newly accessed code / data at the end of the loop, and when it reaches the processing at the beginning of the loop again, it will not be stored in the cache and will always be a cache miss, resulting in inefficiency. There was a problem that was.

The present invention has been made in order to solve the above-mentioned problems, and it is a vast main memory with a relatively slow access speed and an access speed with a much smaller capacity than that. The object of the present invention is to obtain a cache allocation method that has a fast cache memory and that shortens the program execution time without mounting a complicated cache algorithm on the CPU chip.

[0007]

A cache allocation system according to the present invention has a main memory having a predetermined storage capacity and a cache memory having a storage capacity smaller than the main memory and having an access speed faster than that of the main memory.
In the cache allocation method of the apparatus that repeats the fixed cycle processing involving access to the main memory, the apparatus divides the main memory into a normal mode in which the fixed cycle processing is performed and the main memory with a predetermined size
It has a measurement mode for setting cache valid accessed via the cache memory or cache invalid accessed without the cache memory for each divided unit, and the measurement mode is the operation of the fixed-cycle processing program of the device. A combination of cache valid and cache invalid is sequentially switched for each cycle, and cache valid or cache invalid is set for each division unit so that the execution time of the fixed cycle processing program is minimized.

Further, the cache valid or cache invalid setting result in the measurement mode is stored in the non-volatile memory, and when the normal mode is executed, the cache valid or cache invalid is set according to the setting result stored in the non-volatile memory. Is set, and the main memory is accessed according to the setting.

In the measurement mode, cache valid or cache invalid is set while changing the predetermined size of the main memory division unit. In addition, the cache enable or cache disable setting in the measurement mode is
This is performed while changing the input condition that affects the execution time of the fixed cycle processing program.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. The first embodiment of the present invention will be described below. FIG. 1 is a diagram showing cache valid / invalid allocation of a main memory when the cache allocation system according to the first embodiment of the present invention is used. In FIG. 1, 1 is a main memory that stores the code / data of a program and is large but has a relatively low access speed. 2 is a cache memory that has a smaller capacity than the main memory 1 but has a fast access speed. It is a CPU core that executes code and refers to data.

In FIG. 1, 1 MByte as a main memory,
The cache memory has 32 KBytes, and the cache valid / invalid setting size is 4 KByte. Main memory 1
Is divided into 256 spaces by a cache valid / invalid setting size of 4 KBytes, and each division unit is divided into cache setting unit # 1 to cache setting unit # 256.
And In FIG. 1, cache setting units # 1 and #
.., # 6, ... Are set as cache invalid, and therefore the access from the CPU core 3 is made directly without going through the cache memory 2. Further, since the cache setting units # 2, # 4, # 5, ..., # 256 are set to be cache valid, the access from the CPU core 3 is accessed via the cache memory 2. The CPU core 3 has a normal mode in which normal fixed cycle processing is performed, and a measurement mode in which the main memory 1 is divided and cache valid / invalid is set for each cache setting unit which is each division unit.

Next, the overall processing flow will be described. FIG. 2 is a flow chart showing the cache allocation method according to the first embodiment of the present invention, in which the CPU core 3 sequentially switches the cache valid / invalid in synchronization with the operation cycle of the fixed cycle processing program, and the program execution time is reduced. An example of automatically checking the combination of the cache valid / invalid space that becomes the shortest is shown. First, check whether the operation mode this time is the measurement mode or the normal mode (step ST
1-1), in the normal mode, the fixed cycle processing is continuously executed as a normal operation (step ST1-2). In the case of the measurement mode, the minimum processing means is cleared (actually, it is initialized by "0xFFFFFFFF" indicating the maximum time) (step ST1-3), and the minimum pattern is also cleared (step ST1-4). The main memory is divided into fixed sizes N (step ST1-5). Each space (division unit) divided here is set in the cache setting unit #
1 to cache setting unit #M.

Next, it is checked whether or not the processing means measurement for the combination pattern of cache valid / invalid settings has been completed for all the cache setting units (step ST1-
6) When finished, report a cache valid / invalid combination pattern that minimizes the execution time of the fixed cycle processing program whose execution time is shortened in all patterns (step ST1-14). , Exit the measurement mode.

When the processing time measurement for the combination pattern of cache valid / invalid is not completed, the cache valid / invalid for the cache setting units # 1 to #M.
The invalid setting is updated to the next pattern (step ST1)
-7). Next, the processing time measurement is started (step ST
1-8), the fixed cycle processing program for which the processing time is to be shortened is executed (step ST1-9), the processing time measurement is ended after the end (step ST1-10), and the current cache valid / invalid combination is executed. Check whether the processing time in the pattern is shorter than the minimum processing time (step ST
1-11), if it is smaller, the minimum processing time is updated with the processing time of this measurement (step ST1-12). The cache valid / invalid combination pattern at this time is stored as a minimum pattern (step ST1-13), and step S
Repeat from T1-6. In step ST1-11, if the processing time in this cache valid / invalid combination pattern is not less than the minimum processing time, the minimum processing time,
The procedure is repeated from step ST1-6 without updating the minimum pattern. Normally, this processing is realized by the operating system of the processing device or the scheduler, but it may be incorporated in an application program or the like which is a target for reducing the processing time.

As described above, according to the first embodiment, the main memory is divided into certain fixed-size cache setting units, and the cache valid / invalid is sequentially switched in synchronization with the operation cycle of the program in each unit, so that the program Since a means for automatically checking the combination of cache valid / invalid space that provides the shortest execution time is provided, it is possible to obtain the caching setting that actually results in the shortest processing time for a program whose processing time is shortened. It will be possible. Also, no special hardware circuit is required for caching.

Embodiment 2. Next, a second embodiment of the present invention will be described. In the second embodiment, the configuration showing cache valid / invalid allocation is the same as that of the first embodiment shown in FIG. 1, and the processing flow is different from that of the first embodiment. Next, the operation will be described. FIG. 3 is a flowchart showing a cache allocation method according to the second embodiment of the present invention. In FIG. 3, the same process steps as those in the first embodiment are given the same step numbers as those in FIG. 2 and duplicate description is omitted, and only the parts different from FIG. 2 will be described. When the operation mode is the measurement mode, the cache that minimizes the execution time of the fixed-cycle processing program whose execution time is shortened while updating the combination pattern of cache valid / invalid settings for all cache setting units A valid / invalid combination pattern is obtained, the obtained minimum pattern is stored in a nonvolatile memory such as a flash memory (step ST2-14), and the measurement mode is ended. After that, if you set the operation mode to normal mode,
According to the stored minimum pattern, the cache valid / invalid is automatically set for each cache setting unit (step ST2-1), and the fixed cycle processing is continuously executed as a normal operation (step ST1-2).

As described above, according to the second embodiment, the result of checking the cache valid / invalid combination that minimizes the program execution time is stored in a non-volatile memory such as a flash memory, and is stored in the normal mode. Automatically configures and operates the cache with the stored result, so without manually changing the caching setting process in the program according to the reported caching settings,
For a program whose processing time is to be shortened, it is possible to operate the program with a caching setting that actually shortens the time.

Embodiment 3. Next, a third embodiment of the invention will be described. In the third embodiment, the configuration showing cache valid / invalid allocation is the same as that of the first embodiment shown in FIG. 1, and the processing flow is different from that of the first embodiment. Next, the operation will be described. FIG. 4 is a flowchart showing a cache allocation method according to the third embodiment of the present invention. 4, the same processing steps as those in the second embodiment are given the same step numbers as those in FIG. 3 and duplicate explanations are omitted. Only the portions different from FIG. 3 will be explained. In FIG. 3, in step ST1-5, the main memory is divided into the fixed size N in advance, whereas in the third embodiment, the fixed size N is changed.
In steps ST1-6 and ST1-7 of FIG. 3, the cache valid / invalid setting combination pattern is updated for all cache setting units divided in advance with a fixed size, and the target is set as a target for reducing the execution time. In contrast to the cache valid / invalid combination pattern that minimizes the execution time of the periodic processing program, in FIG. 4, the cache valid / invalid of each cache setting unit is determined.
Not only the invalid setting is changed, but also the division size of the main memory is made variable, and switching (step ST3-7) is performed, and it is checked whether or not all sizes and combination patterns have been completed (step ST3-6).

As described above, according to the third embodiment, the main memory is not divided into cache setting units of a fixed size in advance, but the division sizes are also sequentially switched so that the program execution time becomes the shortest. The result of checking the combination of size and cache valid / invalid is stored in a non-volatile memory such as a flash memory, and in the normal mode, the cache is automatically set with the stored result, and means for operating is provided. It becomes possible to operate the program whose processing time is shortened by the caching setting that actually shortens the processing time.

Fourth Embodiment Next, a fourth embodiment of the invention will be described. In the fourth embodiment, the configuration showing cache valid / invalid allocation is the same as that of FIG. 1 in the first embodiment, and the processing flow is different from that of the first embodiment. Next, the operation will be described. FIG. 5 is a flowchart showing a cache allocation method according to Embodiment 4 of the present invention. In FIG. 5, the same process steps as those in the third embodiment are given the same step numbers as those in FIG. 4 and duplicate explanations are omitted. Only parts different from FIG. 4 will be explained. After updating the size for dividing the main memory into each cache setting unit and the cache valid / invalid combination pattern of each cache setting unit (step ST3
-7), in order to measure the worst value of the execution time of the program in the present combination pattern, the present worst processing time is cleared (step ST4-1), and whether or not the input of all input conditions in the present combination pattern has been completed. Is determined (step ST4-2), and when the processing is finished, it is checked whether the worst processing time this time is shorter than the minimum processing time (step ST4-).
11) If it is smaller, the minimum processing time is updated with the worst processing time this time (step ST1-12). If the input of all the input conditions in this combination pattern has not been completed, the input conditions for the fixed cycle processing program for which the processing time is to be shortened are updated (step ST4-3), and the processing time measurement is started (step ST1). -8) Execute the fixed cycle processing program for which the processing time is shortened (step ST
1-9), and at the end, the processing time measurement ends (step S
(T1-10), it is checked whether the processing time under the current input condition is longer than the current worst processing time (step ST4).
-4), if it is larger, the worst processing time is updated this time (step ST4-5), and the process is repeated from step ST4-2. If it is not larger, the worst processing time is not updated this time and the process is repeated from step ST4-2.

As described above, according to the fourth embodiment, not only the size for dividing the main memory into each cache setting unit and the cache valid / invalid combination pattern of each cache setting unit are sequentially switched, but also one division size is used. In the combination pattern, since the means for measuring the worst processing time of the processing time by sequentially switching the input conditions to the program is provided, it is possible to operate with the caching setting that minimizes the worst processing time under all input conditions. Become.

[0022]

Since the present invention is constructed as described above, it has the following effects. A cache allocation method for a device having a main memory having a predetermined storage capacity and a cache memory having a storage capacity smaller than that of the main memory and having an access speed faster than that of the main memory, and repeating a fixed cycle process involving access to the main memory. Is a normal mode in which fixed-cycle processing is performed, and the main memory is divided into a predetermined size, and the cache valid accessed through the cache memory or the cache invalid accessed without the cache memory is divided into each divided unit. There is a measurement mode to be set, and the measurement mode sequentially switches the combination of cache valid and cache invalid for each operation cycle of the fixed-cycle processing program of the device, and the unit of division is set to minimize the execution time of the fixed-cycle processing program. Since each cache setting is enabled or disabled,
Caching can be set so that the execution time of the fixed cycle processing program is minimized.

Further, the cache valid or cache invalid setting result in the measurement mode is stored in the non-volatile memory, and at the time of executing the normal mode, the cache valid or cache invalid is set according to the setting result stored in the non-volatile memory. Is set and the main memory is accessed according to the setting, so that the normal mode can be operated with the caching setting in which the execution time of the fixed cycle processing program is minimum.

Further, in the measurement mode, the cache valid or the cache is set while changing the predetermined size of the main memory division unit, so that the minimum fixed cycle processing program execution time is obtained while changing the predetermined division size. You can configure the caching settings as follows.

Further, the setting of the cache valid or the cache invalid in the measurement mode is performed while changing the input condition affecting the execution time of the fixed cycle processing program, so that the minimum including the input condition affecting the execution time is set. It is possible to obtain the caching setting so that the execution time of the fixed cycle processing program is.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a cache allocation method of a main memory when a cache allocation method according to a first embodiment of the present invention is used;
It is a figure which shows invalid allocation.

FIG. 2 is a flowchart showing a cache allocation method according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing a cache allocation method according to Embodiment 2 of the present invention.

FIG. 4 is a flowchart showing a cache allocation method according to Embodiment 3 of the present invention.

FIG. 5 is a flowchart showing a cache allocation method according to Embodiment 4 of the present invention.

FIG. 6 is a configuration diagram showing a conventional cache control device.

[Explanation of symbols]

1 main memory, 2 cache memory, 3 CPU core.

Claims (4)

[Claims] 1. An apparatus having a main memory having a predetermined storage capacity and a cache memory having a storage capacity smaller than that of the main memory and having an access speed faster than that of the main memory, and repeating a periodic process accompanied by access to the main memory. In the cache allocation method, the apparatus divides the main memory into a normal mode in which the fixed cycle processing is performed, and the main memory is divided into a predetermined size, and cache effective or cache that is accessed through the cache memory for each divided division unit. There is a measurement mode for setting cache invalidity that is accessed without going through a memory, and the measurement mode is such that the combination of cache valid and cache invalidity is sequentially switched for each operation cycle of the fixed cycle processing program of the device, and the fixed mode is set. To minimize the execution time of the cyclic processing program, Cache allocation method characterized by setting cache enable or cache disable. 2. The cache valid or cache invalid setting result in the measurement mode is stored in the non-volatile memory, and when the normal mode is executed, the cache valid or cache is set according to the setting result stored in the non-volatile memory. 2. The cache allocation method according to claim 1, wherein invalid setting is performed and the main memory is accessed according to the setting. 3. The cache allocation method according to claim 1, wherein in the measurement mode, cache valid or cache invalid is set while changing a predetermined size of a main memory division unit. 4. The cache valid or cache invalid setting in the measurement mode is performed while changing an input condition that affects the execution time of the fixed cycle processing program. The cache allocation method described in paragraph 1.