JP2003258253A - Insulated gate bipolar transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an insulated gate bipolar transistor that can obtain a low-ion voltage characteristic without lowering the manufacturing efficiency of the device. <P>SOLUTION: This insulated gate bipolar transistor has a first-conductivity first semiconductor layer, a second-conductivity second semiconductor layer formed on the surface of the first semiconductor layer, and a first-conductivity base layer formed on the surface of the second semiconductor layer. This transistor also has a plurality of gate electrodes buried in trenches formed into the base layer to reach the second semiconductor layer from the surface of the base layer through gate insulating films and arranged in their widthwise directions so that their upper surfaces may form a rectangular pattern having different widths in orthogonal two axial directions, a second-conductivity emitter layer formed to face both end sections of the gate electrodes in their longitudinal directions on the surface of the base layer, and a first main electrode which is in contact with the emitter layer and base layer. In addition, this transistor also has a second main electrode formed on the rear surface of the first conductor layer. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly to an insulated gate bipolar transistor (IGBT).
Regarding).

[0002]

2. Description of the Related Art Conventionally, an IGBT has been known as a low-loss power semiconductor device. Among them, the trench gate type IGBT is a classic planar gate type IGBT.
Compared with the above, the following advantage is obtained: by arranging a large number of miniaturized unit cells in a chip, a parasitic JFET (Junction Field Effecec
t Transistor) is not formed structurally, and therefore, there is an advantage that a low on-voltage characteristic can be obtained without a voltage drop due to pinch-off.

FIG. 15 shows a conventional trench gate type IGB.
FIG. 16 is a plan view of T, and FIG. 16 is a cross-sectional view taken along the line I-I ′.
It p⁺N on the silicon substrate 1^-The mold layer 2 is formed,
N ^-The p-type base layer 3 having a depth of about 4 μm is formed on the surface of the mold layer 2.
Diffusion formed, and depth of about 0.5μ on the surface of the base layer 3.
n of m⁺Type emitter layer 4 is selectively diffused
It

A trench 5 having a width of about 1 μm and a depth of 6 to 7 μm is formed so as to penetrate the emitter layer 4 and the base layer 3, and a gate electrode 6 is embedded in the trench 5. The cathode electrode (emitter electrode) 7 is formed so as to contact the base layer 3 and the emitter layer 4,
The anode electrode (collector electrode) 8 is formed on the back surface of the Si substrate 1.

In this trench gate type IGBT, a plurality of unit cells are arrayed and formed with the surface of the region sandwiched by the plurality of gate electrodes 6 as the cathode region of each unit cell. In the examples of FIGS. 15 and 16, the cathode region width D2 occupying the unit cell width D1 is large.

In such a conventional IGBT, the carrier distribution at the position YY 'in FIG. 15 when it is turned on is as indicated by the broken line in FIG. 19, and the carrier density is near the cathode (K) side surface. It is lower than near the A) side surface. This is an obstacle to making the on-voltage of the IGBT as low as that of the thyristor. If the carrier density near the surface on the cathode side can be increased, the on-voltage of the IGBT can be further lowered.

In FIGS. 17 and 18, the width of the cathode region D2 occupies the width D1 of the unit cell by increasing the trench gate width as compared with the IGBTs of FIGS. 15 and 16.
Shows an example in which is reduced. With such a structure,
As a result of narrowing the passage of the hole current that is injected from the p ⁺ type substrate (anode) 1 into the n ⁻ type layer 2 and flows to the cathode side at the time of turning on, accumulation of holes occurs near the cathode side surface. As a result, the carrier distribution at the YY 'position is as shown by the solid line in FIG. 19, and the carrier density near the surface of the cathode region is high. Further, as the hole density increases, electrons are injected from the cathode into the device to satisfy the charge neutral condition. Since the electron current from the cathode to the anode flows in the channel region controlled by the gate electrode 6, there is no increase in resistance due to the narrowed cathode region width D2.

As described above, by optimizing the width of the trench gate, the width of the cathode region, and the depth of the trench gate, the ON voltage of the IGBT can be lowered to the same level as that of the thyristor. . This has already been reported by the present applicant (for example, refer to Patent Document 1 or Non-Patent Document 1). The IGBT which attained a low on-voltage in this manner, the applicant, IEGT (Carrier I njectio
n E nhanced G ate Bipolar T ransistor ) and is called.

[0009]

[Patent Document 1] US Pat. No. 5,329,142

[Non-Patent Document 1] IEDM Tecknical Digest 1993, p679-6
82

[0010]

When the trench gate width is widened to lower the on-voltage as described above, some disadvantages occur. For example, in order to bury a polysilicon gate electrode in a trench having a width of about 10 μm, it is necessary to deposit polysilicon having a thickness of about 5 μm. Therefore, manufacturing efficiency is reduced. Moreover, if polysilicon having a large volume is buried in the trench, a large stress is applied to the trench region. This induces a crystal defect at the trench edge, resulting in a decrease in reliability and a decrease in yield due to a leak current or the like.

An object of the present invention is to provide an insulated gate bipolar transistor which can obtain low on-voltage characteristics without lowering manufacturing efficiency.

[0012]

An insulated gate bipolar transistor according to the present invention is a first conductive type first semiconductor layer and a second conductive type second semiconductor formed on the surface of the first semiconductor layer. Layer, a first conductive type base layer formed on the surface of the second semiconductor layer, and a trench formed to a depth reaching the second semiconductor layer from the surface of the base layer via a gate insulating film. A plurality of gate electrodes embedded in a rectangular pattern having different widths in the biaxial directions whose upper surfaces are orthogonal to each other and arranged in the lateral direction, and both end portions in the longitudinal direction of the gate electrodes on the surface of the base layer. A second conductivity type emitter layer formed so as to face the first main electrode, a first main electrode contacting the emitter layer and the base layer,
A second main electrode formed on the back surface of the first semiconductor layer;
It is characterized by having.

According to the present invention, the insulated gate buried in the trench has a rectangular upper surface, and a plurality of insulated gates are arranged in the lateral direction, and emitter layers are formed at both ends in the longitudinal direction. As a result, it is possible to easily embed the gate electrode in the trench and obtain a low on-voltage characteristic without lowering the manufacturing efficiency.

In the present invention, it is particularly preferable that the emitter layer is formed as an impurity diffusion layer facing the three side surfaces at both ends in the longitudinal direction of each gate electrode. As a result, it is possible to suppress a decrease in channel width due to a plurality of gate electrodes and emitter layers being divided in the lateral direction of the gate electrode, and it is possible to obtain an IGBT having a necessary current capacity.

In the present invention, the emitter layer is (a)
As an impurity diffusion layer formed independently of each other in the longitudinal direction of each gate electrode, or (b) as an impurity diffusion layer continuous across a plurality of gate electrodes facing both longitudinal ends of each gate electrode, Alternatively, (c) when a plurality of gate electrodes are arranged in the longitudinal direction,
It can be formed as an impurity diffusion layer that faces each end of two gate electrodes adjacent to each other in the longitudinal direction and is continuous between the two adjacent gate electrodes.

Further, according to the present invention, a plurality of gate electrodes are connected to each other at a central portion in the longitudinal direction, a connecting portion having the same structure as the gate electrode is provided, or a gate electrode is connected to each other at both longitudinal ends. It is also effective to provide a connecting portion having the same structure.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 shows an IGBT according to an embodiment.
2 is a plan view of 100a, and FIG. 2 and FIG.
11 is a cross-sectional view taken along line II 'and II-II' of FIG. p ⁺ Silicon substrate (anode emitter layer) 1 surface has a specific resistance of 50Ω ・ c
An n ⁻ type layer (n base layer) 2 of m or more is formed, and a p base layer 3 having a depth of about 4 μm is formed on the surface thereof. p
A trench 5 having a depth reaching the n base layer 2 is formed through the base layer 3, and the gate insulating film 1 is formed in the trench 5.
The gate electrode 6 is buried and formed via Hereinafter, the gate electrode 6 is also referred to as an insulating trench gate or simply a trench gate.

As shown in FIG. 1, the insulating trench gate 6
Has a long and narrow rectangular pattern, and a plurality of them are arranged at predetermined intervals in the lateral direction (y direction). A plurality of trench gates 6 are also arranged in the longitudinal direction (x direction), for example, at least two rows are arranged as shown in FIG. On the surface of the p base layer 3, at both ends in the longitudinal direction of each of these insulating trench gates 6, the three side surfaces S1, S2 of each end are formed.
An n ⁺ -type emitter layer (cathode emitter layer) 4 having a depth of about 0.5 μm is formed so as to face S3.

The surface on which the p base layer 3, the cathode emitter layer 4 and the gate electrode 6 are formed is covered with an insulating film 10. Then, a contact opening is formed in the insulating film 10 between the gate arrays in the x direction, so that the two cathode emitter layers 4 adjacent in the x direction and the p base layer 3 exposed therebetween are contacted with each other. Cathode electrode)
7 is formed. The cathode electrode 7 is formed in a stripe shape continuous in the y direction so as to commonly connect the plurality of cathode emitter layers 4 arranged in the y direction. A collector electrode (anode electrode) 8 is formed on the back surface of the substrate 1.

The IGBT 100a of this embodiment is formed as follows. First, as shown in FIG. 4, an n ⁻ layer 2 having a specific resistance of 50 Ω · cm or more is formed on the p ⁺ silicon substrate 1 by epitaxial growth to a thickness of about 100 μm. Next, boron is ion-implanted into the surface of the n ⁻ -type layer 2 to give a depth of 4
The p base layer 3 is formed by diffusing it to about μm. Further, arsenic is selectively ion-implanted into the surface of the p base layer 3 and diffused to a depth of about 0.5 μm to form a plurality of n ⁺ emitter layers 4 of about 2 μm square.

Next, as shown in FIG. 5, the top surface is rectangular so that it overlaps the n ⁺ emitter layer 4 by about 1 μm, and the width in the lateral direction is about 1 μm and the width in the longitudinal direction is about 10 μm.
A trench 5 having a depth of m and a depth of about 7 μm is formed. Trench 5
A gate insulating film 11 having a thickness of about 0.1 μm is formed on the inner surface of the substrate by thermal oxidation. And CVD (Chemical
After depositing polysilicon of about 0.5 μm by the Vapor Deposition method to fill the inside of the trench 5, RIE (Reactive Ion Etchi) is performed.
ng) to etch back the polysilicon to flatten the surface. Thereby, the embedded gate electrode 6 is obtained.

After that, the surface of the substrate is covered with the insulating film 10. Then, a contact opening is formed in the insulating film 10, and the cathode electrode 7 is formed by vapor deposition or sputtering of Al. Si
A V-Ni-Au film is deposited on the back surface of the substrate 1 to form the anode electrode 8.

Although omitted in the above description, it is necessary to connect the plurality of insulating trench gates 6 in common and lead them to the gate electrode node (G). That is, as schematically shown in FIG. 1, the gate wiring 12 connecting the plurality of insulating trench gates 6 is required. This gate wiring 12
Can be formed with the same metal layer as the cathode electrode 7 or with a different metal layer.

The IGBT 100a of this embodiment is almost the same as the conventional example shown in FIG. That is, the trench gate width is larger than the cathode region width, and the cathode region width D2 in the unit cell width D1 is smaller than that in FIG. As a result, as described in the related art, when turned on,
The carrier density near the surface on the cathode side can be increased, and a low on-voltage can be obtained.

In the case of this embodiment, FIG. 15 or FIG.
Unlike the conventional example of No. 7, since the trench gate 6 and the cathode emitter layer 4 are divided into a plurality in the y direction, the channel width seems to be smaller than that of the IGBT of FIG. 15 or FIG. 17 at first glance. However, since both ends of the trench gate 6 are formed so as to overlap the cathode emitter layer 4 as described above, the cathode emitter layer 4 is formed on the three side surfaces S1, S2, S3 at each end of the trench gate 6. Opposite, the channel will be formed underneath. For example, if the width of the trench gate 6 in the y direction is 1 μm and the overlap with the cathode emitter layer 4 is 1 μm as in the above-mentioned numerical example, a channel width of 3 μm is secured at each end of one trench gate 6. It Therefore, by optimizing the width and the arrangement pitch of the trench gates 6, a channel width that is not so different from the conventional one can be obtained. In other words, it is possible to obtain a current capacity that is not so different from that of the conventional IGBT.

In this embodiment, in the y direction,
The trench gates in FIGS. 17 and 18 are divided into a plurality of pieces, and each trench width is small. Therefore, it is not necessary to deposit a thick polysilicon film as in the example of FIGS. 17 and 18 in order to embed the gate electrode.
As a result, it is possible to prevent a decrease in manufacturing efficiency due to an increase in deposited film thickness. Further, since the volume of one trench is small, stress applied to the trench is reduced, and reliability and yield are improved. In addition, in this embodiment,
Since the cathode emitter layer is formed separately on both ends of each trench gate, the area of the NPNP thyristor which does not contribute to the transistor operation is small and the latch-up withstand capability is large.

In this embodiment, the rectangular pattern on the upper surface of the insulating trench gate has a short side of 1 μm and a long side of 10 μm.
However, the optimum value differs depending on the withstand voltage system. For example, in the case of a 1200V type device, the long side is 16 μm for the short side 1 μm.
The optimum value is about m. Further, the lateral width can be made smaller under the condition that a trench can be formed and a good polysilicon film can be buried. Hereinafter, some other embodiments will be described. In the following embodiments, the parts corresponding to those in the first embodiment will be assigned the same reference numerals as those in the first embodiment, and detailed description thereof will be omitted.

[Second Embodiment] FIG. 6 is a plan view of an IGBT 100b according to a second embodiment. The II 'and II-II' cross sections are the same as those in FIGS. The second embodiment is different from the first embodiment in that the cathode emitter layer 4
Have different shapes. That is, the cathode emitter layer 4 is
Similar to the cathode electrode 7, a plurality of insulating trench gates 6 arranged in the y direction are formed as continuous impurity diffusion layers at both ends of the insulating trench gate 6. The cathode emitter layer 4 faces the three side surfaces at each end of the trench gate, as in the first embodiment. With such a structure, the same effect as that of the first embodiment can be obtained, and the alignment accuracy with the cathode emitter layer 4 when the trench 5 is formed is relaxed, so that the manufacturing margin can be increased. .

[Third Embodiment] FIG. 7 is a plan view of an IGBT 100c according to a third embodiment, and FIG.
It is an I'cross section. The II-II 'cross section is the same as in FIG. In this embodiment, the cathode emitter layer 4 is x
It is formed as one continuous impurity diffusion layer between two insulating trench gates 6 adjacent in the direction, and is shared by the two insulating trench gates 6. Cathode emitter layer 4
Is opposite to the three sides of each end of the trench gate,
It is similar to the first embodiment. The contact between the cathode electrode 7 and the p base layer 3 is between the cathode emitter layers 4 which are formed discretely in the y direction. With such a structure, the same effect as that of the first embodiment is obtained, and the alignment accuracy with the cathode emitter layer 4 is relaxed when the trench 5 is formed, so that the manufacturing margin can be increased. .

[Fourth Embodiment] FIG. 9 is a plan view of an IGBT 100d according to a fourth embodiment. Its II 'and II
-II 'cross section becomes the same as FIG. 2 and FIG. The cathode emitter layer 4 is the same as in the first embodiment. In this embodiment, a connecting portion 21 is provided for connecting the plurality of insulating trench gates 6 arranged in the y direction to each other at the central portion in the longitudinal direction. The connecting portion 21 has the same structure as the insulating trench gate 6 and is formed in the same step to serve as the gate wiring 12 shown in FIG. 1 for connecting the plurality of trench gates 6. In order to reduce the resistance of the gate wiring, it is also effective to form a metal wiring so as to overlap the connecting portion 21. This structure is the same as that of the first embodiment except that the connecting portion 21 is provided, and therefore the first embodiment is the same.
The same effect as can be obtained.

[Fifth Embodiment] FIG. 10 shows a fifth embodiment.
2 is a plan view of the IGBT 100e of FIG. Its II 'and
The II-II 'cross section is the same as that in FIGS. The cathode emitter layer 4 is formed as a diffusion layer continuous over a plurality of trench gates 6 in the y direction, as in the second embodiment shown in FIG. As in the case of FIG. 9, a connecting portion 21 for connecting the trench gates 6 to each other at the central portion in the longitudinal direction thereof is provided. In order to reduce the resistance of the gate wiring, it is also effective to form a metal wiring so as to overlap the connecting portion 21. This structure is the same as that of the second embodiment except that the connecting portion 21 is provided, and therefore, the second embodiment.
The same effect as can be obtained.

[Sixth Embodiment] FIG. 11 shows a sixth embodiment.
3 is a plan view of an IGBT 100f of FIG. Its II 'and
The II-II ′ cross section is the same as that in FIGS. 8 and 3. Similar to the third embodiment (FIGS. 7 and 8), cathode emitter layer 4 is formed as a diffusion layer shared by insulating trench gates 6 adjacent in the x direction. As in the case of FIG. 9, a connecting portion 21 for connecting the trench gates 6 to each other at the central portion in the longitudinal direction thereof is provided. This structure has a connecting part 2
The third embodiment is the same as the third embodiment except that the first embodiment is provided, and therefore the same effect as the third embodiment can be obtained.

[Seventh Embodiment] FIG. 12 shows a seventh embodiment.
It is a top view of IGBT100g. Its II 'and
The II-II 'cross section is the same as that in FIGS. This embodiment is a modification of the embodiment shown in FIG. 9, and has connecting portions 21a, 21 for connecting a plurality of insulating trench gates 6 arranged in the y direction to each other at both longitudinal ends thereof.
b is provided. These connecting portions 21a and 21b have the same structure as the insulating trench gate 6 and are formed in the same process to connect the plurality of trench gates 6 with each other.
This is the same as the fourth embodiment shown in FIG. The cathode emitter layer 4 is formed on the respective trench gates 6 as in FIG. 1 or FIG.
Are impurity diffusion layers formed independently of each other at both ends.

This structure is different from the above-described embodiments in that the cathode emitter layer 4 is formed at the end portion of the trench gate.
It does not face the side surface. However, since a channel is formed under the portion of the cathode emitter layer 4 facing the side surfaces of the connecting portions 21a and 21b, the channel width similar to that of the first embodiment can be secured. In addition, the same effects as those of the first embodiment can be obtained.

[Eighth Embodiment] FIG. 13 shows an eighth embodiment.
2 is a plan view of an IGBT 100h of FIG. Its II 'and
The II-II 'cross section is the same as that in FIGS. This embodiment has a trench gate structure similar to that of the embodiment of FIG. 12, and the cathode emitter layer 4 is formed as shown in FIG.
Similarly, as a diffusion layer continuous over the plurality of trench gates 6 in the y direction, in other words, the connection portion 21a,
21b is formed as a continuous diffusion layer. According to this embodiment, the connecting portion 21 of the trench gate 6 is
All of a and 21b are effective gate electrodes, and a channel region is formed on the entire side surface thereof. As a result, the same channel width as that of the conventional 15 or FIG. 17 can be secured, and a sufficient current capacity can be obtained. Further, as in the embodiment of FIG. 6, a large manufacturing margin can be obtained.

[Ninth Embodiment] FIG. 14 shows a ninth embodiment.
2 is a plan view of the IGBT 100i of FIG. Its II 'and
The II-II ′ cross section is the same as that in FIGS. 8 and 3. This embodiment has a trench gate structure similar to that of the embodiment of FIG. 12, and the cathode emitter layer 4 is formed as shown in FIG.
Similarly, the impurity diffusion layer shared by two adjacent trench gates 6 is formed. A large manufacturing margin can be obtained for the same reason as in the embodiment of FIG.

[0037]

As described above, according to the present invention, it is possible to provide an insulated gate bipolar transistor which can obtain a low on-voltage characteristic without lowering the manufacturing efficiency.

[Brief description of drawings]

FIG. 1 is an IGBT 100a according to an embodiment of the present invention.
FIG.

FIG. 2 is a cross-sectional view taken along the line I-I ′ of FIG.

FIG. 3 is a sectional view taken along the line II-II ′ of FIG.

FIG. 4 is a cross-sectional view for explaining a step of forming the pnpn structure of the same IGBT.

FIG. 5 is a cross-sectional view for explaining a step of forming a trench gate of the same IGBT.

FIG. 6 is a plan view of an IGBT 100b according to another embodiment.

FIG. 7 is a plan view of an IGBT 100c according to another embodiment.

8 is a cross-sectional view taken along the line I-I 'of FIG.

FIG. 9 is a plan view of an IGBT 100d according to another embodiment.

FIG. 10 is a plan view of an IGBT 100e according to another embodiment.

FIG. 11 is a plan view of an IGBT 100f according to another embodiment.

FIG. 12 is a plan view of an IGBT 100g according to another embodiment.

FIG. 13 is a plan view of an IGBT 100h according to another embodiment.

FIG. 14 is a plan view of an IGBT 100i according to another embodiment.

FIG. 15 is a plan view of a conventional IGBT.

16 is a cross-sectional view taken along the line I-I ′ of FIG.

FIG. 17 is a plan view of a conventional improved IGBT.

18 is a cross-sectional view taken along the line I-I ′ of FIG.

FIG. 19 is a diagram showing a carrier distribution when a conventional IGBT is turned on.

[Explanation of symbols]

100a to 100i ... IGBT, 1 ... P ⁺ type silicon substrate, 2 ... N ^- type layer, 3 ... P base layer, 4 ... N ⁺ emitter layer (cathode emitter layer), 5 ... Trench, 6 ... Gate electrode, 7 ... Cathode electrode, 8 ... Anode electrode, 10 ... Insulating film, 11 ... Gate electrode, 21, 21a, 21b ... Connection part.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 658G

Claims (13)

[Claims] 1. A first conductivity type first semiconductor layer, and a second conductivity type second formed on the surface of the first semiconductor layer.
A semiconductor layer, a first conductive type base layer formed on the surface of the second semiconductor layer, and a trench formed to a depth reaching the second semiconductor layer from the surface of the base layer with a gate insulating film interposed. A plurality of gate electrodes that are embedded in a rectangular pattern having different widths in the biaxial directions whose upper surfaces are orthogonal to each other and are arranged in the lateral direction, and both longitudinal ends of each of the gate electrodes on the surface of the base layer. Second-conductivity-type emitter layer formed so as to face the first part, a first main electrode contacting the emitter layer and the base layer, and a second main electrode formed on the back surface of the first semiconductor layer. When,
An insulated gate bipolar transistor having: 2. The insulated gate bipolar transistor according to claim 1, wherein the emitter layer is formed as an impurity diffusion layer facing the three side surfaces at both ends in the longitudinal direction of each gate electrode. 3. The insulated gate bipolar transistor according to claim 2, wherein the emitter layer is an impurity diffusion layer formed independently at both ends of each gate electrode in the longitudinal direction. 4. The impurity diffusion layer is formed such that the emitter layer is formed so as to face both ends of each of the gate electrodes in the longitudinal direction and to be continuous over a plurality of gate electrodes. The insulated gate bipolar transistor described. 5. A plurality of the gate electrodes are arranged also in the longitudinal direction, and the emitter layer has two gates that are opposed to and adjacent to each end of two gate electrodes adjacent to each other in the longitudinal direction. 3. The insulated gate bipolar transistor according to claim 2, wherein the impurity diffusion layer is formed so as to be continuous between the electrodes. 6. The insulated gate bipolar transistor according to claim 2, further comprising a connecting portion having the same structure as the gate electrode, which connects the plurality of gate electrodes to each other at a central portion in a longitudinal direction thereof. 7. The insulated gate bipolar transistor according to claim 6, wherein the emitter layer is an impurity diffusion layer formed independently at both ends in the longitudinal direction of each gate electrode. 8. The impurity diffusion layer is formed such that the emitter layer is formed so as to face both ends of each of the gate electrodes in the longitudinal direction and to be continuous over a plurality of gate electrodes. The insulated gate bipolar transistor described. 9. A plurality of the gate electrodes are arranged in the longitudinal direction, and the emitter layer has two gates facing and facing each end of two gate electrodes adjacent in the longitudinal direction. 7. The insulated gate bipolar transistor according to claim 6, wherein the impurity diffusion layer is formed so as to be continuous between the electrodes. 10. The insulated gate bipolar transistor according to claim 1, further comprising a connecting portion having the same structure as the gate electrode, which connects the plurality of gate electrodes to each other at both ends in the longitudinal direction. 11. The insulated gate bipolar transistor according to claim 10, wherein the emitter layer is an impurity diffusion layer formed independently of each other so as to face both ends in the longitudinal direction of the respective gate electrodes. 12. The impurity diffusion layer, wherein the emitter layer is formed so as to face both ends of each of the gate electrodes in the longitudinal direction and to be continuous along the connecting portion. Insulated gate bipolar transistor. 13. A plurality of the gate electrodes are arranged also in the longitudinal direction, and the emitter layer has two gates facing and adjoining respective end portions of two gate electrodes adjacent to each other in the longitudinal direction. The insulated gate bipolar transistor according to claim 10, wherein the impurity diffusion layer is formed so as to be continuous between the electrodes.