JP2003258122A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and the manufacturing method of the same, capable of contriving the miniaturization of a contact hole in a logic section and provided with an e-DRAM at high density. <P>SOLUTION: A second interlayer insulation film 118 is formed on a base plate, and thereafter, a contact hole 119, reaching a conductor plug 111b and a conductor plug 111c, is formed. Then, a polysilicon film 121 is formed on the base plate. In this case, the contact hole 119 is filled with polysilicon film 121. Thereafter, an opening 124 is formed in the polysilicon film 121 and, thereafter, the etching of a second interlayer insulation film 118 is effected, employing the polysilicon film 121 as a mask to form a contact hole 125. Then, an adherence layer and a tungstenum film are formed on the base plate and, thereafter, a conductor plug 121a, consisting of a polysilicon film, and a conductor plug 122 which consists of an adherence layer and the tungsten film, are formed simultaneously by CMP. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a DRAM memory cell and a manufacturing method thereof, and more particularly to a semiconductor device having a logic transistor mounted therein and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, advances in semiconductor microfabrication technology have made it possible to form semiconductor elements integrated at a giga level on a single semiconductor LSI. As a result, a system consisting of several semiconductor LSIs, which is conventionally composed of separate chips, is about to be formed on one chip (system on silicon). And currently, the core technology for realizing this system is
Large-capacity general-purpose memory DRAM and high-speed logic LSI integrated DRAM logic LSI
(E-DRAM: embedded DRAM).

Here, the memory cell in the DRAM is
It is composed of a capacitor having a capacitance insulating film and a MIS transistor for charging and discharging electric charge to the capacitor.
A heat treatment (formation of a thermal oxide film) at about 0 ° C. is essential. Currently, a technique for forming a capacitive insulating film at a low temperature using a high dielectric material such as a tantalum oxide film (low-temperature process) is being researched, but it has not yet been put into practical use. On the other hand, in logic LSIs that require high-speed operability, it is essential to reduce the gate length of MIS transistors. Therefore, in order to suppress the diffusion of impurities and suppress the short channel effect, it is essential to lower the process temperature. Becomes
In order to realize a DRAM and a logic LSI on the same chip, it is necessary to recognize the difference in the necessity for lowering the temperature in this process and proceed with the process so that no trouble occurs.

In that case, in the DRAM adopting the trench type memory cell structure in which the capacitance insulating film of the capacitor and the cell plate electrode are arranged in the trench, the capacitor can be formed before forming the MIS transistor. Therefore, even if the MIS transistors of the DRAM and the logic LSI are formed by a common process after forming the capacitor, the DRAM and the logic LS as described above are formed.
It is easy to avoid the problem caused by the difference in the need for lowering the temperature from I. From this, the trench memory cell structure is said to be suitable for e-DRAM. However, there are problems in that the process for forming the capacitor is complicated and there is a large restriction on miniaturization of the memory cell. Therefore, at present, the structure of the stack type memory cell in which the capacitor is arranged above the MIS transistor is adopted in many DRAMs, and is considered to be a promising structure for the future.

In the stack type memory cell structure, a process according to the following procedure has been proposed and practiced in order to avoid problems due to heat treatment of the process. First, D
A MIS transistor in the RAM memory section and a capacitor arranged above the MIS transistor with an interlayer insulating film sandwiched therebetween are formed. In the meantime, in the MIS transistor in the logic section, the gate electrode and the LDD region are formed, but a high concentration source is formed. -Leave the drain region unformed. After that, the interlayer insulating film covering the upper part of the logic part is removed, and M of the logic part is removed.
The source / drain regions of the IS transistor are formed.

6 to 8 are examples showing a conventional method for manufacturing an e-DRAM semiconductor device adopting such a process. Here, FIGS. 6A to 6C and FIG.
(A) and FIG. 7 (b), FIG. 8 (a) and FIG. 8 (b)
It is sectional drawing which shows the manufacturing process of the conventional semiconductor device.

First, in a step shown in FIG. 6A, an element isolation insulating film 501 surrounding active regions of a DRAM memory portion and a logic portion is formed on a silicon substrate 500, and then a silicon oxide film is formed on the substrate. And a polysilicon film are sequentially deposited. After that, these films are patterned to form a DRAM.
The gate insulating film 502 and the gate electrode 503 of the MIS transistor of the memory portion and the logic portion are formed.

At this time, a gate wiring 504 connected to the gate electrode 503 of the logic portion and a gate wiring 505 connected to the gate electrode 503 of the DRAM memory portion are formed on the isolation insulating film 501. Next, impurities are introduced into the active regions of the logic portion and the DRAM memory portion by ion implantation or the like, so that the LDD region 507 of the MIS transistor of the logic portion and the MI of the DRAM memory cell portion are formed.
Source of S transistor (memory cell transistor)
A drain region 508 is formed.

Next, in the step shown in FIG. 6B, a thin silicon nitride film 509 is deposited on the substrate to form the gate electrode 50.
3 and the gate wirings 504 and 505 are formed on the silicon nitride film 509.
And then covered with a first silicon oxide film on the substrate.
Then, the interlayer insulating film 510 is deposited. At this time, a thin silicon oxide film may be formed on the substrate as a base film of the silicon nitride film 509. Further, after planarizing the first interlayer insulating film 510 by CMP, the first interlayer insulating film 5 is
10 and the silicon nitride film 509 to penetrate the source / drain region 508 and the gate wiring 5 of the DRAM memory part.
A contact hole reaching 05 is formed. At this time, no contact hole is formed in the logic portion. Next, by filling each contact hole with a conductor film (polysilicon film), M of the DRAM memory section is filled.
A conductor plug 511a (a part of the storage node) connected to the source side of the source / drain region 508 of the IS transistor, a conductor plug 511b (bit line contact) connected to the drain side of the source / drain region 508, and a gate Conductor plug 51 connected to wiring 505
1c (word line contact). The conductor plugs 511b and 511c are not necessarily formed in the cross sections shown in FIG. 6B and FIGS. 6C to 8B described later, but for easy understanding, It is treated as if it exists in this cross section.

Next, in a step shown in FIG. 6C, a thin silicon nitride film 512 is formed on the substrate, and the first interlayer insulating film 510 and each conductor plug 511a to 511c are formed by the silicon nitride film 512. After covering, a silicon oxide film 513 is deposited on the substrate. Then, the silicon oxide film 51
3 and the silicon nitride film 512 are selectively removed, and DR
An opening is formed so that the conductor plug 511a on the source of the source / drain region 508 of the AM memory section is exposed at the bottom surface. Then, after forming a polysilicon film and a photoresist film on the substrate, the upper surface of the substrate is flattened by an etch-back method, and a cylindrical storage node electrode 514 with a bottom made of a polysilicon film is formed in the opening. A photoresist portion 550 filling the recess formed by the storage node electrode 514 is formed.

Next, in the step shown in FIG. 7A, after removing the photoresist portion 550 by ashing or the like, the silicon oxide film 513 is selectively removed using hydrofluoric acid or the like. Then, after depositing a very thin silicon oxide film and a silicon nitride film on the substrate, the surface thereof is oxidized to form a capacitive insulating film 515 made of an ONO film on the storage node electrode 514. An ONO film is also formed on the silicon nitride film 512, but it is not shown in FIG. 7A. Then, after depositing a polysilicon film on the substrate, a photoresist film that covers the DRAM memory portion and opens the logic portion is formed, and the polysilicon film and the polysilicon film are formed by anisotropic dry etching using the photoresist film as a mask. A portion of the silicon nitride film 512 located in the logic portion is removed, and a cell plate electrode 516 is formed on the silicon nitride film 512. After that, the photoresist film is removed, and then wet etching is performed with hydrofluoric acid using the cell plate electrode 516 as a mask to selectively remove the first interlayer insulating film 510. After that, anisotropic etching (dry etching) is performed on the portion of the silicon nitride film 509 exposed on the substrate to form sidewalls 509a on the side surfaces of the gate electrode 503 and the gate wiring 504 in the logic portion. Next, in the logic portion, impurities are introduced into the active region by ion implantation or the like, and a high concentration source /
A drain region 517 is formed.

Next, in the step shown in FIG. 7B, after the second interlayer insulating film 518 made of a silicon oxide film is deposited on the substrate, the second interlayer insulating film 518 and the cell are formed in the DRAM memory section. Plate electrode 516 and silicon nitride film 5
12 and a conductor plug 511b (bit line contact) on the drain of the source / drain region 508,
Contact holes 51 reaching the conductor plugs 511c (word line contacts) on the gate wiring 505, respectively.
9 is formed. Furthermore, after depositing a silicon oxide film on the substrate, anisotropic etching of the silicon oxide film is performed,
An oxide film sidewall 520 is formed on the side surface of the contact hole 519.

Next, in a step shown in FIG. 8A, a photoresist film 551 which covers the DRAM memory portion and has an opening 552 in a contact formation region of the logic portion is formed on the substrate.
To form. Then, by anisotropic dry etching using the photoresist film 551 as a mask, the high-concentration source / drain region 517 and the gate wiring 5 are penetrated through the second interlayer insulating film 518 in the contact formation region of the logic portion.
A contact hole 524 reaching 04 is formed.

Next, in the step shown in FIG. 8B, after removing the photoresist film 551, an adhesion layer (Ti /
(TiN) and a tungsten film are formed, and then the adhesion layer and the tungsten film on the second interlayer insulating film 518 are polished and removed by CMP to fill the contact hole 519 in the DRAM memory part and the contact in the logic part. A conductor plug 522 filling the hole 524 is formed at the same time, and further, on the second interlayer insulating film 518,
A wiring 523 made of an aluminum alloy film or the like connected to the conductor plugs 521 and 522 is formed.

In this manufacturing method, the capacitor of the DRAM memory section can be formed before forming the high-concentration source / drain regions 517 of the MIS transistor of the logic section. Diffusion of impurities in the drain region 517 can be suppressed. Therefore, a decrease in the threshold voltage due to the short channel effect of the MIS transistor in the logic portion is suppressed, and a sufficient voltage is applied to the gate electrode,
The high speed of the operation can be maintained.

[0016]

However, the above-described conventional method of manufacturing a semiconductor device has the following problems.

Of the above-mentioned conventional semiconductor device manufacturing processes,
In the step shown in FIG. 8A, when the contact hole 524 of the logic portion of the second interlayer insulating film 518 is formed, the thickness of the second interlayer insulating film 518 is as thick as about 1400 nm. Photoresist film 55
It is necessary to form the film thickness of 1 to be thicker than the normal film thickness.
For example, the thickness of a normal photoresist film is about 800 nm
However, the film thickness of the photoresist film 551 needs to be about 1000 nm. for that reason,
There is a problem in that it is difficult to form a minute opening 552 in the photoresist film 551, and the contact hole 524 cannot be formed unless the opening 552 is enlarged.
As a result, the contact hole in the MIS transistor in the logic section becomes large, so that the area of the logic section increases in order to secure the alignment margin and the like.

An object of the present invention is to make the contact hole of the logic portion finer and to increase the density of the e-DRA.
It is to provide a semiconductor device having M and a method for manufacturing the same.

[0019]

The semiconductor device of the present invention comprises:
A semiconductor device having a first MIS transistor forming a DRAM memory section and a second MIS transistor forming a logic section, the source of the first MIS transistor formed in a first active region of a semiconductor substrate. A drain region, a source / drain region of the second MIS transistor formed in the second active region of the semiconductor substrate, a first interlayer insulating film formed in the DRAM memory portion on the semiconductor substrate, First contact hole formed in the first interlayer insulating film on the source / drain region of the first MIS transistor and the source / drain region of the first MIS transistor electrically embedded in the first contact hole. A first conductor plug connected to the first electrode layer, a cell plate electrode formed above the first interlayer insulating film, and a cell plate electrode. A second interlayer insulating film formed on the semiconductor substrate including the electrode and having a flattened surface; a second contact hole provided through the second interlayer insulating film and the cell plate electrode; A second conductor plug that is embedded in the contact hole and is electrically connected to the first conductor plug, a third contact hole that penetrates through the second interlayer insulating film, and a third contact hole. And a third conductor plug made of a conductive material different from that of the second conductor plug and electrically connected to the source / drain region of the second MIS transistor.

In the above semiconductor device, the second conductor plug is made of a semiconductor material, and the third conductor plug is made of a metal material. The semiconductor material is polysilicon and the metal material is tungsten.

A method of manufacturing a semiconductor device according to the present invention is a DRA.
A method of manufacturing a semiconductor device having a first MIS transistor that constitutes an M memory section and a second MIS transistor that constitutes a logic section, the method comprising the step of forming a first interlayer insulating film on a semiconductor substrate (a ), A step (b) of forming a cell plate electrode on the first interlayer insulating film of the DRAM memory portion, and a step (c) of removing the first interlayer insulating film of the logic portion after the step (b). ), After the step (c), a step (d) of forming a second interlayer insulating film having a flattened surface on the semiconductor substrate, and a step of forming a first conductor film on the second interlayer insulating film. After the step (e) of forming, the step (f) of forming an opening in the first conductor film, and the step (f), the etching of the second interlayer insulating film is performed using the first conductor film as a mask. The first arriving at the source / drain region of the second MIS transistor And a step (g) to form a contact hole.

In the method for manufacturing a semiconductor device, there is a step of forming a sidewall on the side surface inside the opening provided in the first conductor film after the step (f) and before the step (g). Then, in the step (g), the first contact hole is formed by etching the second interlayer insulating film using the first conductor film and the sidewall as a mask.

In the method of manufacturing a semiconductor device, after the step (g), after forming the second conductive film on the semiconductor substrate, the first conductive film and the second conductive film on the second interlayer insulating film are formed. There is a step of removing the conductive film and forming a first conductive plug made of the second conductive film in the first contact hole.

In the method of manufacturing a semiconductor device described above, after the step (d) and before the step (e), the second interlayer insulating film and the cell plate electrode are penetrated to form the source of the first MIS transistor. A step of forming a second contact hole reaching a conductor plug connected to the drain region, and in the step (e), a first conductor film is formed also in the second contact hole, After (g), a second conductive film is formed on the semiconductor substrate, and then the first conductive film and the second conductive film on the second interlayer insulating film are removed to form a first contact hole. There is a step of forming a first conductive plug made of the second conductive film therein, and forming a second conductive plug made of the first conductive film in the second contact hole.

Further, in the above method of manufacturing a semiconductor device, the first conductive film is a semiconductor film and the second conductive film is a metal film. The semiconductor film is a polysilicon film and the metal film is a tungsten film.

[0026]

(First Embodiment) First Embodiment of the Present Invention
A method for manufacturing the semiconductor device according to the embodiment will be described. 1 (a) to 1 (c), 2 (a) and 2
3B, FIG. 3A and FIG. 3B are cross-sectional views showing a manufacturing process of a semiconductor device having an e-DRAM according to the first embodiment of the present invention.

First, in a step shown in FIG. 1A, an element isolation insulating film 101 surrounding active regions of a DRAM memory portion and a logic portion is formed on a silicon substrate 100, and a thickness of about 3 nm is formed on the substrate. Silicon oxide film with a thickness of about 100
nm polysilicon film is sequentially deposited. After that, these films are patterned to form the gate insulating film 102 and the gate electrode 103 of each MIS transistor in the DRAM memory part and the logic part. At this time, a gate wiring 104 connected to the gate electrode 103 of the logic portion and a gate wiring 105 connected to the gate electrode 103 of the DRAM memory portion are formed on the element isolation insulating film 101.

Thereafter, arsenic ions are ion-implanted into the active regions of the logic section and the DRAM memory section under the conditions of an accelerating voltage of 10 keV and a dose of 1 × 10 ¹⁴ atoms · cm ² .
LDD region 107 of MIS transistor of logic part
And the source / drain regions 108 of the MIS transistor (memory cell transistor) of the DRAM memory cell portion are formed.

Next, in the step shown in FIG. 1B, a silicon nitride film 109 having a thickness of about 50 nm is deposited on the substrate,
After covering the gate electrode 103 and the gate wirings 104 and 105 with a silicon nitride film 109, a first interlayer insulating film 110 made of a silicon oxide film is deposited on the substrate. At this time, a thin silicon oxide film having a thickness of about 10 to 20 nm may be formed on the substrate as a base film of the silicon nitride film 109. After that, the first interlayer insulating film 11 is formed by CMP.
After the flattening of 0, contact holes are formed penetrating the first interlayer insulating film 110 and the silicon nitride film 109 and reaching the source / drain regions 108 and the gate wirings 105 of the DRAM memory part. At this time, no contact hole is formed in the logic portion.

Thereafter, each contact hole is filled with a conductor film (polysilicon film) to form the source / drain region 1 of the MIS transistor in the DRAM memory section.
08, the conductor plug 111a (a part of the storage node) connected to the source side of 08, and the source / drain region 108
Forming a conductor plug 111b (bit line contact) connected to the drain side of the same and a conductor plug 111c (word line contact) connected to the gate wiring 105.
The conductor plugs 111b and 111c are not necessarily shown in FIG.
Although not formed in the cross section shown in (b) and FIG. 1 (c) to FIG. 3 (b), which will be described later, in order to facilitate understanding, the cross section shown in FIG. There is.

Next, in the step shown in FIG. 1C, a silicon nitride film 112 having a thickness of about 50 nm is formed on the substrate, and the first interlayer insulating film 110 and each conductor plug 111a.
After covering 111c with a silicon nitride film 112, a silicon oxide film 113 is deposited on the substrate. Then, the silicon oxide film 113 and the silicon nitride film 112 are selectively removed, and the source / drain region 1 of the DRAM memory section is removed.
An opening is formed so that the conductor plug 111a on the 08 source is exposed at the bottom surface. And the thickness on the substrate is about 1
After forming a 00 nm polysilicon film and a photoresist film, a silicon oxide film 113 is formed by an etch back method.
The upper polysilicon film and the photoresist film are removed, the upper surface of the substrate is flattened, and a cylindrical storage node electrode 114 with a bottom made of a polysilicon film is formed in the opening and a recess formed by the storage node electrode 114. A photoresist portion 150 to be filled is formed.

Next, in the step shown in FIG. 2A, the photoresist portion 150 is removed by ashing or the like, and then the silicon oxide film 113 is selectively removed using hydrofluoric acid or the like. After that, after depositing a silicon oxide film having a thickness of about 2 nm and a silicon nitride film having a thickness of about 5 nm on the substrate, the surface of the silicon nitride film is oxidized by the dilution pyrooxidation method, and is deposited on the storage node electrode 114. A capacitive insulating film 115 made of an ONO film is formed. Although the ONO film is also formed on the silicon nitride film 112, as shown in FIG.
Not shown in (a). Then, after depositing a polysilicon film having a thickness of about 100 nm on the substrate, DRA is performed.
A photoresist film which covers the M memory portion and has an opening in the logic portion is formed, and the portion of the polysilicon film and the silicon nitride film 112 located in the logic portion is removed by anisotropic dry etching using the photoresist film as a mask. Then, the cell plate electrode 116 is formed on the silicon nitride film 112 of the DRAM memory part.

Then, after removing the photoresist film,
Wet etching with hydrofluoric acid is performed using the cell plate electrode 116 as a mask to selectively remove the first interlayer insulating film 110 in the logic portion. After that, anisotropic etching (dry etching) is performed on the portion of the silicon nitride film 109 exposed on the substrate to form sidewalls 109a on the side surfaces of the gate electrode 103 and the gate wiring 104 in the logic portion. After that, arsenic ions are ion-implanted into the active region of the logic portion under the conditions of an acceleration voltage of 20 keV and a dose of 2 × 10 ¹⁵ atoms · cm ⁻² , and LD
High-concentration source / drain region 1 on the outer side of the D region 107
Form 17.

Next, in the step shown in FIG. 2B, after the second interlayer insulating film 118 made of a silicon oxide film is deposited on the substrate, the second interlayer insulating film 118 and the cell are formed in the DRAM memory section. Plate electrode 116 and silicon nitride film 1
12 and a conductor plug 111b (bit line contact) on the drain of the source / drain region 108,
Contact holes 11 reaching the conductor plugs 111c (word line contacts) on the gate wiring 105, respectively.
9 is formed. Further, after depositing a silicon oxide film having a thickness of about 20 nm on the substrate by the CVD method, anisotropic etching of the silicon oxide film is performed to form an oxide film sidewall 120 on the side surface of the contact hole 119.

Next, in the step shown in FIG. 3A, a polysilicon film 121 having a thickness of about 300 nm is formed on the substrate, and then the DRAM memory portion is covered on the polysilicon film 121 to form the logic portion. A photoresist film (not shown) having an opening in the contact formation region is formed. At this time, the polysilicon film 121 is filled in the contact hole 119 of the DRAM memory part. After that, by anisotropic dry etching using the photoresist film as a mask,
The polysilicon film 121 is etched to form an opening 124 in the polysilicon film 121 in the contact formation region of the logic portion. Then, after removing the photoresist film, the high-concentration source / drain region 117 and the gate are penetrated through the second interlayer insulating film 118 of the logic portion using the polysilicon film 121 having the opening 124 as an etching mask. A contact hole 125 reaching the wiring 104 is formed.

Next, in the step shown in FIG. 3B, after forming an adhesion layer (Ti / TiN) and a tungsten film on the substrate, a polysilicon film located on the second interlayer insulating film 118 by CMP. 121, the contact layer and the tungsten film are removed by polishing to be planarized, so that the conductor plug 121a formed of a polysilicon film fills the contact hole 119 in the DRAM memory portion, and the contact layer and the tungsten film fill the contact hole 125 in the logic portion. And the conductor plug 122 is formed at the same time, and the wiring 123 made of an aluminum alloy film or the like connected to the conductor plugs 121a and 122 is formed on the second interlayer insulating film 118.

According to the present embodiment, in the step shown in FIG. 3A, the contact hole 125 is formed in the second interlayer insulating film 118 of the logic portion using the polysilicon film 121 as an etching mask. The contact hole 125 can be formed. That is, since the polysilicon film 121 serving as an etching mask has a large selection ratio with respect to the second interlayer insulating film 118 formed of a silicon oxide film, it functions as an etching mask even when the film thickness is as thin as about 300 nm. Therefore, the thickness of the photoresist film for forming the openings 124 in the polysilicon film 121 can be thinned to about 500 nm, so that the fine openings 124 can be formed. As a result, the second interlayer insulating film is etched using the polysilicon film 121 having the fine openings 124 as an etching mask, so that the fine contact holes 125 can be formed. Further, the polysilicon film 121 is used for the conductor plug 1 embedded in the contact hole 119 of the DRAM memory section.
Since it also serves as a contact material for forming 21a, the fine contact hole 125 can be easily formed by a simple process.
Can be formed. As a result, the contact hole in the logic portion can be miniaturized, and the density can be increased.
-A semiconductor device having a DRAM can be formed.

(Second Embodiment) A method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described. Figure 4
(A) and FIG. 4 (b), FIG. 5 (a) and FIG. 5 (b)
It is sectional drawing which shows the manufacturing process of the semiconductor device which has e-DRAM concerning the 2nd Embodiment of this invention.

In the step shown in FIG. 4 (a), first, the same steps as those shown in FIGS. 1 (a) to 1 (c), 2 (a) and 2 (b) in the first embodiment are performed. Depending on the method, FIG.
A structure as shown in (b) is formed. After that, a polysilicon film 121 having a thickness of about 300 nm is formed on the substrate, and then a photoresist film (not shown) that covers the DRAM memory portion and has an opening in the contact formation region of the logic portion is formed on the polysilicon film 121. ) Is formed. At this time, the polysilicon film 121 is filled in the contact hole 119 of the DRAM memory part. After that, by anisotropic dry etching using the photoresist film as a mask,
The polysilicon film 121 is etched to form an opening 124 in the polysilicon film 121 in the contact formation region of the logic portion. Then, the photoresist film is removed.

Next, in the step shown in FIG. 4B, after a dimension adjusting film made of a polysilicon film having a thickness of about 50 nm is formed on the substrate, the dimension adjusting film is etched by anisotropic etching. Then, a sidewall 126 is formed on the side surface of the polysilicon film 121 inside the opening 124.
As a result, the size of the opening 124 a is twice the thickness of the sidewall 126 than the opening 124 (about 80 nm).
Degree) becomes smaller. In addition, as the dimension adjustment film,
Alternatively, a tungsten film, a plasma nitride film, or the like may be used.

Next, in the step shown in FIG.
A contact hole that reaches the high-concentration source / drain region 117 and the gate wiring 104 through the second interlayer insulating film 118 of the logic portion by using the polysilicon film 121 and the sidewall 126 on which the 24a is formed as an etching mask. Form 125.

Next, in the step shown in FIG. 5B, after forming an adhesion layer (Ti / TiN) and a tungsten film on the substrate, a polysilicon film located on the second interlayer insulating film 118 by CMP. 121, the side wall 126, the adhesion layer, and the tungsten film are polished and removed to be planarized to fill the contact hole 119 of the DRAM memory section with the polysilicon film 121.
And an adhesion layer filling the contact hole 125 of the logic portion and a conductor plug 122 made of a tungsten film are simultaneously formed, and further, on the second interlayer insulating film 118,
A wiring 123 made of an aluminum alloy film or the like connected to each conductor plug 121a, 122 is formed.

According to this embodiment, the same effect as that of the first embodiment can be obtained. Further, in the step shown in FIG. 4B, the opening 12 formed in the polysilicon film 121.
By forming the sidewall 126 on the inner side surface of No. 4, it is possible to form the contact hole 125 which is finer than the minimum opening size that can be formed by the photolithography method. That is, in the step shown in FIG. 4A, an opening 124 is formed in the polysilicon film 121 by using a photoresist film having a minimum opening size that can be formed by photolithography as a mask, and then shown in FIG. In the process, the sidewall 126 is formed on the inner surface of the opening 124.
Therefore, the opening 124a is smaller than the minimum opening size that can be formed by the photolithography method.
As a result, in the step shown in FIG. 5A, the polysilicon film 121 having the opening 124a and the sidewall 126 are formed.
When the contact hole 125 is formed by using as a mask, the size of the contact hole 125 is smaller than the minimum opening size that can be formed by the photolithography method.

In the first and second embodiments, the storage node electrode 114 is described as a cylindrical type, but it may be a simple stack type, an HSG type or a fin type.

[0045]

As described above, according to the semiconductor device or the method of manufacturing the same of the present invention, since the contact hole is formed in the second interlayer insulating film of the logic portion using the polysilicon film as an etching mask, a fine contact is formed. Holes can be formed. Further, the polysilicon film is DR
Since it also serves as a contact material for forming a conductor plug to be embedded in the contact hole of the AM memory portion, a fine contact hole can be easily formed by a simple process. As a result, the contact holes in the logic portion can be miniaturized, and a semiconductor device having a higher density e-DRAM can be formed.

[Brief description of drawings]

1A to 1C are cross-sectional views showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

2A and 2B are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

3A and 3B are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

4A and 4B are cross-sectional views showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

5A and 5B are cross-sectional views showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

6A to 6C are cross-sectional views showing manufacturing steps of a conventional semiconductor device.

7A and 7B are cross-sectional views showing a manufacturing process of a conventional semiconductor device.

8A and 8B are cross-sectional views showing manufacturing steps of a conventional semiconductor device.

[Explanation of symbols]

100 silicon substrate 101 Insulation film for element isolation 102 gate insulating film 103 gate electrode 104 gate wiring 105 gate wiring 107 LDD region 108 source / drain region 109 Silicon nitride film 110 First interlayer insulating film 111a conductor plug 111b conductor plug 111c conductor plug 112 Silicon nitride film 113 Silicon oxide film 114 storage node electrode 115 Capacitance insulating film 116 Cell plate electrode 117 High concentration source / drain region 118 Second interlayer insulating film 119 contact holes 120 Oxide film sidewall 121 Polysilicon film 121a Conductor plug 122 conductor plug 123 wiring 124 opening 124a opening 125 contact holes 126 Sidewall 150 photoresist section

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hideyuki Arai             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 5F038 DF05 DF11 EZ11 EZ13 EZ14                       EZ20                 5F083 AD24 AD49 AD56 JA04 JA19                       JA32 JA36 JA39 JA40 JA56                       MA05 MA06 MA18 MA19 MA20                       NA01 PR29 PR36 PR43 PR44                       PR53 PR54 ZA06 ZA12

Claims (9)

[Claims] 1. A first MI constituting a DRAM memory section.
A semiconductor device having an S-transistor and a second MIS transistor forming a logic portion, the first M being formed in a first active region of a semiconductor substrate.
The source / drain region of the IS transistor and the second active region formed on the second active region of the semiconductor substrate.
Source / drain regions of the MIS transistor, a first interlayer insulating film formed in the DRAM memory section on the semiconductor substrate, and the first interlayer insulating layer on the source / drain regions of the first MIS transistor. A first contact hole formed in the film; embedded in the first contact hole;
A first conductor plug electrically connected to a source / drain region of the MIS transistor, a cell plate electrode formed above the first interlayer insulating film, and a semiconductor substrate including the cell plate electrode A second interlayer insulating film formed above and having a flattened surface; a second contact hole penetrating the second interlayer insulating film and the cell plate electrode; and the second contact Embedded in the hole, the first
A second conductor plug electrically connected to the conductor plug, a third contact hole provided through the second interlayer insulating film, and a third contact hole embedded in the third contact hole, The second
And a third conductor plug made of a conductive material different from that of the second conductive plug, the semiconductor device being electrically connected to the source / drain regions of the MIS transistor. 2. The semiconductor device according to claim 1, wherein the second conductor plug is made of a semiconductor material, and the third conductor plug is made of a metal material. 3. The semiconductor device according to claim 2, wherein the semiconductor material is polysilicon, and the metal material is tungsten. 4. A first MI which constitutes a DRAM memory section.
A method of manufacturing a semiconductor device having an S transistor and a second MIS transistor forming a logic portion, the method comprising: forming a first interlayer insulating film on a semiconductor substrate (a).
And (b) forming a cell plate electrode on the first interlayer insulating film of the DRAM memory part, and removing the first interlayer insulating film of the logic part after the step (b). A step (c) of performing, a step (d) of forming a second interlayer insulating film having a flat surface on the semiconductor substrate after the step (c), and a step of forming a second interlayer insulating film on the semiconductor substrate. A step (e) of forming a first conductor film on the substrate, a step (f) of forming an opening on the first conductor film, and a step of using the first conductor film as a mask after the step (f). A step (g) of etching the second interlayer insulating film to form a first contact hole reaching the source / drain region of the second MIS transistor. Device manufacturing method. 5. The method for manufacturing a semiconductor device according to claim 4, wherein a side surface inside the opening provided in the first conductor film after the step (f) and before the step (g). A step of forming a sidewall thereon, and in the step (g), the first interlayer insulating film is etched by using the first conductor film and the sidewall as a mask, thereby forming the first interlayer insulating film. A method of manufacturing a semiconductor device, which comprises forming the contact hole. 6. The method for manufacturing a semiconductor device according to claim 4, wherein after the step (g), a second conductive film is formed on the semiconductor substrate and then on the second interlayer insulating film. And removing the first conductive film and the second conductive film, and forming a first conductive plug made of the second conductive film in the first contact hole. A method for manufacturing a characteristic semiconductor device. 7. The method for manufacturing a semiconductor device according to claim 4, wherein the second interlayer insulating film and the cell plate electrode are formed after the step (d) and before the step (e). A step of forming a second contact hole penetrating through and reaching a conductor plug connected to the source / drain region of the first MIS transistor, and in the step (e), the second contact hole is formed. The first conductive film is also formed in the first conductive film, the second conductive film is formed on the semiconductor substrate after the step (g), and then the first conductive film is formed on the second interlayer insulating film. By removing the film and the second conductive film,
A first conductive plug made of the second conductive film is formed in the first contact hole, and a second conductive plug made of the first conductive film is formed in the second contact hole. A method of manufacturing a semiconductor device, comprising: 8. The method of manufacturing a semiconductor device according to claim 6, wherein the first conductive film is a semiconductor film, and the second conductive film is a metal film. Device manufacturing method. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor film is a polysilicon film, and the metal film is a tungsten film.