JP2003256487A - System and method for aiding design - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To optimize a command set and a arithmetic resource in an dedicated processor. <P>SOLUTION: A design aid system includes a target value file for storing information about required processing and a required performance target for a specified application, a processing realizing database for correlating a command for realizing the processing to the each processing, a command resource database for correlating the each arithmetic resource to the each command, a resource database for storing a specification of the each arithmetic resource, and a processing realizing proposal preparation-evaluating unit for preparing a plurality of combinations comprising the command set and the arithmetic resource for realizing the required processing based on the processing realizing database and the command resource database, for evaluating the plurality of combinations comprising the command set and the arithmetic resource based on the resource database, and for selecting one of the combinations comprising the command set and the arithmetic resource so as to satisfy the performance target. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a design support method and system, and more particularly to a processor design support method and system.

2. Description of the Related Art Home appliances and the like are generally used for specific purposes. As a processor used therefor, a general-purpose processor designed for general purpose is usually used. is there. Therefore, for example, in an image device, despite performing almost only image processing,
A general-purpose processor incorporating various functions is used as the processor to be used, which is inefficient and costly.

Therefore, it is desired to design a dedicated processor for a specific application. In the first step of designing a dedicated processor, it is necessary to determine the instruction set of the processor and the arithmetic resources to be implemented for a particular application. This instruction set and computing resources are
It is an important factor that determines the processing capacity of the processor and the scale of the mounted circuit for the desired application. Also, the manufacturing cost of the processor and the power consumption of the processor are determined by the scale of the mounted circuit.

If the instruction set of a general-purpose processor is used as it is as the instruction set of the processor, it is difficult to say that the configuration is optimal. Since the processing speed of a dedicated processor varies greatly depending on the type of instruction set and the implementation calculation resource, it is necessary to provide the optimum instruction set according to the application. For example, a processor for image processing will execute many array operations and decimal point operations, and a processor for text and database processing will execute many integer operations and pointer processing (array processing).

In view of the above, it is an object of the present invention to provide a design support method and system for optimizing an instruction set and a calculation resource in a dedicated processor for a specific application.

A design support system according to the present invention includes a target value file for storing information on a process required for a specific application and a required performance target, and an instruction for realizing the process. A process realization database that corresponds to each process, an instruction resource database that associates a calculation resource with each instruction, a resource database that stores specifications of each calculation resource, and a necessary process based on the process realization database and the instruction resource database. Creating a plurality of combinations of instruction sets and calculation resources for realizing, evaluating the plurality of combinations of the instruction sets and calculation resources based on the resource database, and satisfying the performance target. Create a process implementation plan selecting one of the combinations Including the unit.

Further, the design support method according to the present invention determines a required process and a required performance target for a specific application, determines an instruction set for realizing the required process, and determines the instruction set. Each step of determining a computing resource to be realized, evaluating the instruction set and the computing resource based on a specification of the computing resource, and optimizing the instruction set and the computing resource so as to meet the performance target is included.

In the above invention, for a process required for a specific application, an instruction set and a calculation resource for realizing the process are determined, and the instruction set and the calculation resource are optimized so as to satisfy the required performance target. . Therefore, it becomes possible to select an optimum instruction set and a calculation resource for implementing the same for a specific application, and it is possible to design a processor having a desired processing capacity, cost, power consumption, and the like.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a diagram showing the configuration of a dedicated processor design support system according to the present invention.

Dedicated processor design support system 1 of FIG.
0 is a process implementation plan creation unit 11, a process implementation plan evaluation unit 12, a target value setting unit 13, a performance target value extraction unit 14, a resource database creation unit 1
5, a processing realization database creation unit 16, an instruction resource database creation unit 17, a resource database 21, a processing realization database 22, an instruction resource database 23, an application program file 24, a target value file 25, and an optimal realization plan file 26.

The application program file 24 is a file that stores an application program used for a specific purpose. By the performance target value extraction unit 14,
A performance target value is extracted from the application program stored in the application program file 24. The extracted performance target value is stored in the target value file 25.

The target value setting unit 13 sets target values such as processor performance, mounting area, power consumption, etc., from an overall viewpoint apart from the details of the application program. The set target value is stored in the target value file 25. FIG. 2 shows an example of target values set by the target value setting unit 13.

Resource database creation unit 15
Creates a resource database 21 by collecting the area and processing speed of each calculation resource. The resource database 21 stores, for example, information such that the low-speed 8-bit adder has an area of 30 and the processing time is 28, and the high-speed 32-bit multiplier has an area of 2500 and the processing time is 70. Here, the processing time is in nanoseconds, and the area is in units of μm ² . FIG. 3 shows an example of data stored in the resource database 21.

In the resource database 21, in addition to the area and the processing speed, the power consumption may be described for each computing resource. FIG. 4 shows an example of the resource database 21 having power consumption as an entry.

Processing implementation database creation unit 16
Creates a process realization database 22 by collecting information on which command can realize the process for each process. This process implementation database 2
For 2, for example, the multiplication process may use a floating point multiplication instruction, an integer multiplication instruction (and a shift instruction for performing a decimal point processing), or an addition instruction and a shift instruction repeatedly. Information indicating that it is feasible is stored. FIG. 5 shows an example of information stored in the process implementation database 22.

Instruction resource database creation unit 1
7 creates an instruction resource database 23 by summarizing which arithmetic resource is used for processing each instruction. This command resource database 2
In 3, for example, the integer addition instruction calculates C = A + B using an integer register A and B as an input and an integer register C as an output and a ripple carry adder, or inputs the integer registers A and B. And an integer register C is used as an output and a carry look ahead adder is used as C = A +
Information such as calculating B is stored. Also, for example,
The floating point multiplication instruction is executed by the floating point registers A and B.
Is input and the floating point register C is output, and information such as calculating C = AB using a floating point multiplier is stored.

The process implementation plan creating unit 11 uses the resource database 21, the process implementation database 22, and the command resource database 23 to implement the process implementation plan for achieving the target value set in the target value file 25, that is, the process. A draft of an instruction set and a calculation resource for realizing is created. The processing implementation plan evaluation unit 12
The process realization plan including the instruction set and the calculation resource obtained by the process realization plan creation unit 11 is evaluated, and the optimum process realization plan is determined on the basis of, for example, the criterion that the fastest process plan is the optimum plan. The determined optimal processing realization plan is
It is stored in the optimal realization plan file 26.

Below, using a specific program example,
The operation of the dedicated processor design support system 10 of FIG. 1 will be described in detail.

FIG. 6 is a flow chart showing the processing by the performance target value extraction unit 14. FIG. 7 is a diagram showing a specific example for explaining the process of FIG.

In step S1, a target time for executing the processing of a predetermined application program is set.

In step S2, the application program is executed to count how many times each sentence is executed. In the example of FIG. 7, the program 31 is executed to count the number of times the statements 1 to 7 are executed. As a result, for example, as shown at 32 in FIG. 7, the number of executions is obtained for each of the sentences 1 to 7.

In step S3, the execution contents of each sentence are classified for each process, and the number of executions for each process is counted. In the example of FIG. 7, the execution content of each statement is classified as a process as indicated by 33, and the number of executions of each process is counted as indicated by 34. For example, integer assignment is executed in statements 3 and 6 as shown at 33, statement 3 is executed once and statement 6 is executed 10 times as shown at 32.
Therefore, as shown by 34, the integer substitution is executed 11 times in total.

In step S4, the target performance, which is the number of processes per unit time, is obtained by dividing the number of executions by the target processing time. For example, the program of FIG.
If you want to execute with ec, the target processing time is 100 ms
It becomes ec. In this case, for example, the integer substitution process has a performance target of 0.11 (= 11/100) times per unit time msec.

FIG. 8 is a flow chart showing the processing of the processing implementation plan creation unit 11.

In step S1, the target value file 2
Each process whose performance target is set to 5 is detailed using the process realization database 22.

For the sake of explanation, the following simple application program will be taken as an example.

Int A, B, C, D, E, F; If (A == B) then {statement 1 C = A + F; statement 2 D = A * 2.0; statement 3 E = C;} statement 4 According to the flowchart of FIG. 6, the integer comparison process is extracted from the sentence 1, the integer addition process is extracted from the sentence 2, the integer multiplication process is extracted from the sentence 3, and the arithmetic process is not extracted from the sentence 4 only the substitution process. Therefore, the processing executed by this program is one integer comparison processing, one integer addition processing, and one integer multiplication processing. Note that here, without considering integer assignment processing,
Only arithmetic processing is considered. For example, if the target processing time of this application program is 1 second, the performance target is 1 integer comparison process, 1 integer addition process, and 1 integer multiplication process per second.

When the above-mentioned respective processes are detailed by the process realization database 22, for example, integer comparison → 32-bit subtraction process → 8-bit addition / subtraction × 4 times integer addition → 32-bit addition process → 8-bit addition / subtraction × 4 times integer multiplication → ( Shift processing and 32-bit addition processing) x 32
8 times shift processing × 128 times and 8 bits addition and subtraction × 1
Detailed processing can be performed as 28 times. Here, for example, the fact that the integer comparison can be realized by the 32-bit subtraction processing as described above is shown in A of the processing realization database 22 of FIG. 5, and that the 32-bit subtraction processing can be decomposed into four 8-bit addition / subtraction is shown in FIG. It is shown in B of the process realization database 22. As a result of the above-described refinement, the 8-bit addition / subtraction process is 136 times and the 8-bit shift process is 128 times in total.

Referring again to FIG. 8, in step S2, each detailed process is associated with an instruction. For example, the 8-bit addition / subtraction processing is associated with the low-speed addition / subtraction instruction as shown in C of FIG. 5, and the 8-bit shift processing is associated with the 8-bit shift instruction as shown in D of FIG.

In step S3, each instruction is associated with a computing resource using the instruction resource database 23. For example, the low-speed addition / subtraction instruction is assigned to the low-speed 8-bit adder / subtractor, and the 8-bit shift instruction is assigned to the 8-bit shifter.

In step S4, the resource database 2
1 is used to obtain the performance of the processing implementation plan. For example, in the resource database 21 of FIG. 3, the area of the low speed 8-bit adder / subtractor is 30 and the processing time is 28. The area of the 8-bit shifter is 30 and the processing time is 10. Therefore, the total area is 60, which is the sum of the area of the low speed 8-bit adder and the area of the 8-bit shifter. The total processing time is 1 of the processing time of the low speed 8-bit adder / subtractor.
It is the sum of 36 times and 128 times the processing time of the 8-bit shifter, which is 5088 (= 28 · 136 + 10 · 128).

As described above, the process realization plan creating unit 11 creates the process realization plan. Note that different combinations can be selected for the details of the above processing, instruction allocation, and calculation resource allocation. For example, the integer comparison process, the integer addition process, and the integer multiplication process of the application program in the above example are performed by a 32-bit comparator, a 32-bit high-speed adder / subtractor, and a 32-bit high-speed adder / reducer, respectively.
It is also possible to implement with a bit fast multiplier. In this case, the total area is 2760 (= 40 + 220 + 250
0), and the total processing time is 96 (= 8 + 18 + 7).
0).

The evaluation between these different combinations is performed by the process implementation plan evaluation unit 12 of FIG.

The process implementation plan evaluation process executed by the process implementation plan evaluation unit 12 will be described in detail below.

As described above, the processing implementation plan creation unit 1
There may be a number of different combinations of instructions and computational resources in the processing implementation created by 1. Several methods are conceivable in order to select the optimum process realization plan from these plural different process realization plans.

A method is conceivable in which all different combinations are first generated and the combinations are exhaustively evaluated.
For example, all combinations satisfying predetermined conditions such as the performance target, the maximum mounting area, and the power consumption as shown in FIG. 2 may be evaluated, and the one having the fastest calculation speed may be selected as the optimum processing implementation plan. This method is preferable because when the target application program is simple, the calculation load is small and the optimum solution is always obtained. However, as the application program becomes more complicated, the total number of combinations increases rapidly, which increases the computational load and is not a practical means.

Therefore, when the total number of combinations is large, a method is taken as a starting point, which is set as a starting point, and is gradually improved so as to approach a near-optimal processing implementation plan. Is desirable.

FIG. 9 is a flowchart showing an example of the process implementation plan evaluation process executed by the process implementation plan evaluation unit 12.

In step S1 of FIG. 9, it is determined whether or not the number of processing implementation plans in all cases is larger than a specified value.
If the number of cases is not more than the specified value, the process proceeds to step S2, and the optimal realization plan is selected by the brute force process. If the number of cases is larger than the specified value, the process proceeds to step S3, and an excellent realization plan is selected by the improved method.

In the brute force processing in step S2,
Create all implementation methods (process proposals in all cases) and select the most suitable one. In this case, the one with the highest calculation speed may be optimal, or the one with the minimum power in the target performance may be selected as the optimum with low power oriented,
Alternatively, as the cost-oriented, the one with the minimum cost within the target performance may be selected as the optimum. Alternatively, an evaluation function that combines conditions such as speed, power, and cost may be set, and the processing plan with the lowest evaluation function may be selected as the optimum one.

In the improved method of step S3, a plurality of modes are prepared and a good implementation plan is searched according to the mode selected by the user. As a plurality of modes, for example, a search mode from high-speed mounting that emphasizes performance, a search mode from small mounting that emphasizes area and power consumption, and a typical solution used when various conditions need to be considered A search mode is provided.

FIG. 10 is a flowchart showing the processing in the search mode from the high-speed mounting.

When the search mode from the high-speed implementation is selected in step S3 of FIG. 9, high-speed instructions and high-speed arithmetic resources are selected for all the processes in step S1 of FIG. Create an implementation plan). Step S2
Then, the evaluation is performed by calculating the area, the processing speed, the power consumption, etc. for the initial solution.

In step S3, it is determined whether the area is within a predetermined target area. If it is within the predetermined area, the process proceeds to step S4. Otherwise, step S5
The solution (process implementation plan) is changed to reduce the area with, and the process returns to step S2.

In step S4, it is determined whether the power consumption is within a predetermined target power consumption. If it is within the predetermined power consumption, the process ends. If not, the solution (process implementation plan) is changed to reduce power consumption in step S6, and the process returns to step S2.

By the above processing, it is possible to select a processing implementation plan that satisfies predetermined conditions with respect to area and power consumption, while being an implementation plan that emphasizes processing speed.

FIG. 11 is a flow chart showing the processing of the search mode from the small implementation.

When the search mode from small implementation is selected in step S3 of FIG. 9, instructions and operation resources of low power consumption and small area are selected for all the processes in step S1 of FIG. Create a solution (process implementation plan). In step S2, the initial solution is evaluated by calculating the area, processing speed, power consumption, and the like.

In step S3, it is determined whether the processing speed is within a predetermined target processing speed. If it is within the predetermined processing speed, the processing is ended. If not, the solution (process implementation plan) is changed in the direction of increasing the speed in step S4, and the process returns to step S2.

Through the above processing, it is possible to select a processing implementation plan that satisfies a predetermined condition with respect to processing speed, even though it is an implementation plan that emphasizes area and power consumption.

FIG. 12 is a flowchart showing the processing in the search mode from the representative solution.

When the search mode from the representative solution is selected in step S3 of FIG. 9, an initial solution is created in step S1 of FIG. In the process of creating the initial solution, first, in step S1-1, the calculation having the largest number of processes is selected.
That is, the number of executions of each operation is counted when the application program is executed, and the operation having the largest number of executions counted is selected. In step S1-2, three types of mounting patterns of maximum, intermediate, and minimum are determined for the selected calculation from the viewpoint of area, power consumption, or speed. In step S1-3, it is determined whether the number of combinations of mounting is less than or equal to a predetermined number (specified value). If it is less than or equal to the specified value, the operation with the next largest number of processes is selected, and step S1
Return to -2, and similarly determine the maximum, intermediate, and minimum three implementations. When the number of combinations of implementations exceeds the specified value, the processing is interrupted, and the intermediate implementation pattern is applied to the remaining unselected operations. This makes it possible to create a plurality of mounting patterns (a plurality of initial representative solutions) corresponding to different combinations.

In step S2, a certain representative solution among a plurality of initial representative solutions is evaluated. In step S3, it is determined whether or not the representative solution is below the speed target. If the speed is lower than the speed target, the speed of the representative solution is increased in step S8. When the speed target is achieved, the representative solution is improved so that the power consumption is reduced in step S4 or the area is reduced in step S9. Then in step S5,
The better one is selected from the representative solution with reduced power consumption and the representative solution with reduced area. In step S6, the new representative solution is recorded in the history.

The above series of processing is executed for each representative solution. For example, when there are 20 representative solutions at the beginning, 20 new representative solutions are obtained by the series of the first processing. In step S7, it is determined whether or not there is a new solution recorded in the history that is different from the existing solution, and the process returns to step S2 via step S10 for the solution different from the existing solution. As a result, for example, with respect to the above 20 new representative solutions, the processing from step S2 is executed again. By repeating this, a plurality of initial representative solutions are gradually improved. When the iteration process starting from an initial representative solution falls to a local solution (local minimum),
Even if this representative solution is changed further, it returns to the local solution and is the same as the existing representative solution. In this way, the traces starting from a plurality of initial representative solutions settle down to local solutions, respectively. As a result, if, for example, 20 local solutions are obtained, it is determined in step S7 that there is no solution different from the existing solution, and the process ends. The best one is selected as the optimum solution from the plurality of finally obtained local solutions.

This completes the processing of the search mode from the representative solution.

In the procedure shown in FIGS. 10, 11, and 12, the process of reducing the area, the process of reducing the power consumption, and the process of increasing the speed are executed. do it.

In order to reduce the area, for example, by comparing the size of the computing resource with the usage time, an inefficient computing resource (having a large (size / usage time)) is selected, and this is reduced in area. Change to a smaller computing resource.
In order to reduce the power consumption, for example, by comparing the power consumption of the computing resource with the usage time, a computing resource with low efficiency ((power consumption / usage time is large) is selected,
This is changed to a computing resource that consumes less power.
Further, in order to increase the speed, for example, the process execution times may be compared, and the part that takes the longest time may be changed to a higher speed method.

FIG. 13 is a diagram showing the configuration of an apparatus for realizing the design support method / design support system according to the present invention.

As shown in FIG. 13, the apparatus for realizing the design support method / design support system according to the present invention is realized by a computer such as a personal computer or an engineering workstation. FIG.
The device is a computer 510 and a computer 510.
Device 520 and communication device 52 connected to
3 and an input device. The input device includes, for example, a keyboard 521 and a mouse 522. Computer 51
0 includes a CPU 511, a RAM 512, a ROM 513, a secondary storage device 514 such as a hard disk, a removable medium storage device 515, and an interface 516.

The keyboard 521 and the mouse 522 provide an interface with the user, and various commands for operating the computer 510 and user responses to requested data are input. The display device 520 displays the results processed by the computer 510, and displays various data to allow the user to interact when operating the computer 510. The communication device 523 is for communicating with a remote place, and is composed of, for example, a modem or a network interface.

The design support method according to the present invention is provided as a computer program executable by the computer 510. This computer program is stored in a storage medium M that can be attached to the removable medium storage device 515, and from the storage medium M via the removable medium storage device 515,
It is loaded into the RAM 512 or the secondary storage device 514. Alternatively, this computer program is stored in a storage medium (not shown) in a remote place, and is loaded from the storage medium into the RAM 512 or the secondary storage device 514 via the communication device 523 and the interface 516.

Keyboard 521 and / or mouse 522
When a user gives a program execution instruction via
The U 511 loads the program from the storage medium M, the remote storage medium, or the secondary storage device 514 into the RAM 512. The CPU 511 uses the free storage space of the RAM 512 as a work area, executes the program loaded in the RAM 512, and advances the processing while appropriately interacting with the user. The ROM 513 is the computer 510.
A control program for controlling the basic operation of is stored.

By executing the computer program, the design support method is executed as described in each of the embodiments. This design support environment is the design support system.

Although the present invention has been described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the claims. (Supplementary Note 1) A target value file that stores information related to required processing and required performance goals for a specific application, a processing realization database that associates an instruction for realizing the processing with each processing, and an operation for each instruction A command resource database that associates resources, a resource database that stores specifications of each calculation resource, a plurality of combinations of a command set and a calculation resource for realizing the required process based on the process realization database and the command resource database And evaluating a plurality of combinations of the instruction set and the arithmetic resource based on the resource database, and selecting one of the combination of the instruction set and the arithmetic resource so as to satisfy the performance target. A design support system including a unit. (Supplementary Note 2) The design support system according to Supplementary Note 1, wherein the resource database includes information regarding processing time and mounting area for each calculation resource. (Supplementary Note 3) The processing implementation plan creation evaluation unit selects one of the combination of the instruction set and the computing resource so that the mounting area is within the limit required for the performance target and the processing time is the shortest. The design support system according to appendix 2, which is characterized in that (Supplementary note 4) The design support system according to supplementary note 2, wherein the resource database further includes information regarding power consumption for each calculation resource. (Supplementary note 5) The design support system according to supplementary note 1, further comprising a performance target value extraction unit that extracts the necessary processing by analyzing a specific application program. (Supplementary note 6) The design support system according to supplementary note 1, wherein the processing implementation plan creation evaluation unit evaluates all possible combinations of the instruction set and the computing resource in a brute force manner and selects an optimum combination. (Supplementary Note 7) The processing implementation plan creation / evaluation unit sets a certain combination of the instruction set and the calculation resource as an initial setting,
The design support system according to appendix 1, wherein the combinations are successively improved so as to approach desired performance. (Supplementary Note 8) A process required for a specific application and a required performance target are determined, an instruction set for realizing the required process is determined, and a computing resource for realizing the instruction set is determined. A design support method comprising: each step of evaluating the instruction set and the operation resource based on a specification of the operation resource, and optimizing the instruction set and the operation resource so as to satisfy the performance target. (Supplementary Note 9) The specification of the computing resource includes a mounting area and a processing time, and the optimizing step is performed so that the mounting area is within the limit required by the performance target and the processing time is the shortest. 9. The design support method according to attachment 8, wherein the instruction set and the computing resource are optimized. (Supplementary note 10) The design support method according to supplementary note 8, further comprising a step of extracting the necessary processing by analyzing a specific application program.

According to the present invention, with respect to the processing required for a specific application, the instruction set and arithmetic resource for realizing this are determined, and the instruction set and arithmetic resource are optimized so as to satisfy the required performance target. Turn into. Therefore, it becomes possible to select an optimum instruction set and a calculation resource for implementing the same for a specific application, and it is possible to design a processor having a desired processing capacity, cost, power consumption, and the like.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a dedicated processor design support system.

FIG. 2 is a diagram showing an example of a target value set by a target value setting unit.

FIG. 3 is a diagram showing an example of data stored in a resource database.

FIG. 4 is a diagram showing an example of a resource database having power consumption as an entry.

FIG. 5 is a diagram showing an example of information stored in a process implementation database.

FIG. 6 is a flowchart showing processing by a performance target value extraction unit.

FIG. 7 is a diagram showing a specific example for explaining the process of FIG.

FIG. 8 is a flowchart showing a process of a process implementation plan creation unit.

FIG. 9 is a flowchart showing an example of a process implementation plan evaluation process executed by a process implementation plan evaluation unit.

FIG. 10 is a flowchart showing processing in a search mode from high-speed mounting.

FIG. 11 is a flowchart showing processing in a search mode from sub-implementation.

FIG. 12 is a flowchart showing processing in a search mode from a representative solution.

FIG. 13 is a diagram showing a configuration of an apparatus that realizes a design support method / design support system according to the present invention.

[Explanation of symbols]

10 Dedicated processor design support system 11 Process implementation plan creation unit 12 Process implementation plan evaluation unit 13 Target value setting unit 14 Performance target value extraction unit 15 Resource database creation unit 16 Process Realization Database Creation Unit 17 Instruction resource database creation unit 21 Resource database 22 Process Realization Database 23 Command Resource Database 24 Application program file 25 Target value file 26 Optimal Realization Plan File

Claims (5)

[Claims] 1. A target value file that stores information about a process required for a specific application and a required performance target, a process realization database that associates a command for realizing the process with each process, and a command realization file for each command. A command resource database that associates the calculation resources, a resource database that stores the specifications of the calculation resources, a processing implementation database and a plurality of command sets and calculation resources that realize the necessary processing based on the command resource database. Creating a combination, creating a process implementation plan that evaluates a plurality of combinations of the instruction set and the computing resource based on the resource database and selects one of the combination of the instruction set and the computing resource so as to meet the performance goal. Design support system characterized by including an evaluation unit Mu. 2. The design support system according to claim 1, wherein the resource database includes information regarding a processing time and a mounting area for each calculation resource. 3. The design support system according to claim 1, further comprising a performance target value extraction unit that extracts the necessary processing by analyzing a specific application program. 4. The design support system according to claim 1, wherein the processing implementation plan creation evaluation unit evaluates all possible combinations of the instruction set and operation resources in a brute force manner and selects an optimum combination. . 5. A process required for a specific application and a required performance target are determined, an instruction set for realizing the required process is determined, and a computing resource for realizing the instruction set is determined. A design support method comprising: each step of evaluating the instruction set and the calculation resource based on the specification of the calculation resource, and optimizing the instruction set and the calculation resource so as to satisfy the performance target.