JP5245727B2 - Design support program, design support apparatus, and design support method - Google Patents

Description

  The present invention relates to a design support program, a design support apparatus, and a design support method that support optimization of an embedded system.

  Conventionally, embedded systems have strong demands for multi-functionality and high performance, but the method of improving the operating frequency consumes too much power, so a system LSI consisting of multiple processing elements (PE) Multi-core which is (Large Scale Integration) has come to be used. Some of these functions can work independently, while others work in dependence.

  The program structure and required performance are also different. In order to cope with these, in addition to the processor, a DSP (Digital Single Processor) that excels in media operations, and Reconf (Reconfigurable) that enables high-speed processing by changing the configuration for a specific instruction. Heterogeneous multi-core processors (hereinafter referred to as “AMPs”) in which a plurality of different types of cores such as accelerators and dedicated hardware such as processors are mounted are often used.

  In order to bring out the performance of such AMP, software such as understanding the characteristics of the PE installed in AMP, extracting the function from the program, mapping the optimum PE for the processing, and performing parallel processing, etc. Optimization is required.

  In the field of high performance computing (hereinafter “HPC”), parallel multi-core (SMP) has been studied as a system equipped with a plurality of processors of the same type. It was. In the parallelization in SMP, the uniformity of the processing load in each processor is the key to improving the performance, and many studies have been conducted on the loop parallelism that can easily extract the uniformity of the processing load.

  In parallel processing based on loop parallelism performed by SMP, it is difficult to extract the performance of AMP having different performance depending on PE. In AMP, it is necessary to optimize software such as analyzing a program, extracting a process from the program, mapping an optimum PE to the program, and performing parallel processing. Even in the configuration of a single processor + hardware accelerator, heavy processing has been assigned to the hardware accelerator.

  Further, in order to inherit existing assets, a method of analyzing required functions, separating them into software and hardware, and integrating and developing IP (Intellectual Property) having those functions has been performed. However, when multiple types of PEs that perform software processing are installed, such as AMP, the complexity of analysis increases rapidly. In addition, the scale of the program is said to be several hundred Kstep-1000 Kstep and will continue to expand in the future, and manual analysis is almost impossible for embedded software having a complicated structure at that scale. . For this reason, a method of optimization by automatic analysis is disclosed.

JP 2007-328415 A Ikuo Nakata “Compiler construction and optimization” Asakura Shoten Publishing September 1999 p270-p288

  In the conventional technology described above, a program is divided into a plurality of tasks based on a defined task division rule, and an optimum core is assigned by scheduling in the target AMP. Therefore, even if the AMP configuration is changed, the task division result is not changed.

  On the other hand, in the present invention, a program pattern according to the characteristics of the core is extracted from the program and assigned. The pattern is different for each core, and when a new core is added, the pattern is also newly added. By this method, the characteristics of the target AMP core can be maximized. Further, it is possible to extract a portion to be processed by dedicated hardware, and it is also possible to automatically divide the processing by software and the processing by hardware.

  An object of the present invention is to provide a design support program, a design support apparatus, and a design support method capable of optimizing an embedded system according to a program, reducing a design burden on a designer, and shortening a design period. And

  In order to solve the above-described problems and achieve the object, the design support program, the design support apparatus, and the design support method divide the target program code into a plurality of tasks and based on the types of arithmetic elements that execute the tasks. Calculating the execution cost according to the execution time of each task, generating a combination pattern representing the execution order of the tasks, and calculating the total execution cost according to the execution time of each combination pattern based on the execution cost Then, based on the total execution cost, a specific combination pattern is determined from the combination pattern group, and the determination result is output.

  According to the design support program, the design support apparatus, and the design support method, it is possible to reduce the design burden on the designer and shorten the design period while optimizing the embedded system according to the program. Play.

  Exemplary embodiments of a design support program, a design support apparatus, and a design support method will be described below in detail with reference to the accompanying drawings. This design support program, design support device, and design support method calculate the cost by dividing the program executed in the embedded system into tasks, and schedule the task execution order to obtain a pattern that minimizes the cost. This is a technology that optimizes embedded systems and improves performance.

(Hardware configuration of design support device)
FIG. 1 is a block diagram showing a hardware configuration of the design support apparatus according to the present embodiment. In FIG. 1, a design support apparatus includes a CPU (Central Processing Unit) 101, a ROM (Read-Only Memory) 102, a RAM (Random Access Memory) 103, a magnetic disk drive 104, a magnetic disk 105, and an optical disk drive. 106, an optical disk 107, a display 108, an I / F (Interface) 109, a keyboard 110, a mouse 111, a scanner 112, and a printer 113. Each component is connected by a bus 100.

  Here, the CPU 101 is a central processing unit that controls the entire design support apparatus. The ROM 102 stores a program such as a boot program. The RAM 103 is used as a work area for the CPU 101. The magnetic disk drive 104 controls reading / writing of data with respect to the magnetic disk 105 according to the control of the CPU 101. The magnetic disk 105 stores data written under the control of the magnetic disk drive 104.

  The optical disk drive 106 controls reading / writing of data with respect to the optical disk 107 according to the control of the CPU 101. The optical disc 107 stores data written under the control of the optical disc drive 106, and causes the computer to read data stored on the optical disc 107.

  The display 108 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. As this display 108, for example, a CRT, a TFT liquid crystal display, a plasma display, or the like can be adopted.

  An interface (hereinafter abbreviated as “I / F”) 109 is connected to a network 114 such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line. Connected to other devices. The I / F 109 controls an internal interface with the network 114 and controls data input / output from an external device. For example, a modem or a LAN adapter may be employed as the I / F 109.

  The keyboard 110 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Moreover, a touch panel type input pad or a numeric keypad may be used. The mouse 111 performs cursor movement, range selection, window movement, size change, and the like. A trackball or a joystick may be used as long as they have the same function as a pointing device.

  The scanner 112 optically reads an image and takes in the image data into the design support apparatus. The scanner 112 may have an OCR (Optical Character Reader) function. The printer 113 prints image data and document data. For example, a laser printer or an ink jet printer can be employed as the printer 113.

(Functional configuration of design support device)
FIG. 2 is a block diagram showing a functional configuration of the design support apparatus according to the present embodiment. The design support apparatus 200 includes a division unit 201, an acquisition unit 202, an extraction unit 203, a task execution cost calculation unit 204, a generation unit 205, a total execution cost calculation unit 206, a determination unit 207, and an output unit 208. It is the structure containing these. Specifically, the functions (the dividing unit 201 to the output unit 208) serving as the control unit are, for example, a program stored in a storage device such as the ROM 102, the RAM 103, the magnetic disk 105, and the optical disk 107 illustrated in FIG. The function is realized by executing the function or by the I / F 109.

  The dividing unit 201 has a function of dividing the target program code to be executed by the embedded system into a plurality of tasks. The embedded system includes a plurality of types of cores (arithmetic elements), and includes arithmetic elements such as a processor, a reconfiguration circuit, and a DSP. The dividing unit 201 functionally divides the target program code into blocks in control statement units. Each divided block is called a task. The division by the dividing unit 201 is realized by a known method.

  FIG. 3 is an explanatory diagram showing a description example of the target program code. Here, the target program code 300 including three for blocks is taken as an example. FIG. 4 is an explanatory diagram showing an example of division of the target program code 300 shown in FIG. In FIG. 4, the task is divided into tasks T1 to T3.

  The acquisition unit 202 has a function of acquiring setting information related to the types of calculation elements incorporated in the embedded system and optimization processing to be executed by the calculation elements. When the user inputs setting information to a predetermined input screen by operating the mouse 111 or the keyboard 110, the setting information is stored in the storage device.

  5-7 is explanatory drawing which shows an example of an input screen. In this input screen 500, tabs 501 to 503 are displayed for each computation element, and by specifying a tab, setting information (optimization technique, execution constraint, parameter) of computation elements specified by the designated tab is input. Regions 504 to 506 are displayed. By clicking the OK button 507, the setting information is stored in the storage device.

  FIG. 5 shows an input screen 500 when the processor tab 501 is designated. In the optimization method, check boxes such as “loop parallel processing” and “VLIW instruction” are displayed. A desired optimization method can be set by operating the mouse 111 and the keyboard 110 and checking them. For the “VLIW instruction”, since a parallel number is also required, a numerical value is input by operating the mouse 111 or the keyboard 110. Execution constraints are automatically input by specifying an optimization method. Regarding parameters, numerical values are input by operating the mouse 111 and the keyboard 110.

  FIG. 6 shows an input screen 500 when the DSP tab 502 is designated. In the optimization method, check boxes such as “SIMD” are displayed. A desired optimization method can be set by operating the mouse 111 and the keyboard 110 and checking them. For “SIMD”, since a parallel number is required for each type, a numerical value is input by operating the mouse 111 or the keyboard 110. Execution constraints are automatically input by specifying an optimization method. Regarding parameters, numerical values are input by operating the mouse 111 and the keyboard 110.

  FIG. 7 shows an input screen 500 when the reconfiguration circuit tab 503 is designated. In the optimization method, check boxes such as “for block block pipeline processing”, “if block simultaneous processing”, and “switch block simultaneous processing” are displayed. A desired optimization method can be set by operating the mouse 111 and the keyboard 110 and checking them. Execution constraints are automatically input by specifying an optimization method. Regarding parameters, numerical values are input by operating the mouse 111 and the keyboard 110. The information input in this way is stored in the storage device as setting information.

  FIG. 8 is an explanatory diagram showing the data structure of the setting information. The setting information includes a computation element (PE) type, a parameter, a target block, an optimization method, and an execution constraint. The PE type (processor, DSP, reconfiguration circuit) designated by the tab is stored in the PE type. The parameter stores a numerical value (number of PEs used, operating frequency, etc.) input in the input area.

  The target block stores a type (for, if-else, switch-case) of a block (task) to which the optimization technique is applied. The type of the target block is uniquely determined by the optimization method. For example, when the optimization method is “loop parallelism”, the target block is “for”.

  In the optimization method, the optimization method designated by the check box is stored. In addition, when a numerical value of the parallel number is input, the numerical value is also stored. The execution constraint stores the execution constraint of the optimization method specified by the check box. Execution constraints are uniquely determined by an optimization method. For example, when the PE type is “reconfigurable circuit” and the optimization method is “pipeline”, execution constraints such as “normalization of (loop header)”, “complete nesting”, and “loop carry dependency” are set. .

  The extraction unit 203 has a function of extracting, from a plurality of tasks, a task that can be optimized by the type of calculation element included in the setting information acquired by the acquisition unit 202. Specifically, for example, a program pattern that matches the setting information is selected from an analysis routine for extracting a program pattern prepared in advance. Then, a task corresponding to the selected program pattern is extracted from a plurality of tasks. The extracted task is stored in the storage device.

  For example, when the PE type is “reconfigurable circuit” and the optimization method is “pipeline”, an analysis routine related to pipeline processing is selected, and the target program code 300 is analyzed for each divided task. This analysis routine includes analysis of “normalization of (loop header)”, “complete nesting”, and “loop carry dependency” which are execution constraints of pipeline processing. By this analysis routine, a task assigned to the reconfiguration circuit is extracted from a plurality of divided tasks. As described above, when a task is extracted, the task is executed by an arithmetic element that executes the optimization method.

  The task execution cost calculation unit 204 has a function of calculating an execution cost corresponding to the execution time of each task based on the type of arithmetic element that executes each task obtained by the dividing unit 201. Specifically, the execution cost corresponding to the execution time of the task extracted by the extraction unit 203 is calculated based on the setting information. Here, the execution cost is a value proportional to the execution time of the task. The higher the execution cost, the longer the execution time of the task, and the lower the execution cost, the shorter the execution time of the task. The execution cost of the processor is calculated by the following equation (1).

C = s × c × L / f (1)
Here, C is the execution cost, s is the number of statements of the target task, c is the number of operations, L is the number of loop rotations of the target task, and f is the target operation element. Clock frequency (setting information operating frequency). c is a constant, and hereinafter, c = 5.

For example, when the processor executes the task T1 shown in FIG. 4, the execution cost C (T1) is f = 500 [MHz].
s = 1
c = 5
From L = 20 × 10,
C (T1) = 2 [μs]. Similarly, for tasks T2 and T3,
C (T2) = 0.5 [μs] and Cp (T3) = 0.5 [μs].

  The execution cost of the DSP / processor is calculated by the following equation (2).

C = s × c × L / (f × p) (2)
Here, C is the execution cost of the DSP / processor parallel processing by SIMD / VLIW, s is the number of statements of the target task, and p is the parallel number of parallel processing by SIMD / VLIW.

For example, when the DSP / processor executes the SIMD arithmetic processing / VLIW processing for the task T1 shown in FIG. 4, the execution cost C (T1) is f = 500 [MHz].
s = 1
c = 5
L = 20 × 10
From p = 8
C (T1) = 0.25. Similarly, for tasks T2 and T3,
C (T2) = 0.0625 [μs] and C (T3) = 0.0625 [μs].

  Further, when the target task executes both SIMD / VLIW parallel processing, the task is divided by the parallel number of both.

  For example, if the DSP executes SIMD arithmetic processing for the task T1 shown in FIG. 4 and the processor executes VLIW processing, the execution cost C is assumed to be SIMD parallel number p = 8 and VLIW parallel number p = 4. , C (T1) = 0.0625 [μs].

  Since VLIW processing performs parallel processing at the instruction level, it is necessary to use a native compiler for detailed estimation. However, if rough accuracy is sufficient, this estimation method is applied.

  Further, the execution cost of the reconfiguration circuit is calculated by the following equation (3).

C = L / f + r (3)
Here, C is the execution cost of the reconfiguration circuit, and r is the dynamic reconfiguration cost. When r is 1 to several clocks, it can be ignored for L / f. Hereinafter, r = 0.

For example, when the reconfiguration circuit executes the task T1 shown in FIG. 4, the execution cost C (T1) is f = 500 [MHz].
From L = 20 × 10,
C (T1) = 0.4 [μs]. Similarly, for tasks T2 and T3,
C (T2) = 0.1 [μs] and C (T3) = 0.1 [μs].

  The task execution cost calculation unit 204 also calculates a transfer cost corresponding to the data transfer time between the calculation elements. When executed by a DSP or a reconfigurable circuit, or when executed in parallel by a plurality of processors, data transfer is performed, so transfer cost is required. The transfer cost is calculated by the following equation (4).

Ct = d / bt (4)
Here, d is the data transfer amount, and bt is the bus throughput. The data transfer amount d is the number of loop rotations L × the number of parallels p of the task. If not SIMD / VLIW, p = 1. The bus throughput bt is, for example, 64 × 166 = 10624 in the case of 64 bits and 166 MHz.

  As described above, the task extracted as the task corresponding to the program pattern is stored in the storage device as allocation information together with the calculation element that is the execution subject and the execution cost (including the transfer cost when the transfer cost is used). Is done. FIG. 9 is an explanatory diagram showing a data structure of allocation information.

  In FIG. 2, the generation unit 205 has a function of generating a combination pattern representing the task execution order. Specifically, for example, by referring to the allocation information, the calculation element and the task assigned to the calculation element are specified, so these tasks are executed in time series (serial) or in parallel by the corresponding calculation element. Construct a combination pattern in the order in which it will be performed. The combination pattern is generated so as to cover all patterns as much as possible. An example of generating a combination pattern will be described later.

  The total execution cost calculation unit 206 has a function of calculating the total execution cost according to the execution time of each combination pattern generated by the generation unit 205 based on the execution cost calculated by the task execution cost calculation unit 204. Specifically, for example, the execution costs of the tasks constituting the combination pattern are totaled. More specifically, the tasks executed in series add up the execution costs. In the case of branching in parallel, the total execution cost is totaled by adopting the one with the largest total execution cost at the branch destination. In addition, the transfer cost is added to the portion where the data transfer occurs. A specific calculation example of the total execution cost will be described later.

  The determination unit 207 has a function of determining a specific combination pattern from the combination pattern group based on the total execution cost calculated by the total execution cost calculation unit 206. Specifically, for example, the combination pattern that minimizes the total execution cost is determined as the optimal combination pattern. As a result, the execution time of the embedded system is minimized, so that the embedded system can be optimized.

  In addition, a combination pattern whose total execution cost is equal to or less than a predetermined threshold value may be determined as an optimal combination pattern. As a result, a combination pattern with an allowable limit of the user is obtained, and the number of combinations of combination patterns increases. Also, in any case, when the total execution cost is the same value, the one with the smaller number of operation elements used may be set as the optimum combination pattern. Thereby, reduction of power consumption can be achieved. The optimal combination pattern is stored in the storage device.

  The output unit 208 has a function of outputting the determination result determined by the determination unit 207. Specifically, for example, the optimal combination pattern is displayed on the display screen of the display 108 by passing the optimal combination pattern to the display 108. In addition, it is transmitted to another computer by passing it to the I / F 109.

(Design support processing procedure)
FIG. 10 is a flowchart showing a design support processing procedure according to the present embodiment. First, setting information is acquired by the acquisition unit 202 and stored in the storage device (step S1001), and the target program code 300 is read and stored in the storage device (step S1002). The reading of the target program code 300 may be executed prior to the acquisition of setting information (step S1001).

  Then, the dividing unit 201 analyzes the target program code 300 to divide the task, and stores the divided task in the storage device (step S1003). Thereafter, program pattern allocation processing (step S1004) and scheduling processing (step S1005) are executed, and finally, the output unit 208 outputs an optimum combination pattern (step S1006).

  FIG. 11 is a flowchart showing a detailed processing procedure of the program pattern assignment processing (step S1004). First, it is determined whether or not there is an unprocessed PE type (step S1101). If there is an unprocessed PE type (step S1101: Yes), one unprocessed PE type is selected (step S1102). Next, setting information corresponding to the selected PE type is read (step S1103), and an analysis routine is called (step S1104).

  The analysis routine is a program pattern extraction algorithm called by a corresponding optimization method. Multiple analysis routines may be called. Finally, analysis execution processing (step S1105) is performed. In the analysis execution process, the called analysis routine is executed. If multiple analysis routines are called, they will be executed sequentially. Then, the process returns to step S1101. In step S1101, when there is no unprocessed PE type (step S1101: No), the process proceeds to step S1005.

  FIG. 12 is a flowchart showing a detailed processing procedure of the analysis execution process (step S1105). First, it is determined whether or not there is an unprocessed analysis routine (step S1201). If there is an unprocessed analysis routine (step S1201: Yes), one unprocessed analysis routine is selected (step S1202). A selection analysis routine is executed (step S1203). Then, the process returns to step S1201. If there is no unprocessed analysis routine in step S1201 (step S1201: No), the process returns to step S1101.

  Next, a specific example of the analysis routine will be described. 13 to 20 are flowcharts showing execution processing procedures of various analysis routines. Hereinafter, it demonstrates individually.

  FIG. 13 is a flowchart showing a program pattern extraction processing procedure regarding loop parallel processing of the for block. This analysis routine is an analysis routine for assigning a for block task to a processor.

  First, it is determined whether or not the search for all divided blocks (tasks) has been completed (step S1301). If the search has not ended (step S1301: No), the searched target block is selected (step S1302), and it is determined whether it is a for block (step S1303). If it is not a for block (step S1303: No), the process returns to step S1301. On the other hand, if it is a for block (step S1303: Yes), it is determined whether or not normalization is possible (step S1304).

  Here, normalization is a process of converting the loop header into a form of “for (i = 0; i op (comparison operation) constant; i ++)”. In step S1304, it is determined whether or not conversion to the shape is possible before execution of the loop. If it cannot be converted into the above form, it will be determined as NG because the rotational speed of the loop is not known at the time of execution.

  If normalization is not possible (step S1304: NO), the process returns to step S1301. On the other hand, if normalization is possible (step S1304: Yes), it is determined whether there is a loop carry-over dependency (step S1305). Here, when the same data is defined / referenced between different iterations, such as when the result of one iteration (i = i0) is used in another iteration (i = i1), there is a loop carry dependency. That's it.

  This is because if the processing is assigned to different cores (calculation elements) for each iteration, the execution order is not guaranteed, so that there is a possibility that the result is different from the case of sequential execution. Therefore, when there is no loop carry-over dependency (step S1305: No), the process returns to step S1301. On the other hand, when there is a loop carry-over dependency (step S1305: Yes), the task execution cost calculation unit 204 performs cost estimation (step S1306). That is, the execution cost and transfer cost of the target block are calculated.

  Then, it is determined whether the cost is commensurate with the allocation (step S1307). More specifically, if “loop execution cost + transfer cost + call overhead” becomes larger than “sequential execution cost”, assigning a process may cause performance degradation. Therefore, if “loop execution cost + transfer cost + call overhead” <“cost when sequentially executed”, the cost is commensurate with the allocation. For example, if the loop speed of the target block is very small, the execution cost will be small, and it will not be appropriate for allocation.

  If the allocation is not met (step S1307: NO), the process returns to step S1301. On the other hand, if it matches the allocation (step S1307: Yes), the target block is determined as a task that can be allocated to the processor (step S1308). For example, an allocation flag is set for the target block. Then, the process returns to step S1301. In step S1301, when the search is finished (step S1301: Yes), this analysis routine is finished.

  FIG. 14 is a flowchart showing a program pattern extraction processing procedure regarding pipeline processing of the for block. This analysis routine is an analysis routine for assigning the task of the for block to the processor / reconfigurable circuit (indicated as “reconf” in FIG. 14).

  First, it is determined whether or not the search for all divided blocks (tasks) has been completed (step S1401). If the search has not ended (step S1401: No), the searched target block is selected (step S1402), and it is determined whether it is a for block (step S1403). If it is not a for block (step S1403: No), the process returns to step S1401. On the other hand, if it is a for block (step S1403: Yes), it is determined whether or not normalization is possible (step S1404).

  Here, normalization is a process of converting the loop header into a form of “for (i = 0; i op (comparison operation) constant; i ++)”. In step S1404, it is determined whether or not conversion to the shape is possible before execution of the loop. If it cannot be converted into the above form, it will be determined as NG because the rotational speed of the loop is not known at the time of execution.

  When normalization is not possible (step S1404: No), the process returns to step S1401. On the other hand, if normalization is possible (step S1404: Yes), it is determined whether the structure is a nested structure (step S1405). This determination is a complete nesting analysis. When it is not a nested structure (step S1405: No), it returns to step S1401. On the other hand, if it is a nested structure (step S1405: Yes), it is determined whether there is a loop carry-over dependency (step S1406). Here, when the same data is defined / referenced between different iterations, such as when the result of one iteration (i = i0) is used in another iteration (i = i1), there is a loop carry dependency. That's it.

  This is because if the processing is assigned to different cores (calculation elements) for each iteration, the execution order is not guaranteed, so that there is a possibility that the result is different from the case of sequential execution. Therefore, when there is no loop carry-over dependency (step S1406: No), the process returns to step S1401. On the other hand, when there is a loop carry-over dependency (step S1406: Yes), the task execution cost calculation unit 204 performs cost estimation (step S1407). That is, the execution cost and transfer cost of the target block are calculated.

  Then, it is determined whether the cost is commensurate with the allocation (step S1408). More specifically, if “loop execution cost + transfer cost + call overhead” becomes larger than “sequential execution cost”, assigning a process may cause performance degradation. Therefore, if “loop execution cost + transfer cost + call overhead” <“cost when sequentially executed”, the cost is commensurate with the allocation. For example, if the loop speed of the target block is very small, the execution cost will be small, and it will not be appropriate for allocation.

  If the allocation is not met (step S1408: NO), the process returns to step S1401. On the other hand, if it matches the allocation (step S1408: Yes), the target block is determined as a task that can be allocated to the processor (step S1409). For example, an allocation flag is set for the target block. Then, the process returns to step S1401. In step S1401, when the search is finished (step S1401: Yes), this analysis routine is finished.

  FIG. 15 is a flowchart showing a program pattern extraction processing procedure related to simultaneous processing of the switch-case block. This analysis routine is an analysis routine for assigning the task of the switch-case block to the processor / DSP.

  First, it is determined whether or not the search for all divided blocks (tasks) has been completed (step S1501). If the search has not ended (step S1501: No), the searched target block is selected (step S1502), and it is determined whether the block is a switch-case block (step S1503). If it is not a switch-case block (step S1503: No), the process returns to step S1501.

  On the other hand, if it is a switch-case block (step S1503: Yes), it is determined whether or not there is an unselected case block in the switch-case block (step S1504). When there is no unselected case block (step S1504: No), the process returns to step S1501. On the other hand, when there is an unselected case block (step S1504: Yes), an unselected case block is selected (step S1505), and it is determined whether there is a break statement (step S1506).

  When there is no break sentence (step S1506: No), the process returns to step S1501. On the other hand, when there is a break sentence (step S1506: Yes), the process returns to step S1504. If the search is completed in step S1501 (step S1501: Yes), it is determined whether or not there is a break statement in all the case blocks (step S1507). In some cases, each case block is determined as a task that can be assigned to a core (target operation element, here, a processor or a DSP) (step S1508). For example, an allocation flag is set for each case block. Then, this analysis routine ends. On the other hand, if it is not found in step S1507 (step S1507: Yes), this analysis routine is terminated.

  FIG. 16 is a flowchart showing a program pattern extraction processing procedure related to simultaneous processing of the switch-case block. This analysis routine is an analysis routine for assigning the task of the switch-case block to the reconfiguration circuit.

  First, it is determined whether or not the search for all divided blocks (tasks) has been completed (step S1601). If the search has not ended (step S1601: No), the searched target block is selected (step S1602), and it is determined whether the block is a switch-case block (step S1603). If it is not a switch-case block (step S1603: No), the process returns to step S1601.

  On the other hand, if it is a switch-case block (step S1603: Yes), it is determined whether or not there is an unselected case block in the switch-case block (step S1604). If there is no unselected case block (step S1604: No), the process returns to step S1601. On the other hand, when there is an unselected case block (step S1604: Yes),

  An unselected case block is selected (step S1605), and it is determined whether circuit configuration information can be generated (step S1606). If it cannot be generated (step S1606: NO), the process returns to step S1604. On the other hand, if it can be generated (step S1606: Yes), circuit configuration information of the selected case block is generated (step S1607), and the process returns to step S1604. On the other hand, if there is no unselected case block in step S1604 (step S1604: No), the process returns to step S1601.

  Here, in determining whether circuit configuration information can be generated, as an example of an item to be analyzed, whether a break statement is included in the case block, whether a floating point is used, whether a pointer variable / structure Whether the field is used, whether the divisor in the division / remainder is a constant, etc. If at least one of them matches, the circuit configuration information may be generated, and if all match, the circuit configuration information may be generated.

  The circuit configuration information consists of typical arithmetic unit-based coarse-grained components consisting of 4-bit to 32-bit arithmetic operations, ALU (Arithmetic and Logic Unit) that performs logical operations, bit shift and mask circuits, and register files. Are generated by connecting by a data selector that switches the data flow between them. The generation of the circuit configuration information itself is well known (reference material: “Reconfigurable System” Toshinori Sueyoshi, Hideharu Amano [edited], p144 5.2.1 Use of coarse-grained components).

  FIG. 17 is an explanatory diagram showing a switch-case block that is a target block and its circuit configuration information. Partial circuit configuration information 1711 to 1713 is generated for each case block having a break statement of the switch-case block 1700 and finally integrated to obtain circuit configuration information 1710. The circuit represented by this circuit configuration information 1710 is mapped to the reconfiguration circuit.

  In FIG. 16, when the search is completed in step 1601 (step S1601: Yes), it is determined whether or not circuit configuration information has been generated in all the case blocks (step S1608). If it has been completed (step S1608: Yes), each case block is determined as an assignable task (step S1609). For example, an allocation flag is set for all case blocks. Then, this analysis routine ends. On the other hand, if it could not be done (step S1608: No), this analysis routine is terminated.

  FIG. 18 is a flowchart showing a program pattern extraction processing procedure regarding the simultaneous processing of the if block / else block. This analysis routine is an analysis routine for assigning the task of the if block / else block to the processor / DSP.

  First, it is determined whether or not the search for all divided blocks (tasks) has been completed (step S1801). If the search is not completed (step S1801: No), the searched target block is selected (step S1802), and it is determined whether the block is an if block / else block (step S1803). If it is not an if block / else block (step S1803: NO), the process returns to step S1801.

  On the other hand, if it is an if block / else block (step S1803: Yes), it is determined whether there is an unselected if block / else block in the if block / else block (step S1804). If there is no unselected if block / else block (step S1804: No), the process returns to step S1801.

  On the other hand, if there is an unselected if block / else block (step S1804: Yes), an unselected if block / else block is selected (step S1805), and the target block is selected as a target calculation element (here, a processor or DSP). ) Is determined as a task that can be assigned (step S1806). For example, an allocation flag is set for the target block. Then, the process returns to step S1804. In step S1801, when the search is completed (step S1801: Yes), the analysis routine is terminated.

  FIG. 19 is a flowchart showing a program pattern extraction processing procedure regarding the simultaneous processing of the if block / else block. This analysis routine is an analysis routine for assigning the task of the if block / else block to the reconfiguration circuit.

  First, it is determined whether or not the search for all divided blocks (tasks) has been completed (step S1901). If the search has not ended (step S1901: No), the searched target block is selected (step S1902), and it is determined whether the block is an if block / else block (step S1903). If it is not an if block / else block (step S1903: NO), the process returns to step S1901.

  On the other hand, if it is an if block / else block (step S1903: Yes), it is determined whether there is an unselected if block / else block in the if block / else block (step S1904). If there is no unselected if block / else block (step S1904: No), the process returns to step S1901. On the other hand, if there is an unselected if block / else block (step S1904: Yes), an unselected if block / else block is selected (step S1905).

  Then, it is determined whether circuit configuration information can be generated (step S1906). If it cannot be generated (step S1906: NO), the process returns to step S1904. On the other hand, if it can be generated (step S1906: Yes), circuit configuration information of the selected if block / else block is generated (step S1907), and the process returns to step S1904. On the other hand, if there is no unselected if block / else block in step S1904 (step S1904: No), the process returns to step S1901.

  Here, in determining whether circuit configuration information can be generated, as an example of an item to be analyzed, whether a floating point is used, whether a pointer variable / structure is used, division / Whether the divisor in the remainder is a constant or not. If at least one of them matches, the circuit configuration information may be generated, and if all match, the circuit configuration information may be generated.

  If the search is completed in step S1901 (step S1901: Yes), it is determined whether circuit configuration information has been generated in all if blocks / else blocks (step S1908). If completed (step S1908: Yes), each if block / else block is determined as an assignable task (step S1909). For example, an allocation flag is set for all case blocks. Then, this analysis routine ends. On the other hand, if it could not be done (step S1908: No), this analysis routine is terminated.

  FIG. 20 is a flowchart showing a program pattern extraction processing procedure related to SIMD arithmetic processing. This analysis routine is an analysis routine for assigning the task of the for block to the DSP.

  First, it is determined whether or not the search for all divided blocks (tasks) has been completed (step S2001). If the search is not completed (step S2001: No), the searched target block is selected (step S2002), and it is determined whether it is a for block (step S2003). If it is not a for block (step S2003: No), the process returns to step S2001. On the other hand, if it is a for block (step S2003: Yes), it is determined whether there is a SIMD calculation application location (step S2004).

  Specifically, a loop process that repeatedly accesses the same data type such as an array element executes the same type of data operation at a time, and is therefore a SIMD operation application location. On the other hand, when there is data dependence, it is not possible to do so, so the native location is analyzed by the native compiler and it is determined whether or not it becomes an applicable location.

  When there is no SIMD calculation application part (step S2004: No), the process returns to step S2001. On the other hand, if there is a SIMD calculation application location (step S2004: Yes), optimization by the native compiler is executed (step S2005).

Each core is provided with a compiler for creating an execution binary called a native compiler, and various optimizations can be executed in the native compiler. For example,
for (i = 0; i <4; i ++)
a [i] = b [i] + c [j];
The
a [i] = SIMD_add (b [i], c [i]);
In this way, conversion is performed so that a plurality of data operations can be executed at once.

  Then, after optimization, the task execution cost calculation unit 204 performs cost estimation (step S2006). That is, the execution cost and transfer cost of the target block after optimization are calculated.

  Then, it is determined whether or not the cost is commensurate with the allocation (step S2007). More specifically, if “loop execution cost + transfer cost + call overhead” becomes larger than “sequential execution cost”, assigning a process may cause performance degradation. Therefore, if “loop execution cost + transfer cost + call overhead” <“cost when sequentially executed”, the cost is commensurate with the allocation. For example, if the loop speed of the target block is very small, the execution cost will be small, and it will not be appropriate for allocation.

  And when it does not match with allocation (step S2007: No), it returns to step S2001. On the other hand, if it is suitable for allocation (step S2007: Yes), the target block after optimization is determined as a task that can be allocated to the DSP and can be subjected to SIMD calculation (step S2008). For example, an allocation flag is set for the target block. Then, the process returns to step S2001. In step S2001, when the search ends (step S2001: Yes), the analysis routine ends.

  FIG. 21 is a flowchart showing a program pattern extraction processing procedure regarding the VLIW instruction execution processing. This analysis routine is an analysis routine for assigning a for block task to a processor.

  First, it is determined whether or not the search for all divided blocks (tasks) has been completed (step S2101). If the search is not completed (step S2101: No), the searched unselected target block is selected (step S2102), and it is determined whether the block is a for block (step S2103). If it is not a for block (step S2103: No), the process returns to step S2101. On the other hand, when it is a for block (step S2103: Yes), optimization by native compiler is performed (step S2104). This optimization converts the for block into a block that can execute a plurality of operations at once.

  Then, after optimization, the task execution cost calculation unit 204 performs cost estimation (step S2105). That is, the execution cost and transfer cost of the target block after optimization are calculated.

  Then, it is determined whether the cost is commensurate with the allocation (step S2106). More specifically, if “loop execution cost + transfer cost + call overhead” becomes larger than “sequential execution cost”, assigning a process may cause performance degradation. Therefore, if “loop execution cost + transfer cost + call overhead” <“cost when sequentially executed”, the cost is commensurate with the allocation. For example, if the loop speed of the target block is very small, the execution cost will be small, and it will not be appropriate for allocation.

  If the allocation is not met (step S2106: NO), the process returns to step S2101. On the other hand, if it matches the assignment (step S2106: Yes), the optimized target block is determined as a task that can be assigned to the processor and can execute the VLIW instruction (step S2107). For example, an allocation flag is set for the target block. Then, the process returns to step S2101. In step S2101, when the search is finished (step S2101: Yes), this analysis routine is finished. In this way, by preparing various analysis routines, optimization can be performed no matter what setting information is acquired.

  FIG. 22 is a flowchart showing a detailed processing procedure of the scheduling process shown in FIG. First, a combination pattern is generated by the generation unit 205 (step S2201). Next, it is determined whether or not there is an unselected combination pattern (step S2202).

  If there is an unselected combination pattern (step S2202: Yes), one unselected combination pattern is selected (step S2203), and the total execution cost calculation unit 206 calculates the total execution cost of the selected combination pattern (step S2202). S2204). Then, the process returns to step S2202. On the other hand, when there is no unselected combination pattern (step S2202: No), the determination unit 207 determines an optimum combination pattern (step S2205). Then, control goes to a step S1006.

  Next, Example 1 will be described. In the first embodiment, the target program code 300 shown in FIG. 3 is mapped to the embedded system. In the first embodiment, two processors and one reconfiguration circuit are used. The processor uses the loop parallelism of the for block as the optimization method, and the reconfiguration circuit selects the pipeline processing as the optimization method. This is an application example.

  FIG. 23 is an explanatory diagram of setting information in the first embodiment. The setting information is tabulated in this way and stored in the storage device. FIG. 24 is an explanatory diagram of an allocation table showing the program pattern extraction result in the first embodiment. The allocation table constitutes a part of the allocation information shown in FIG. In this allocation table, an allocation flag is set for a computation element that can execute a task. In the case of FIG. 24, all of the tasks T1 to T3 are executed by the processor and the reconfiguration circuit. That is, the tasks T1 to T3 are blocks determined as tasks that can be assigned to the processor by the analysis routine shown in FIG. Similarly, the tasks T1 to T3 are blocks determined as tasks that can be assigned to the processor by the analysis routine shown in FIG.

  FIG. 25 is an explanatory diagram illustrating combination patterns for optimization in the first embodiment. In FIG. 25, “Task #” indicates a task T #. In the first embodiment, the generation unit 205 generates 12 combination patterns (1) to (12). In FIG. 25, the black tasks indicate tasks assigned to the processor, and the shaded tasks indicate tasks assigned to the reconfiguration circuit.

  Moreover, each task T1-T3 can be performed collectively. These tasks are referred to as tasks T4 to T7. The task T4 is a task that executes the task T2 and the task T3 with one processor. The task T5 is a task that executes the task T1 and the task T3 with one processor. The task T6 is a task for executing the task T1 and the task T2 by one processor. The task T7 is a task for executing the tasks T1 to T3 by one processor. 26 to 29 are explanatory diagrams illustrating examples in which tasks are collected.

  FIG. 30 is an explanatory diagram of a calculation result table for execution costs and transfer costs in the first embodiment. The calculation result table constitutes a part of the allocation information shown in FIG. 9 together with the allocation table shown in FIG. As described above, the execution costs of the tasks T1 to T3 are calculated by the analysis routines of FIGS. Note that the tasks T4 to T7 are newly collected tasks, but these execution costs are combinations of the execution costs of the tasks T1 to T3.

  FIG. 31 is an explanatory diagram showing a scheduling result of the combination pattern (1) shown in FIG. In FIG. 31, since the execution subject is only the reconfiguration circuit, the reconfiguration circuit executes tasks T1 to T3 in this order. In this case, since the mapping to the reconfiguration circuit occurs, the transfer cost is added for each task. The transfer cost is doubled due to transmission and reception. Therefore, the total execution cost of the task T1 is 70 (= 40 + 15 + 15). Similarly, the total execution cost of task T2 is 20 (= 10 + 5 + 5), and the total execution cost of task T3 is 20 (= 10 + 5 + 5). Therefore, the total execution cost of the combination pattern (1) is 110 (= 70 + 20 + 20).

  FIG. 32 is an explanatory diagram showing a scheduling result of the combination pattern (2) shown in FIG. In FIG. 32, the reconfiguration circuit executes tasks T1 and T2, and the processor executes task T3. In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfigurable circuit is 90: the sum of the total execution cost of the task T1: 70 and the total execution cost of the task T2: 20. On the other hand, since the task T3 may be executed by the main processor of the two processors, there is no transfer cost. Therefore, the total execution cost of task T3 is 50. Since the reconfiguration circuit and the processor are executed in parallel, select the one with the highest total execution cost. Therefore, the total execution cost of the combination pattern (2) is 90 (= 70 + 20).

  FIG. 33 is an explanatory diagram showing a scheduling result of the combination pattern (3) shown in FIG. In FIG. 33, the reconfiguration circuit executes tasks T1 and T3, and the processor executes task T2. In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfiguration circuit is 90: the sum of the total execution cost of task T1: 70 and the total execution cost of task T3: 20. On the other hand, since the task T2 may be executed by the main processor of the two processors, there is no transfer cost. Therefore, the total execution cost of task T2 is 50. Since the reconfiguration circuit and the processor are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (3) is 90 (= 70 + 20).

  FIG. 34 is an explanatory diagram showing a scheduling result of the combination pattern (4) shown in FIG. In FIG. 34, the reconfiguration circuit executes task T1, and the processor executes tasks T2 and T3. In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfiguration circuit is the total execution cost of task T1: 70. On the other hand, the tasks T2 and T3 are executed by two processors, respectively, but no data transfer occurs to the main processor. Therefore, if the processor that executes task T3 is the main, the total execution cost of task T2 is 60 (= 50 + 5 + 5), and the total execution cost of task T3 is 50. Since the reconfiguration circuit and the processor are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (4) is 70 (= 40 + 15 + 15).

  FIG. 35 is an explanatory diagram showing a scheduling result of the combination pattern (5) shown in FIG. In FIG. 35, the processor executes task T1, and the reconfiguration circuit executes tasks T2 and T3. In this way, when different calculation elements are used, they can be executed in parallel. In the processor, the total execution cost of the task T1 is 200. On the other hand, in the reconfiguration circuit, the total execution cost of task T2 is 20 (= 10 + 5 + 5), and the total execution cost of task T3 is 20 (= 10 + 5 + 5). The total execution cost of the reconfiguration circuit is 40: the sum of the total execution cost of task T2: 20 and the total execution cost of task T3: 20. Since the reconfiguration circuit and the processor are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (5) is 200.

  FIG. 36 is an explanatory diagram showing a scheduling result of the combination pattern (6) shown in FIG. In FIG. 36, the reconfiguration circuit executes task T2, and the processor executes tasks T1 and T3. In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfiguration circuit is the total execution cost of task T2: 20. On the other hand, the tasks T1 and T3 are executed by two processors, respectively, but no data transfer occurs to the main processor. Therefore, assuming that the processor that executes the task T1 is the main, the total execution cost of the task T1 is 200, and the total execution cost of the task T3 is 60 (= 50 + 5 + 5). By using the processor with the higher transfer cost as the main, the total execution cost can be suppressed. Since the reconfiguration circuit and the processor are executed in parallel, select the one with the highest total execution cost. Therefore, the total execution cost of the combination pattern (6) is 200.

  FIG. 37 is an explanatory diagram showing a scheduling result of the combination pattern (7) shown in FIG. In FIG. 37, the reconfiguration circuit executes task T3, and the processor executes tasks T1 and T2. In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfiguration circuit is the total execution cost of task T3: 20. On the other hand, tasks T1 and T2 are executed by two processors, respectively, but no data transfer occurs to the main processor. Therefore, assuming that the processor that executes the task T1 is the main, the total execution cost of the task T1 is 200, and the total execution cost of the task T2 is 60 (= 50 + 5 + 5). By using the processor with the higher transfer cost as the main, the total execution cost can be suppressed. Since the reconfiguration circuit and the processor are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (7) is 200.

  FIG. 38 is an explanatory diagram showing a scheduling result of the combination pattern (8) shown in FIG. In FIG. 38, the processor executes any of the tasks T1 to T3. Here, since the number of processors is two, the task T1 is executed by one main processor, and the tasks T2 and T3 are executed by the other processor. By using the processor with the higher transfer cost as the main, the total execution cost can be suppressed. Since the processor that executes tasks T2 and T3 is not the main processor, transfer costs are incurred. Therefore, the total execution cost of task T1 is 200, the total execution cost of task T2 is 60, and the total execution cost of task T3 is 60. Since the processor executing the task T1 and the processor executing the tasks T2 and T3 are executed in parallel, the one having the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (8) is 200.

  FIG. 39 is an explanatory diagram showing a scheduling result of the combination pattern (9) shown in FIG. In FIG. 39, the reconfiguration circuit executes task T1, and the processor executes task T4 (T2 + T3). In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfiguration circuit is the total execution cost of task T1: 70. On the other hand, since the task T4 is executed only by the main processor, there is no transfer cost. Therefore, the total execution cost of the task T4 is 100 (= 50 + 50). Since the reconfiguration circuit and the processor are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (9) is 100.

  FIG. 40 is an explanatory diagram showing a scheduling result of the combination pattern (10) shown in FIG. In FIG. 40, the reconfiguration circuit executes task T2, and the processor executes task T5 (T1 + T3). In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfiguration circuit is the total execution cost of task T2: 20. On the other hand, since the task T5 is executed only by the main processor, there is no transfer cost. Therefore, the total execution cost of task T5 is 250 (200 + 50). Since the reconfiguration circuit and the processor are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (10) is 250.

  FIG. 41 is an explanatory diagram showing a scheduling result of the combination pattern (11) shown in FIG. In FIG. 41, the reconfiguration circuit executes task T3, and the processor executes task T6 (T1 + T2). In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfiguration circuit is the total execution cost of task T3: 20. On the other hand, since the task T6 is executed only by the main processor, there is no transfer cost. Therefore, the total execution cost of task T6 is 250 (200 + 50). Since the reconfiguration circuit and the processor are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (11) is 250.

  FIG. 42 is an explanatory diagram showing a scheduling result of the combination pattern (12) shown in FIG. In FIG. 42, the processor executes task T7 (T1 + T2 + T3). Since task T7 is executed only by the main processor, there is no transfer cost. Therefore, the total execution cost of task T7 is 300 (200 + 50 + 50). Therefore, the total execution cost of the combination pattern (12) is 300.

  The determination unit 207 determines a combination pattern having the minimum total execution cost as an optimal combination pattern from the total execution costs of the combination patterns (1) to (12). Therefore, since the total execution cost of the combination pattern (4) shown in FIG. 34 is the minimum, the combination pattern (4) is determined as the optimal combination pattern. That is, the optimal combination is that the task T1 is assigned to the reconfiguration circuit and the tasks T2 and T3 are assigned to the two processors, respectively.

  Next, Example 2 will be described. In the second embodiment, the target program code 300 shown in FIG. 3 is mapped to the embedded system. The second embodiment uses one processor for controlling the whole, two DSPs, and one reconfigurable circuit. The DSP adopts a for block SIMD arithmetic processing (4 parallel) as an optimization method. This is an application example when pipeline processing is selected as an optimization method.

  FIG. 43 is an explanatory diagram of setting information in the second embodiment. The setting information is tabulated in this way and stored in the storage device. FIG. 44 is an assignment table showing program pattern extraction results in the second embodiment. This allocation table constitutes a part of the allocation information shown in FIG. In this allocation table, an allocation flag is set for a computation element that can execute a task. In the case of FIG. 44, the tasks T1 to T3 are all executed by the DSP and the reconfiguration circuit. That is, the tasks T1 to T3 are blocks determined as tasks that can be assigned to the DSP by the analysis routine shown in FIG. Similarly, the tasks T1 to T3 are blocks determined as tasks that can be assigned to the processor by the analysis routine shown in FIG.

  FIG. 45 is an explanatory diagram illustrating combination patterns for optimization in the second embodiment. In FIG. 45, “Task #” indicates a task T #. In the second embodiment, the generation unit 205 generates 12 combination patterns (101) to (112). In FIG. 45, hatched tasks indicate tasks assigned to the DSP, and shaded tasks indicate tasks assigned to the reconfiguration circuit.

  Moreover, each task T1-T3 can be performed collectively. These tasks are referred to as tasks T4 to T7. The task T4 is a task for executing the task T2 and the task T3 with one DSP. The task T5 is a task that executes the task T1 and the task T3 with one DSP. The task T6 is a task for executing the task T1 and the task T2 by one DSP. The task T7 is a task for executing the tasks T1 to T3 by one DSP. The method of grouping tasks is as shown in FIGS.

  FIG. 46 is an explanatory diagram of an execution cost and transfer cost calculation result table in the second embodiment. The calculation result table constitutes a part of the allocation information shown in FIG. 9 together with the allocation table shown in FIG. As described above, the execution costs of the tasks T1 to T3 are calculated by the analysis routines of FIGS. Note that the tasks T4 to T7 are newly collected tasks, but these execution costs are combinations of the execution costs of the tasks T1 to T3.

  FIG. 47 is an explanatory diagram showing a scheduling result of the combination pattern (101) shown in FIG. In FIG. 47, since the execution subject is only the reconfiguration circuit, the reconfiguration circuit executes tasks T1 to T3 in this order. In this case, since the mapping to the reconfiguration circuit occurs, the transfer cost is added for each task. The transfer cost is doubled due to transmission and reception. Therefore, the total execution cost of the task T1 is 70 (= 40 + 15 + 15). Similarly, the total execution cost of task T2 is 20 (= 10 + 5 + 5), and the total execution cost of task T3 is 20 (= 10 + 5 + 5). Therefore, the total execution cost of the combination pattern (101) is 110 (= 70 + 20 + 20).

  FIG. 48 is an explanatory diagram showing a scheduling result of the combination pattern (102) shown in FIG. In FIG. 48, the reconfiguration circuit executes tasks T1 and T2, and the DSP executes task T3. In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfigurable circuit is 90: the sum of the total execution cost of the task T1: 70 and the total execution cost of the task T2: 20. On the other hand, since the task T3 may be executed by the main DSP of the two DSPs, no transfer cost is generated. Therefore, the total execution cost of task T3 is 13. Since the reconfiguration circuit and the DSP are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (102) is 90 (= 70 + 20).

  FIG. 49 is an explanatory diagram showing a scheduling result of the combination pattern (103) shown in FIG. In FIG. 49, tasks T1 and T3 are executed by the reconfiguration circuit, and task T2 is executed by the DSP. In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfiguration circuit is 90: the sum of the total execution cost of task T1: 70 and the total execution cost of task T3: 20. On the other hand, since the task T2 may be executed by the main DSP of the two DSPs, no transfer cost is generated. Therefore, the total execution cost of task T2 is 13. Since the reconfiguration circuit and the DSP are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (103) is 90 (= 70 + 20).

  FIG. 50 is an explanatory diagram showing a scheduling result of the combination pattern (104) shown in FIG. In FIG. 50, the reconfiguration circuit executes task T1, and the DSP executes tasks T2 and T3. In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfiguration circuit is the total execution cost of task T1: 70. On the other hand, the tasks T2 and T3 are executed by two DSPs, respectively, but no data transfer occurs to the main DSP. Therefore, if the DSP that executes task T3 is the main, the total execution cost of task T2 is 23 (= 13 + 5 + 5), and the total execution cost of task T3 is 13. Since the reconfiguration circuit and the DSP are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (104) is 70 (= 40 + 15 + 15).

  FIG. 51 is an explanatory diagram showing a scheduling result of the combination pattern (105) shown in FIG. In FIG. 51, the task T1 is executed by the DSP, and the tasks T2 and T3 are executed by the reconfiguration circuit. In this way, when different calculation elements are used, they can be executed in parallel. In the DSP, the total execution cost of the task T1 is 50. On the other hand, in the reconfiguration circuit, the total execution cost of task T2 is 20 (= 10 + 5 + 5), and the total execution cost of task T3 is 20 (= 10 + 5 + 5). The total execution cost of the reconfiguration circuit is 40: the sum of the total execution cost of task T2: 20 and the total execution cost of task T3: 20. Since the reconfiguration circuit and the processor are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (105) is 50.

  FIG. 52 is an explanatory diagram showing a scheduling result of the combination pattern (106) shown in FIG. In FIG. 52, the reconfiguration circuit executes task T2, and the DSP executes tasks T1 and T3. In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfiguration circuit is the total execution cost of task T2: 20. On the other hand, the tasks T1 and T3 are executed by the two DSPs, respectively, but no data transfer occurs to the main DSP. Therefore, if the DSP that executes the task T1 is the main, the total execution cost of the task T1 is 50, and the total execution cost of the task T3 is 23 (= 13 + 5 + 5). By using the DSP having the higher transfer cost as the main, the total execution cost can be suppressed. Since the reconfiguration circuit and the DSP are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (106) is 50.

  FIG. 53 is an explanatory diagram showing a scheduling result of the combination pattern (107) shown in FIG. In FIG. 53, the reconfiguration circuit executes task T3, and the DSP executes tasks T1 and T2. In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfiguration circuit is the total execution cost of task T3: 20. On the other hand, tasks T1 and T2 are executed by two DSPs, respectively, but no data transfer occurs to the main DSP. Therefore, if the DSP that executes task T1 is the main, the total execution cost of task T1 is 50, and the total execution cost of task T2 is 23 (= 13 + 5 + 5). By using the DSP having the higher transfer cost as the main, the total execution cost can be suppressed. Since the reconfiguration circuit and the DSP are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (107) is 50.

  FIG. 54 is an explanatory diagram showing a scheduling result of the combination pattern (108) shown in FIG. In FIG. 54, the DSP executes any of the tasks T1 to T3. Here, since the number of DSPs is two, the task DSP is executed by one main DSP and the tasks T2 and T3 are executed by the other DSP. By using the DSP having the higher transfer cost as the main, the total execution cost can be suppressed. Since the DSP that executes the tasks T2 and T3 is not the main DSP, there is a transfer cost. Therefore, the total execution cost of task T1 is 50, the total execution cost of task T2 is 23, and the total execution cost of task T3 is 23. Since the DSP that executes the task T1 and the DSP that executes the tasks T2 and T3 are executed in parallel, the one having the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (108) is 50.

  FIG. 55 is an explanatory diagram showing a scheduling result of the combination pattern (109) shown in FIG. In FIG. 55, the reconfiguration circuit executes task T1, and the DSP executes task T4 (T2 + T3). In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfiguration circuit is the total execution cost of task T1: 70. On the other hand, since the task T4 is executed only by the main DSP, there is no transfer cost. Therefore, the total execution cost of task T4 is 26 (= 13 + 13). Since the reconfiguration circuit and the DSP are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (109) is 70.

  FIG. 56 is an explanatory diagram showing a scheduling result of the combination pattern (110) shown in FIG. In FIG. 56, the reconfiguration circuit executes task T2, and the DSP executes task T5 (T1 + T3). In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfiguration circuit is the total execution cost of task T2: 20. On the other hand, since the task T5 is executed only by the main DSP, there is no transfer cost. Therefore, the total execution cost of the task T5 is 63 (= 50 + 13). Since the reconfiguration circuit and the DSP are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (110) is 63.

  FIG. 57 is an explanatory diagram showing a scheduling result of the combination pattern (111) shown in FIG. In FIG. 57, the reconfiguration circuit executes task T3, and the DSP executes task T6 (T1 + T2). In this way, when different calculation elements are used, they can be executed in parallel. The total execution cost of the reconfiguration circuit is the total execution cost of task T3: 20. On the other hand, since the task T6 is executed only by the main DSP, there is no transfer cost. Therefore, the total execution cost of the task T6 is 63 (= 50 + 13). Since the reconfiguration circuit and the DSP are executed in parallel, the one with the higher total execution cost is selected. Therefore, the total execution cost of the combination pattern (111) is 63.

  FIG. 58 is an explanatory diagram showing a scheduling result of the combination pattern (112) shown in FIG. In FIG. 58, the DSP executes task T7 (T1 + T2 + T3). Since task T7 is executed only by the main DSP, there is no transfer cost. Therefore, the total execution cost of task T7 is 76 (= 50 + 13 + 13). Therefore, the total execution cost of the combination pattern (112) is 76.

  The determining unit 207 determines a combination pattern that minimizes the total execution cost from among the total execution costs of the combination patterns (101) to (112) as an optimal combination pattern. Therefore, since the total execution cost of the combination patterns (105) to (108) shown in FIGS. 51 to 54 is the minimum, the combination patterns (105) to (108) are determined as the optimum combination patterns. Here, since a plurality of combination patterns are determined, among them, the combination patterns (105) and (108) of FIG. 51 or FIG.

  That is, as in the combination pattern (105), when the task T1 is assigned to the DSP and the tasks T2 and T3 are assigned to the reconfiguration circuit, an optimum combination is obtained. Similarly, when the task T1 is assigned to one main DSP and the tasks T2 and T3 are assigned to the other DSP as in the combination pattern (108), an optimal combination is obtained.

  As described above, according to the present embodiment, the target program code 300 is divided into a plurality of functions and optimized for each process in the optimization with AMP for which it is difficult to effectively extract the performance with the conventional automation technology. A process (task) is assigned to a computation element (core). Therefore, sufficient performance can be extracted with the minimum necessary calculation element configuration. In addition, since the assignment of processing was determined manually based on many years of experience and intuition, it was not necessarily optimal, whereas in this embodiment, processing (task) was assigned quantitatively. Can be determined. In addition, by dynamically reconfiguring tasks, it is possible to optimally allocate a portion that cannot be analyzed statically. If the optimum combination pattern is not obtained, the input screen 500 can be called again to reset the setting information, and tuning and scheduling can be performed again.

  As described above, since the optimization of the software in the system design and the determination of the configuration of the arithmetic element are supported, it is possible to reduce the resources and the period, and to realize a great improvement in the development efficiency. From the above, according to the present embodiment, it is possible to reduce the design burden on the designer and shorten the design period while optimizing the embedded system according to the program.

  The design support method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. Further, this program may be distributed via a network such as the Internet.

  The following additional notes are disclosed with respect to the embodiment described above.

(Appendix 1) Computer
A dividing means for dividing the target program code into a plurality of tasks;
Task execution cost calculation means for calculating an execution cost according to the execution time of each task based on the type of calculation element that executes each task obtained by the dividing means;
Generating means for generating a combination pattern representing the execution order of the tasks;
Based on the execution cost calculated by the task execution cost calculation means, a total execution cost calculation means for calculating the total execution cost according to the execution time of each combination pattern generated by the generation means,
A determination unit that determines a specific combination pattern from the combination pattern group based on the total execution cost calculated by the total execution cost calculation unit;
Output means for outputting the determination result determined by the determination means;
Design support program characterized by functioning as

(Appendix 2)
An acquisition means for acquiring setting information related to the type of the calculation element and optimization processing to be executed by the calculation element;
A function that can be executed by the optimization process according to the type of the calculation element included in the setting information acquired by the acquisition unit to function as an extraction unit that extracts the task from the plurality of tasks;
The task execution cost calculation means includes:
The design support program according to appendix 1, wherein an execution cost corresponding to an execution time of a task extracted by the extraction unit is calculated based on the setting information.

(Supplementary Note 3) The task execution cost calculation means includes:
Furthermore, the transfer cost according to the data transfer time between the calculation elements is calculated,
The total execution cost calculation means includes:
The design support program according to appendix 1 or 2, wherein a total execution cost corresponding to an execution time of each combination pattern is calculated based on an execution cost and a transfer cost calculated by the task execution cost calculation means .

(Supplementary note 4)
The design support program according to any one of appendices 1 to 3, wherein the combination pattern that minimizes the total execution cost is determined as the specific combination pattern.

(Supplementary note 5)
4. The design support program according to any one of appendices 1 to 3, wherein a combination pattern that minimizes the total execution cost and minimizes the number of calculation elements to be used is determined as the specific combination pattern.

(Appendix 6) The determination means includes:
The design support program according to any one of appendices 1 to 3, wherein a combination pattern in which the total execution cost is equal to or less than a predetermined threshold is determined as the specific combination pattern.

(Supplementary note 7)
The combination pattern in which the total execution cost is equal to or less than a predetermined threshold value and the number of use of the calculation elements is minimized is determined as the specific combination pattern. Design support program.

(Supplementary Note 8) Dividing means for dividing the target program code into a plurality of tasks;
Task execution cost calculation means for calculating an execution cost according to the execution time of each task, based on the type of arithmetic element that executes each task obtained by the dividing means;
Generating means for generating a combination pattern representing the execution order of the tasks;
Based on the execution cost calculated by the task execution cost calculation means, a total execution cost calculation means for calculating a total execution cost according to the execution time of each combination pattern generated by the generation means;
A determination unit that determines a specific combination pattern from the combination pattern group based on the total execution cost calculated by the total execution cost calculation unit;
Output means for outputting the determination result determined by the determination means;
A design support apparatus comprising:

(Supplementary Note 9) A computer including a central processing unit and a storage device is provided.
Dividing the target program code into a plurality of tasks by the central processing unit and storing the plurality of tasks in the storage device;
Accessing the storage device by the central processing unit, calculating the execution cost according to the execution time of each task, based on the type of arithmetic element that executes each task obtained by the division step, A task execution cost calculation step of storing an execution cost in the storage device;
Generating a combination pattern representing the execution order of the tasks by the central processing unit, and storing the combination pattern in the storage device;
The storage device is accessed by the central processing unit, and the total execution cost corresponding to the execution time of each combination pattern generated by the generation step is calculated based on the execution cost calculated by the task execution cost calculation step A total execution cost calculating step of storing the total execution cost in the storage device;
The central processing unit accesses the storage device, determines a specific combination pattern from the combination pattern group based on the total execution cost calculated by the total execution cost calculation step, and determines the determination result. A determination step of storing in the storage device;
An output step of accessing the storage device by the central processing unit and outputting a determination result determined by the determination step;
A design support method characterized by executing

It is a block diagram which shows the hardware constitutions of the design support apparatus concerning this Embodiment. It is a block diagram which shows the functional structure of the design assistance apparatus concerning this Embodiment. It is explanatory drawing which shows the example of 1 description of object program code. It is explanatory drawing which shows the example of a division | segmentation of the object program code shown in FIG. It is explanatory drawing (the 1) which shows an example of an input screen. It is explanatory drawing (the 2) which shows an example of an input screen. It is explanatory drawing (the 3) which shows an example of an input screen. It is explanatory drawing which shows the data structure of setting information. It is explanatory drawing which shows the data structure of allocation information. It is a flowchart which shows the design assistance process procedure concerning this Embodiment. It is a flowchart which shows the detailed process sequence of a program pattern allocation process (step S1004). It is a flowchart which shows the detailed process sequence of an analysis execution process (step S1105). It is a flowchart which shows the program pattern extraction process procedure regarding the loop parallel process of a for block. It is a flowchart which shows the program pattern extraction process procedure regarding the pipeline process of a for block. It is a flowchart which shows the extraction process procedure of the program pattern regarding the simultaneous process of a switch-case block. It is a flowchart which shows the extraction process procedure of the program pattern regarding the simultaneous process of a switch-case block. It is explanatory drawing which shows the switch-case block used as the object block, and its circuit structure information. It is a flowchart which shows the extraction process procedure of the program pattern regarding the simultaneous process of an if-else block. It is a flowchart which shows the extraction process procedure of the program pattern regarding the simultaneous process of an if block / else block. It is a flowchart which shows the program pattern extraction process procedure regarding SIMD arithmetic processing. It is a flowchart which shows the program pattern extraction process procedure regarding a VLIW instruction execution process. It is a flowchart which shows the detailed process sequence of the scheduling process shown in FIG. It is explanatory drawing which shows the setting information in Example 1. FIG. It is explanatory drawing which shows the allocation table which shows the program pattern extraction result in Example 1. FIG. It is explanatory drawing which shows the combination pattern for the optimization in Example 1. FIG. It is explanatory drawing (the 1) which shows the example which put together the task. It is explanatory drawing (the 2) which shows the example which put together the task. It is explanatory drawing (the 3) which shows the example which put together the task. It is explanatory drawing (the 4) which shows the example which put together the task. It is explanatory drawing which shows the calculation result table of the execution cost and transfer cost in Example 1. FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (1) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (2) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (3) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (4) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (5) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (6) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (7) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (8) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (9) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (10) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (11) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (12) shown in FIG. It is explanatory drawing which shows the setting information in Example 2. FIG. 12 is an allocation table showing a program pattern extraction result in the second embodiment. It is explanatory drawing which shows the combination pattern for the optimization in Example 2. FIG. It is explanatory drawing which shows the calculation result table of the execution cost and transfer cost in Example 2. FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (101) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (102) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (103) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (104) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (105) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (106) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (107) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (108) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (109) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (110) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (111) shown in FIG. It is explanatory drawing which shows the scheduling result of the combination pattern (112) shown in FIG.

Explanation of symbols

200 Design Support Device 201 Division Unit 202 Acquisition Unit 203 Extraction Unit 204 Task Execution Cost Calculation Unit 205 Generation Unit 206 Total Execution Cost Calculation Unit 207 Determination Unit 208 Output Unit 300 Target Program Code

Claims (5)

Computer
A dividing means for dividing the target program code into a plurality of tasks;
An acquisition unit that acquires the setting information regarding the type of the calculation element that executes each task obtained by the dividing unit and the optimization process to be executed by the calculation element;
Extraction means for extracting a task that can be executed by the optimization process from the plurality of tasks according to the type of calculation element included in the setting information acquired by the acquisition means;
A task execution cost calculating means for calculating an execution cost according to the execution time of the task extracted by the extracting means based on the setting information ;
Generating means for generating a combination pattern of types of arithmetic elements for executing the task;
Based on the execution cost calculated by the task execution cost calculation means, a total execution cost calculation means for calculating the total execution cost according to the execution time of each combination pattern generated by the generation means,
A determination unit that determines a specific combination pattern from the combination pattern group based on the total execution cost calculated by the total execution cost calculation unit;
Output means for outputting the determination result determined by the determination means;
Design support program characterized by functioning as The computer,
For each combination pattern generated by the generating means, based on the type of arithmetic element that executes each task, function as a determining means for determining whether each task can be executed in parallel ,
The total execution cost calculation means includes:
Based on the execution cost calculated by the task execution cost calculation means and the determination result of whether or not each task determined by the determination means can be executed in parallel, the total execution cost according to the execution time of each combination pattern design support program according to claim 1, characterized in that calculated. The task execution cost calculation means includes:
Furthermore, the transfer cost according to the data transfer time between the calculation elements is calculated,
The total execution cost calculation means includes:
The design support according to claim 1 or 2, wherein a total execution cost corresponding to an execution time of each combination pattern is calculated based on an execution cost and a transfer cost calculated by the task execution cost calculation means. program. A dividing means for dividing the target program code into a plurality of tasks;
An acquisition means for acquiring setting information related to the type of the calculation element that executes each task obtained by the dividing means and the optimization process to be executed by the calculation element;
Extraction means for extracting a task that can be executed by the optimization process from the plurality of tasks according to the type of calculation element included in the setting information acquired by the acquisition means;
Based on the setting information, task execution cost calculation means for calculating an execution cost according to the execution time of the task extracted by the extraction means;
Generating means for generating a combination pattern of types of calculation elements for executing the task;
Based on the execution cost calculated by the task execution cost calculation means, a total execution cost calculation means for calculating a total execution cost according to the execution time of each combination pattern generated by the generation means;
A determination unit that determines a specific combination pattern from the combination pattern group based on the total execution cost calculated by the total execution cost calculation unit;
Output means for outputting the determination result determined by the determination means;
A design support apparatus comprising: A computer comprising a central processing unit and a storage device,
Dividing the target program code into a plurality of tasks by the central processing unit and storing the plurality of tasks in the storage device;
An acquisition step of accessing the storage device by the central processing unit and acquiring setting information relating to the type of arithmetic element that executes each task obtained by the dividing step and the optimization processing to be executed by the arithmetic element;
Extraction that accesses the storage device by the central processing unit and extracts a task that can be executed by the optimization process from the plurality of tasks according to the type of calculation element included in the setting information acquired by the acquisition step Process,
The central processing unit accesses the storage device, calculates an execution cost according to the execution time of the task extracted by the extraction step based on the setting information, and stores the execution cost in the storage device Task execution cost calculation process to perform,
The central processing unit generates a combination pattern of types of arithmetic elements that execute the task, and a generation step of storing the combination pattern in the storage device;
The storage device is accessed by the central processing unit, and the total execution cost corresponding to the execution time of each combination pattern generated by the generation step is calculated based on the execution cost calculated by the task execution cost calculation step A total execution cost calculating step of storing the total execution cost in the storage device;
The central processing unit accesses the storage device, determines a specific combination pattern from the combination pattern group based on the total execution cost calculated by the total execution cost calculation step, and determines the determination result. A determination step of storing in the storage device;
An output step of accessing the storage device by the central processing unit and outputting a determination result determined by the determination step;
A design support method characterized by executing

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