JP2003256056A - Mos type reference voltage generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reference voltage generation circuit of a semiconductor integrated circuit having a small chip occupancy area and structured with MOSFETs for giving small influence on a reference voltage caused by fluctuation of power supply voltage and temperature. <P>SOLUTION: In a circuit having a current mirror circuit (4) with a plurality of current routes structured with a P channel MOSFET and a plurality of N channel MOSFETs connected to the current routes, the MOS type reference voltage generation circuit has N channel MOSFETs: N3, N4 serially connected to the P channel MOSFET for temperature compensation of which gate is connected to an output terminal of the reference voltage. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit formed in a semiconductor integrated circuit including MOSFETs.

[0002]

2. Description of the Related Art Today, with the demand for small-sized, low-power and high-speed circuits, most digital circuits are composed of CMOS devices satisfying such requirements, and bipolar circuits are the main analog circuits. Also in the field of, the realization by CMOS devices is desired. However, in analog circuits, unlike digital circuits, it is extremely important to realize a reference voltage generation circuit that is not affected by temperature and is not affected by fluctuations in power supply voltage. Particularly, in the analog-digital conversion circuit and the digital-analog conversion circuit, a reference voltage generation circuit that is stable with respect to the power supply voltage and the temperature is required. Therefore, CMOS
Constructing a stable reference voltage generation circuit using a circuit is an essential requirement for realizing an analog CMOS circuit.

Conventionally, a reference voltage generating circuit constructed in a semiconductor integrated circuit is a bandgap reference voltage generating circuit (hereinafter referred to as a bandgap circuit) having a start-up circuit and a current mirror circuit as shown in FIG. 9 showing a conventional example. It is composed of.

The start-up circuit is a starting circuit for promoting a transition from a stable state before power-on to a stable operation state in which a predetermined output voltage is obtained at the initial stage of power-on of the bandgap circuit. In this circuit configuration, when power is turned on, a P-channel MOSFET (hereinafter referred to as PMOSFET) P07 and an N-channel M
By rapidly raising the drain voltage of the OSFET (hereinafter referred to as NMOSFET) N09, the NM is quickly
OSFET: N06 is operating, NMOSFET: N01
And the desired gate voltage for N02 can be obtained.

Channel width: W and channel length: L are extremely important design parameters that determine the characteristics of the MOSFET. Here, by setting the width and length of the channel to a constant ratio (including the case of the same size), a constant ratio is given to the drain currents of the MOSFETs in the set. The current mirror circuit utilizes such characteristics, and for example, as shown in FIG. 9, PMOSFETs of the same size: P01,
By connecting P02 and P03 in a current mirror connection and connecting respective sources in the current mirror connection to the power supply voltage V _DD , the respective M's in the current mirror connection are formed.
The same constant current (hereinafter, referred to as drain current) is passed between the drain and the source of the OSFET.

The bandgap circuit is a circuit for generating a reference voltage depending on a silicon bandgap (hereinafter referred to as a bandgap) which is a physical constant by using a pn junction diode D01, and theoretically,
PMOSFET of the current mirror circuit: P01, P
On condition that the drain currents of 02 and P03 are equal to each other (or have a predetermined ratio), the predetermined reference voltage is stably generated without being affected by the fluctuation of the power supply voltage V _DD .

[0007]

The circuit configuration shown in the conventional figure.
Then, in order to generate a stable reference voltage against temperature changes
Necessary resistance element for temperature compensation: R '_Three, R '_FourIs used
However, normally, the resistance element R ' _ThreeIs several tens of kΩ and resistance element R '
_FourA resistance element with a very high resistance value of several hundred kΩ is used for
Therefore, the area occupied by the resistive element on the chip is large.
Occupies an area equal to or larger than that of the MOSFETs
As a result, the manufacturing cost increases.

Further, even if a difference occurs between the drain voltage of N01 and the drain voltage of N02, and even if the operating region of N01 and N02 is in the subthreshold region, the current between the drain and source of N01 and N02 is Since they do not match, the theoretically ideal operation of the current mirror circuit cannot be obtained. As a result, the current flowing through the output stage is affected by the fluctuation of the power supply voltage V _DD , and V
It was not possible to obtain a stable reference voltage V _REF for _DD .

The present invention has been made in view of the above circumstances, and has a small chip occupying area and has no influence on the reference voltage due to fluctuations in the power supply voltage or temperature. For the purpose of providing.

[0010]

A MOS type reference voltage generating circuit according to the present invention made to solve the above-mentioned problems,
A current mirror circuit having a plurality of current paths composed of PMOSFETs and currents thereof are replaced with NMOSFETs to replace the temperature compensating resistance element to reduce the chip occupation area and to generate a more stable reference voltage. In a circuit having a plurality of NMOSFETs connected to a path, the temperature compensating NMOSFETs N3 and N4 whose gates are connected to the output terminal of the reference voltage are
It is characterized by being connected in series with ET.

More specifically, a current mirror circuit having first, second and third current paths composed of PMOSFETs and having the second current path as a bias stage, and the first current path. And NMOSFET operating in the sub-threshold region, which is connected to, and NM operating in the sub-threshold region, which is connected to the second current path.
OSFET: N2, temperature compensating NMOSFET whose gate is connected to the output terminal of the reference voltage: N3, and the PMOSFET and the NMOS in the second current path.
Drain-source voltage correction NMOSFET: N5 connected in series between FET: N2, pn junction diode: D1 connected to the third current path, and temperature compensation in which the gate is connected to the output terminal of the reference voltage. NMOS FE
An example is a band gap reference voltage generating circuit configured with T: N4. According to the specifications, the PMOSFET is provided for each of the first, second and third current paths.
In some cases, a current mirror circuit is formed by connecting the two in series with each other.

Here, the bias stage is a gate of all PMOSFETs in a current mirror circuit in order to connect the same potential to the gates of all PMOSFETs in the current mirror circuit among a plurality of stages of circuits forming a current mirror circuit. In this stage, there is a common acquisition point of the potential to be connected, and NMOSFET: N3 for determining the current flowing through the stage is connected.

In order to stabilize the value of the reference voltage at the threshold voltage, a diode-connected NMOS FE is used instead of the pn junction diode D1 connected to the third current path.
A structure using T: N8 may be adopted, and further, in order to enable control of the reference voltage, the diode-connected NMO is used.
It is also possible to employ a configuration in which a substrate bias variable circuit for adjusting the substrate bias voltage V _Sub in SFET: N8 is provided. The diode-connected NMOSFET
Is an NMOSF used by short-circuiting the gate and drain
Refers to ET.

Between the power source V _DD and GND, a PMOSFET is provided.
And a diode-connected drive NMOSFET connected in series in n stages, and one drive NMOS arbitrarily selected
The drain of the FET is connected to the gate of the drain-source voltage correction NMOSFET: N5, and n is a natural number, and n ≦ (power supply voltage V _DD ) / (drive NM)
In some cases, a drive circuit satisfying the threshold voltage V _{T of the} OSFET is provided.

Further, a PMOS is connected between the power source V _DD and GND.
FET and diode-connected drive NMOSFET
Are connected in series in l stages, and a drive circuit is provided, which comprises l: natural number and l ≦ (power supply voltage V _DD ) / (threshold voltage V _T of drive NMOSFET), and the drive circuit is configured. The drain of one drive NMOSFET arbitrarily selected from among the drive NMOSFETs to be connected is connected as the power supply terminals of the first, second and third current paths constituted by the PMOSFET, and the power supply terminal A PMOSFET and a diode-connected drive NMOSFET are connected in series between the GND in n stages, and the drive NMOSFET is connected in series.
One drive NMOS FE arbitrarily selected from the above
The drain of T is the NM for correcting the drain-source voltage
OSFET: connected to the gate of N5, n: natural number, and n ≦ (power supply terminal voltage) / (drive NMOS)
In some cases, a drive circuit satisfying the threshold voltage V _{T of the} FET is provided.

In addition, one of the drive NMOSFEs arbitrarily selected from the drive NMOSFETs forming a drive circuit connected to the gate of the drain-source voltage correction NMOSFET: N5.
The drain of T is connected to the gate, the drain of the NMOSFET: N1 in the first current path is connected to the source, and the gate of the NMOSFET for drain-source voltage correction NMOSFET: N5 is connected. N for the drive forming a drive circuit
A start-up circuit using NMOSFET: N7 in which the drain of one drive NMOSFET arbitrarily selected from MOSFETs is connected to the gate and the gates of the temperature compensating NMOSFETs N3 and N4 are connected to the sources It may be configured to have.

In the MOS type reference voltage generating circuit, as described above, the drain-source voltage correcting NMOSFE is used.
In constructing a drive circuit connected to the gate of T: N5, a PMOSFET and a PMOSFET are connected between the power supply _VDD and GND.
A diode-connected drive NMOSFET is serially connected in m stages, and m is a natural number and m ≦ (power supply voltage V _D
D ) / (driving NMOSFET threshold voltage V _T ) is provided, and the drain of one driving NMOSFET arbitrarily selected from the driving NMOSFETs constituting the driving circuit is It is also possible to connect the power supply terminals of the first, second and third current paths formed by PMOSFETs.

On the other hand, in the above circuit configuration, the drain
-Source voltage correction NMOSFET: N5 gate
The diode-connected drive NMOSFET
NMO for drive connected in series in n stages and connected in series
One drive NM arbitrarily selected from SFET
Reference voltage V without connecting to the drain of OSFET
_REFIn some cases, the circuit may be connected to the output terminal of
In such a configuration, the power supply V_DD・ Between GND
In addition, PMOSFET and N for driving the diode connection
Channel MOSFETs are connected in series in q stages, and q:
Natural number and q ≤ (power supply voltage V_DD) / (N for drive
Channel MOSFET threshold voltage V_T) Is satisfied
A drive circuit may be provided.

In addition, in the circuit configuration in which the gate of the drain-source voltage correction NMOSFET: N5 is connected to the output terminal of the reference voltage in this way, the power source V _DD · GN
A P-channel MOSFET and a diode-connected drive N-channel MOSFET are connected in series between D in l stages, and l is a natural number and l ≦ (power supply voltage V _DD ) /
(Threshold voltage V of drive N-channel MOSFET
_T ) is provided, and one drive N-channel MOSF arbitrarily selected from the drive N-channel MOSFETs forming the drive circuit.
The drain of ET is connected as a power supply terminal of the first, second and third current paths (1, 2, 3) constituted by the P-channel MOSFET, and the power supply terminal / GN is connected.
A P-channel MOSFET and a diode-connected driving N-channel MOSFET are connected in series between D in q stages, and q is a natural number and q ≦ (power supply terminal voltage) /
(Threshold voltage V of drive N-channel MOSFET
_In some cases, the circuit configuration may include a drive circuit that satisfies _{T 1} ).

Further, the P-channel MOSFET and a diode-connected N-channel MOSFET for driving are connected to q
A drive circuit that is connected in series to the stage and that satisfies q: natural number and q ≦ (power supply terminal voltage) / (threshold voltage V _T of drive N-channel MOSFET) is provided, and the drive circuit is configured. N-channel MO for drive
The drain of one of the drive N-channel MOSFETs arbitrarily selected from the SFETs is connected to the gate, and the N-channel MO in the first current path is connected.
The drain of SFET: N1 is connected to the source, and the drain of one drive N-channel MOSFET arbitrarily selected from the drive N-channel MOSFET is connected to the gate. N channel MOSFE for temperature compensation
It is also possible to adopt a configuration having a start-up circuit using an N-channel MOSFET: N7 in which the gates of T: N3 and N4 are connected to the sources.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a MOS reference voltage generating circuit according to the present invention will be described below with reference to the drawings. Figure 1
The sample circuit shown in FIG. 2 is an NMO for correcting the drain-source voltage for making the drain voltages of the current mirror circuit 4 and the MOSFET of PMOSFET almost equal.
It is a reference voltage generating circuit including a bandgap circuit including SFET: N5 and a start-up circuit 6 that promotes stabilization of the operation of the bandgap circuit in the initial stage of power-on.

The bandgap circuit has a power supply voltage V
PMOSFET: P1, PMOSF between _DD and GND
A first current path 1 in which ET: P4 and NMOSFET: N1 are connected in series, and PMOSFET: P2, PMO
SFET: P5, NMO for drain-source voltage correction
Second current path 2 in which SFET: N5, NMOSFET: N2, and temperature compensating NMOSFET: N3 are connected in series, PMOSFET: P3, PMOSFET: P
6, pn junction diode: D1 and NMOS for temperature correction
It is constituted by connecting in parallel a third current path 3 in which FET: N4 is connected in series.

The current mirror circuit 4 is a PMOSF.
ET: The gate and drain of P2 and P5 are short-circuited, and P
MOSFETs: P1, P2, P3 gates, and P
MOSFET: P4, P5, P6 has a current mirror portion formed by short-circuiting the gates of each other, and is configured in a two-stage stacked three-row configuration. Further, the drain and the gate of the N1 are short-circuited, and further, the gates of the NMOSFETs N1 and N2 are short-circuited to each other.
The current mirror configuration by is also formed. Reference voltage V that is the output of the reference voltage generation circuit of the semiconductor integrated circuit
_REF is a PMOSFE that constitutes the third current path.
It is taken out from the output terminal between T: P6 and pn junction diode: D1.

The startup circuit 6 has a power supply voltage V
_{Between DD} and GND, PMOSFET: P7, drain,
N for drive with short circuit between gates and diode connection
MOSFET: N9 and drive NMOSFET:
A drive circuit 5 in which N10 is connected in series and which satisfies n: 2, and 2 ≦ (power supply voltage V _DD ) / (threshold voltage V _T of driving NMOSFET), and a drain to the power supply voltage V _DD , A startup NMOSFET: N6 in which a source is connected between P4 and N1 of the bandgap circuit and a gate is connected between N9 and N10.
When the power supply voltage _{V D} as well as a drain connected to the _D, NMOSFET for temperature compensation of the bandgap circuit: N
The source is connected to the gates of N3 and N4, and the P7
Startup NMOS with gate connected between N10
FET: N7. By operating the startup NMOSFETs N6 and N7, a desired gate voltage is quickly supplied to N1, N2 and N3, N4 to start up the bandgap circuit. The drive NMOSFET: N1
The drain of 0 is N for voltage correction between the drain and source.
It is connected to the gate of MOSFET: N5 and is used to drive the drain-source voltage correction NMOSFET: N5.

In the above structure, PMOSFET: P1,
The channel lengths and channel widths of P2 and P3 are set to be equal to each other, the channel lengths and channel widths of PMOSFET: P4, P5 and P6 are set to be equal to each other, and the channel lengths of NMOSFETs: N1 and N2 are set to be equal to each other. At the same time, the N2 channel width is set to an appropriate ratio (8 times in the circuit of FIG. 2) to the N1 channel width.

Since NMOSFETs N1 and N2 are designed to operate in the subthreshold current region,
Current I flowing through these NMOSFETs: N1 and N2
_{1 (N1)} and I2 _(N2) are given by the following equations (1) and (2),
The current I3 _(D1) flowing through the pn junction diode: D1 is the equivalent resistance value of the temperature-correcting NMOSFETs: N3, N4.
_{If 3} and R ₄ , they are given by the following equation (3).

[0027]

[Equation 1]

[Equation 2]

[Equation 3] Here, I _S : temperature-independent subthreshold current V _G : gate voltage V _T : threshold voltage n: subthreshold coefficient correction term V _t : thermal voltage (= k · T / q) k: Boltzmann constant T: Absolute temperature q: Charge amount of electrons V _D : Voltage applied to pn junction diode E _G : Bandgap of silicon

[0028] Then, the current I ₁ flowing through the first current path 1 of the bandgap circuit, a current I ₂ flowing through the second current path 2, is equal to the current I ₃ flowing through the third current path 3 If the condition (I ₁ = I ₂ = I ₃ ) is satisfied,
I ₁ , I ₂ , and I given by the above equations (1), (2), and (3)
₃ are equal to each other.

The reference voltage V _REF is given by the following equation (4).

[Equation 4]

The temperature characteristic of the reference voltage V _REF is given by the following equation (5), and the temperature characteristic of the voltage V _D applied to the pn junction diode: D1 is given by the following equation (6).

[Equation 5]

[Equation 6]

By flattening the temperature characteristic, (Δ /
When ΔT) · V _REF = 0 and substituted into the equation (5), the following equation (7) is obtained.

[Equation 7]

That is, temperature compensating NMOSFET: N3
Ratio (R ₄ / R ₃ ) of equivalent resistance values R ₃ and R ₄ of N4
If the circuit is designed so that satisfies the expression (7), the voltage of the following expression (8), which has a flat temperature characteristic and is very stable, can be obtained as the reference voltage V _REF . The V _REF
Is called a bandgap reference voltage because it is determined by the bandgap potential which is a physical constant of silicon.

[Equation 8]

In the sample circuit shown in FIG. 2, p
It is shown that the n-junction diode: D1 can be replaced by a diode-connected NMOSFET: N8 in which the drain and the gate are short-circuited. In this way, the pn junction diode: D1 is connected to the diode-connected NMOSFET: N
When replaced by 8, the current I _{3 (D1)} flowing through the pn junction diode: D1 is the diode-connected NMOS.
FET: Current I flowing between the drain and source of N8
_{3 (N8)} , which is given by the following equation (9).

[Equation 9] The temperature characteristic of the voltage applied to the diode-connected NMOSFET: N8 is given by the following equation (10), as in the case of the bandgap reference voltage V _REF .

[Equation 10]

Here, to satisfy the following equation (11)
If the circuit is designed, (Δ / ΔT) ・ V _REF= 0,
Reference voltage V as shown in equation (12) below_REFIs obtained. This
The reference voltage V_REFIs a diode-connected NMOS FE
T: Stabilized to the threshold voltage of N8 at T = 0 K
Threshold voltage reference voltage V_TRCall it.

[Equation 11]

[Equation 12]

In theory, the ideal subthreshold current of the NMOSFET is determined only by the gate voltage V _G as given by the equations (1) and (2) and does not depend on the drain voltage. Therefore, the same currents I ₁ and I ₂ should flow through the NMOSFETs N1 and N2 to which the same gate voltage is applied. However, in reality, the subthreshold current also depends on the voltage between the source and the drain, so in order to satisfy I ₁ = I ₂ exactly, the NMOS
It is necessary to make the source-drain voltages of the FETs N1 and N2 equal.

In the circuit of this embodiment, NMOSFET: N
The source voltage of ₂ becomes higher than the source voltage of NMOSFET: N1 by the voltage of I ₂ · R ₃ , but since this voltage is usually about several tens of mV, its influence on the subthreshold current can be ignored. Therefore, in this case, attention should be paid to the drain voltage difference between the NMOSFETs N1 and N2. According to the simulation result of the sample circuit, NMOSFET: N when V _DD is 5V
The drain voltages of 1 and N2 are 0.7 V and 2.7 V, respectively, when there is no source-drain voltage correction NMOSFET: N5, resulting in a drain voltage difference of about 2.0 V. Originally, in such a result, the relation of I ₁ = I ₂ = I ₃ assumed in the theoretical calculation is not strictly established, so that the stability of the reference voltage V _REF with respect to V _DD and temperature deteriorates. Can be easily guessed.

However, the above sample circuit (see FIG. 1 and FIG.
And FIG. 2), the source-drain voltage
Compensation NMOSFET: N5
Gate voltage is supplied from the
Voltage V_DDDue to fluctuations in NMOSFET: N1,
Voltage correction operation that absorbs the difference that occurs in the drain voltage of N2
Occurs, drain voltage of NMOSFET: N1, N2
Is approximately equal to 0.7V. In this way, the source
・ Drain voltage correction NMOSFET: N5 voltage compensation
The positive action is the drain flowing in the NMOSFETs N1 and N2.
Current I₁And I _TwoAnd I₁= I_Two= I_Three
As a result of the action of strictly satisfying the condition
Power supply voltage V_DDStable against changes in
Reference voltage V_REFWill be given.

[0038]

[Embodiment] The following will describe the results of trial manufacture and measurement of the above sample circuit. In order to distinguish the reference voltage V _REF extracted from the above-mentioned two types of circuits, the band gap reference voltage V _REF using the pn junction diode: D1 is referred to as V _BR, and the diode-connected NMOSFET: N8 is used. The threshold voltage reference voltage V _REF is referred to as V _TR . Sample circuit prototype is 1.2 micron rule
The well CMOS process was used.

The bandgap reference voltage _VBR of the pn junction diode D1 used in the sample circuit of FIG.
FIG. 6 shows the temperature dependence data at _DD = 3V, 4V, 5V, 6V, 7V. Measurement temperature is -60, -20, +2
0, +60, + 100 ° C. FIG. 6A shows a temperature compensating NMOSFET: N3, N4 according to an embodiment of the present invention.
6B shows the case where the temperature compensation NMOSFE is used.
T: N3, N4 resistive element is formed in n-well resistor in place of R _'3, R' ₄ (where, R _'3 is 50kΩ, R' ₄ is 63
The measurement result when 5 kΩ) is used is shown. V _DD = 5.
V _BR at 0 V and T = + 20 ° C. is about 1.1, respectively.
At 4V and about 1.26V, both consumed currents were about 6 microamps.

Diode connection used in the sample circuit of FIG.
Continuation NMOSFET: threshold voltage reference voltage by N8
V_TRFIG. 7 shows the similar measurement results in the above. At this time, the figure
7 (a) is an embodiment of the present invention, in which an NMOS for temperature compensation is used.
When FET: N3 and N4 are used, FIG.
NMOSFET for correction: N3 well N instead of N3, N4
Resistance element R'formed by resistance_Three, R '_Four(However, R '_ThreeIs 5
0kΩ, R '_FourIs 525 kΩ)
Indicates. V_DD= 5.0V, V at T = + 20 ° C _TRIs
It was about 1.14V and about 1.29V. Clear from the figure
Kana temperature compensation of NMOSFET instead of resistance element
By using it as a device for_DDNot to mention dependency
The temperature dependence was also greatly improved.

The above measurement result is used as a bandgap reference voltage.
V_BRAnd threshold voltage reference voltage V _TROf the volatility of
Is shown in FIG. In addition, ΔV on the vertical axis_BROr ΔV
_TRIs V _DD= 5.0V, T = + 20 ℃
Cap reference voltage V_BRAnd threshold voltage reference voltage V_TR
V is the standard value_DD= 3V to 7V range and V
_DD= T = -60 ° C to 10 for the range of 4V to 6V.
Bandgap reference voltage V in the measurement range of 0 ℃_BR
And threshold voltage reference voltage V_TRFrom maximum to minimum
The amount of change over time is displayed as a ratio (%) to the reference value.
It is shown.

Hereinafter, the fluctuation rate in the range of V _DD = 3V to 7V is shown outside the parentheses, and the variation in the range of V _DD = 4V to 6V is shown in the parentheses. ΔV _BR is N for temperature compensation
MOSFET: N3, by using the N4, resistive element: R in the case of using the _{'3, R' 4, 1.9} (1.1)
% To 1.2 (0.4)% with a variation rate of about 60 (40)%. Similarly, ΔV _TR is NM for temperature compensation.
By using the OSFET, the variation rate of about 75 (50)% was improved from 1.7 (1.0)% when the resistance element was used to 1.3 (0.5)%. Thus, by using the temperature compensating NMOSFETs: N3 and N4, V _BR
The V _DD dependency and the temperature dependency of V _TR were significantly improved, demonstrating their usefulness.

The measurement results described above are the measurement results when the substrate voltage V _Sub of all the NMOSFETs existing in the reference voltage generating circuit is connected to the common GND. As shown in FIG. Connection NMOS
FET: by providing the substrate bias variable circuit 7 for adjusting a substrate bias voltage _{V Sub} of the NMOSFET, including N8, for example, in a case of obtaining a threshold voltage reference voltage _{V TR,} changing the _{V Su b} Voltage Due to
The threshold voltage V _T0 of the diode-connected NMOSFET: N8 at T = 0 K can be controlled.

By applying the substrate voltage V _Sub of 0.0 V to −2.0 V to all the NMOSFETs existing in the reference voltage generating circuit, the (V _TR ) _typ voltage becomes 1.
It can be controlled in a wide range from 14V to a voltage value higher by about 0.4V. As described above, the fact that the threshold voltage reference voltage V _TR can be varied over a wide voltage range by applying the substrate voltage V _Sub means that the threshold voltage reference voltage V _BR cannot be obtained by the reference voltage source by the band gap reference voltage V _BR.
This is a feature of the reference voltage source using _TR .

Next, an embodiment in which the power supply voltage V _DD is not directly used as the power supply voltage of the bandgap circuit will be described.
The sample circuit shown in FIG. 4 is an example in which the power supply voltage of the bandgap circuit is created by the drive circuit 9 separately.
The drive circuit 9 of the sample circuit has a power supply voltage V _DD
-PMOSFET between GND: P8 and drain-
NM for drive with short circuit between gates and diode connection
OSFETs: N12, N13, and N14 are connected in series to form an NMOSFET: N14 from the drain of FIG.
The power supply voltage of the bandgap circuit shown in is supplied. In this example, 1: 3, that is, N for driving a diode connection
A drive circuit 9 in which three stages of MOSFETs are connected in series is configured and satisfies 3 ≦ (power supply voltage V _DD ) / (threshold voltage V _T of driving N-channel MOSFET). In addition, the power supply terminal G of the bandgap circuit
A diode-connected drive NMOS FE between ND and
A drive circuit 5 in which T: N9 and N10 are connected in series is configured, and 2 ≦ (power supply terminal voltage) / (drive N)
The threshold voltage V _T of the channel MOSFET is satisfied.

Further, the sample circuit shown in FIG. 5 is such that the drive N-channel is provided between the PMOSFET P7 and the drive NMOSFET N10 of the drive circuit 5 of the embodiment shown in FIG.
A drive circuit 8 in which MOSFET: N11 is inserted is provided, and the drain of N11 is connected to the sources of PMOSFETs: P1, P2, P3 that compose the current mirror circuit 4. At this time, the diode-connected drive NMOS FE
A drive circuit 8 in which T: N9, N10, and N11 are connected in series is configured and satisfies m: 3 and 3 ≦ (power supply terminal voltage) / (threshold voltage V _T of driving NMOSFET). NMO used for startup
The drains of the SFETs N6 and N7 are the power supply V _DD or N
MOSFET: Connected to either of the drains of N11.
NMOSFET: N11 of the sample circuit shown in FIG. 5 or NMOSFET: N14 of the sample circuit shown in FIG.
The drain voltage of V _DD is improved to 1.8 (1.2) V, which is about 1/2 of the fluctuation range of V _DD for 3 to 7 (4 to 6) V and 4 (2) V, It can be regarded as a simple constant voltage circuit. In the embodiment shown in FIGS. 4 and 5, FIG.
Compared with the embodiment described above, the fluctuation rate of the reference voltage is about 70 (5
0)%.

In the start-up circuit of the embodiment shown in FIGS. 1 to 5, one PMOSF is connected between V _DD and GND.
ET: P7 and two or three NMOSFETs: N9,
An example in which N10 or N11 is connected in series is shown, and the drain of the second NMOSFET: N10 from the GND side and the gate of the drain-source voltage correction NMOSFET: N5 are connected. However, depending on the circuit characteristics, the drain
Source-to-source voltage correction NMOSFET: In order to operate N5, there are n stages between V _DD and GND (however, n ≦ V _DD /
V _T ) NMOSFETs connected in series to
It is also possible to connect the drain of the desired stage to the gate of the drain-source voltage correction NMOSFET: N5 from the GND side of the OSFET.

Further, in the embodiment shown in FIG. 4, another drive circuit 9 in another stage is installed so that the drain of one drive MOSFET selected arbitrarily can be used to supply the power of the embodiment shown in FIGS. The power supply voltage was supplied to the circuit corresponding to the voltage V _DD . However, in this case, it is considered that the power consumption is increased by adding another drive circuit. Therefore, in the embodiment shown in FIG. 5, the gate voltage is supplied from the one-stage drive circuit 8 to the drain-source voltage correction NMOSFET N5 and the startup NMOSFETs N6 and N7, and to the current mirror circuit 4. By supplying the power supply voltage, the same effect as that of the embodiment shown in FIG. 4 can be obtained.

10 to 12 show another sample circuit of the present invention. These have the same components as those in FIG. 1, FIG. 4 or FIG. 5, but the gate of the drain-source voltage correction NMOSFET: N5 is connected to the output terminal of the reference voltage V _REF . They differ in points. In FIGS. 10 to 12, the drive circuit for operating the startup NMOSFETs N6 and N7 is a drain-source voltage correction NMOS.
In addition to the drive circuit 10 of FIG. 1 and FIG. 4 in which the gate of the FET: N5 is connected, the drive circuit 10 is described,
The drive circuit 1 is distinguished from the drive circuit 8 in FIG.
It is written as 1. In the sample circuits of FIGS. 10 to 12, the pn junction diode D1 is provided in the third current path 3.
However, as illustrated in FIG. 2 and FIG.
Junction diode: N diode-connected instead of D1
It goes without saying that MOSFET: N8 can be used.

V _{DD of the} reference voltage V _REF obtained by the sample circuits of FIGS. 10 and 11 is 3 V, 4 V, 5 V,
The temperature dependence data at 6V and 7V are shown in FIG. 13, and the drain-source voltage correction NMOSFET: N
Consider the effect of the circuit configuration in which the gate of 5 is connected to the output terminal of the reference voltage V _REF . In the sample circuit of FIG. 10, the variation rate of V _BR in the range of T = −60 ° C. to 100 ° C. is about 0.05% (variation value: about 0.6) as shown in FIG.
The result obtained is about 0.03% (variation value: about 0.4 m) as shown in FIG. 13B.
The result V) was obtained. This means that a variation rate ΔV _{BR of} 1/10 or less can be obtained compared with the result of the sample circuit of FIG. 1 (see FIG. 6A) of about 0.6%, and the drain-source voltage is Correction NMOSFET: N
It can be said that the effectiveness of the circuit configuration in which the gate of _No. 5 is connected to the output terminal of the reference voltage V _REF is directly proved.

1 to 5 and FIGS. 10 to 1
In the sample circuit shown in 2, the pn junction diode D1, NMOSFET: N4 or the diode-connected NMOSFET: N8, NMOSFET: N4 in this order from the power supply V _DD side between the pull-out point of the reference voltage V _REF and GND. Although connected, this order can be changed. Since the n-well CMOS process is used in the present embodiment, the diode current of the pn junction diode D1 formed in the n well may leak to the substrate due to the parasitic bipolar effect. Therefore, the pn junction diode D1 formed on another chip is used. Used, but CM of triple well structure
If an OS process or the like is used, there is no such limitation and it can be realized with one chip.

On the other hand, in the case of the reference voltage generating circuit based on the threshold voltage reference voltage V _TR , in the n-well CMOS process, the diode-connected NMOSFET: N8 has a source of I ₃ · R ₄ (where R ₄ is an NMOSFET). : Equivalent resistance value of N4), the threshold voltage reference voltage V _TR rises by the amount of V _T0 rise due to the substrate bias voltage. However, if the triple well structure CMOS process is used, the NMOSFE
Since the substrate and the source of T: N8 can be commonly connected, the change of V _T0 due to the substrate bias voltage does not occur. Also, depending on the CMOS process used, NMOSFET and PM
It is also possible to adopt a circuit configuration in which all the OSFETs are replaced. Needless to say, a bipolar transistor can be used instead of the pn junction diode D1.

[0053]

As described above, according to the MOS type reference voltage generating circuit of the present invention, the circuit element can be constituted by only the MOSFET and the pn junction diode or the MOSFET without using the resistance element which has been used conventionally. We were able to reduce the chip area and stabilize the reference voltage.

Further, in a circuit having a current mirror circuit having a plurality of current paths composed of PMOSFETs and a plurality of NMOSFETs connected to these current paths, MOSFETs for correcting the source-drain voltage of the plurality of NMOSFETs are provided. Is connected in series with the PMOSFET, and has a first, second and third current path composed of, for example, PMOSFET, and a current mirror circuit having the second current path as a bias stage, and a first current path Operating in the sub-subthreshold region connected to the
FET, NMOSFET operating in the subthreshold region connected to the second current path, and NMOSFET used in place of the resistance element, pn junction diode connected to the third current path, and resistance element Used N
In a bandgap reference voltage generation circuit including a MOSFET, the PMOS in the second current path
An NMOSFET that constitutes the current mirror circuit by adopting a configuration in which a drain-source voltage correction NMOSFET is connected between the FET and the NMOSFET.
As a result of the drain voltages of the NMOSFETs becoming almost equal,
The drain currents of V _REF were equalized, and the stability of V _REF was significantly improved.

Further, a PMOS is connected between the power source V _DD and GND.
FET and diode-connected drive NMOSFET
Were connected in series to the n stages, n: natural number, and n ≦ (power supply voltage _{V D} D) / be provided drive circuit which satisfies the (threshold voltage _{V T} of the drive for the NMOSFET), shown in Example Drain the drain voltage of an appropriate stage other than the second stage.
Since the voltage can be applied to the gate of the source-to-source voltage correction NMOSFET, it is possible to more accurately adjust the drain voltage difference between the plurality of NMOSFETs in the current mirror configuration such as N1 and N2.

The drive NMOSF of the first stage
The drain of ET is connected to the gate and the power supply V
NM in which _DD is connected to the drain and the drain of the NMOSFET in the first current path is connected to the source
OSFET: N6, the drain of the second driving NMOSFET is connected to the gate, the power supply V _DD is connected to the drain, and the NMOSFET connected to the second and third current paths instead of the resistance element. By providing a start-up circuit using NMOSFET: N7 whose gate is connected to the source, a desired gate voltage can be rapidly supplied to start up the bandgap circuit without delay. Further, the power source of the current mirror circuit 4 is the drive NMOS of the third stage.
FET: If supplied from the drain of N11, the power supply voltage V
_The power supply whose _DD change height is improved to about 1/2 is applied to the current mirror circuit 4, and the fluctuation rate of the obtained reference voltage is also greatly improved.

The bandgap reference voltage using the pn junction diode connected to the third current path is fixed to a constant value of about 1.21 V, which is determined by a physical constant called a bandgap. By using a diode-connected NMOSFET: N8 instead of the pn junction diode connected to the third current path, the reference voltage can be controlled by a threshold voltage that can be arbitrarily adjusted by the manufacturing process, and the reference voltage can be set. The range will be significantly wider. This makes it possible to cope with the tendency that the power supply voltage is reduced with the miniaturization of the CMOSFET and the reference voltage is accordingly reduced. Further, by providing the substrate bias variable circuit for adjusting the substrate bias voltage V _Sub in the diode-connected NMOSFET: N8, the threshold voltage reference voltage V _TR can be changed over a wide voltage range.

The temperature compensating NMOSFETs (N3, N4, etc.) connected instead of the temperature compensating resistance element.
_Is connected to the output terminal of the reference voltage V _REF , and the gate of the drain-source voltage correction NMOSFET (N5, etc.) is also connected to the drain of the drive NMOSFET constituting any of the drive circuits. without by connecting the output terminal of the reference voltage V _REF, it is possible to obtain a very stable reference voltage V _REF to changes in the power supply voltage V _DD and temperature.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a MOS type reference voltage generating circuit according to the present invention.

FIG. 2 is a circuit diagram showing an example of a MOS type reference voltage generating circuit according to the present invention.

FIG. 3 is a circuit diagram showing an example of a MOS type reference voltage generating circuit according to the present invention.

FIG. 4 is a circuit diagram showing an example of a MOS type reference voltage generating circuit according to the present invention.

FIG. 5 is a circuit diagram showing an example of a MOS type reference voltage generating circuit according to the present invention.

6A and 6B show a case where a temperature compensating NMOSFET is used in place of the resistance element that determines the current in the second and third current paths, and a case where a resistance element is used as in the conventional case.
Reference voltage V including the effect of voltage fluctuation
It is a graph which showed the temperature characteristic of _REF ( _VBR ).

FIG. 7 (b) shows a case where a temperature compensating NMOSFET is used in place of the resistance element that determines the current in the second and third current paths, and a case where a resistance element is used as in the conventional case.
Reference voltage V including the effect of voltage fluctuation
It is a graph which showed the temperature characteristic of _REF ( _VTR ).

FIG. 8 shows a case where a temperature compensating NMOSFET is used in place of the resistance element that determines the currents in the second and third current paths,
The reference voltage V _REF (V _BR and V _TR ) including the effect of voltage fluctuation in the case where the resistance element is used as usual.
3 is a graph showing the temperature characteristics of the graph with a fluctuation range.

FIG. 9 is a circuit diagram showing an example of a conventional MOS reference voltage generation circuit.

FIG. 10 is a circuit diagram showing an example of a MOS type reference voltage generating circuit according to the present invention.

FIG. 11 is a circuit diagram showing an example of a MOS type reference voltage generating circuit according to the present invention.

FIG. 12 is a circuit diagram showing an example of a MOS type reference voltage generating circuit according to the present invention.

13A and 13B are graphs showing the temperature characteristics of the reference voltage V _REF (V _BR ) including the influence of the voltage fluctuation of the MOS type reference voltage generating circuit shown in FIGS. 10 and 11.

[Explanation of symbols]

1 First current path 2 Second current path 3 Third current path 4 Current mirror circuit 5 drive circuit 6 Startup circuit 7 Substrate bias variable circuit 8 drive circuit 9 Drive circuit 10 drive circuit 11 Drive circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Toshihiro Matsuda             5180 Kurokawa, Kosugi-cho, Imizu-gun, Toyama Prefecture Toyama Prefectural University             On campus (72) Inventor Akira Kanemori             5180 Kurokawa, Kosugi-cho, Imizu-gun, Toyama Prefecture Toyama Prefectural University             On campus (72) Inventor Shigeki Nakajima             2184 Eguchi, Uozu City, Toyama Prefecture Shikinoha Co., Ltd.             In Itek (72) Inventor Takashi Ihara             2184 Eguchi, Uozu City, Toyama Prefecture Shikinoha Co., Ltd.             In Itek (72) Inventor Shinya Yamamoto             2184 Eguchi, Uozu City, Toyama Prefecture Shikinoha Co., Ltd.             In Itek F-term (reference) 5H420 NA23 NA27 NB02 NB25 NC02                       NE01 NE23                 5J090 AA01 AA11 AA58 CA02 CA04                       CA87 CA92 FA00 FN00 HA17                       HA19 HA25 KA00 KA09 MA21                       TA02 TA04                 5J500 AA01 AA11 AA58 AC02 AC04                       AC87 AC92 AF00 AH17 AH19                       AH25 AK00 AK09 AM21 AT02                       AT04 NF00

Claims (12)

[Claims] 1. A current mirror circuit (4) having a plurality of current paths composed of P-channel MOSFETs, and a plurality of N-channel MOSFs connected to these current paths.
In a circuit having ET, a temperature compensating N-channel MOSFET whose gate is connected to an output terminal of a reference voltage: N
A MOS type reference voltage generating circuit in which N3 and N4 are connected in series with the P-channel MOSFET. 2. A current mirror circuit (4) having first, second and third current paths (1, 2, 3) composed of P-channel MOSFETs and using the second current path as a bias stage. And an N-channel MOSFE operating in the subthreshold region connected to the first current path (1)
T: N1 and connected to the second current path (2),
N-channel MOSF operating in subthreshold region
ET: N2, temperature compensation N-channel MOSFET whose gate is connected to the output terminal of the reference voltage: N3, and the P-channel MOSFE in the second current path (2).
N-channel MOS for voltage correction between drain and source connected in series between T and the N-channel MOSFET: N2
FET: N5 and p connected to the third current path (3)
n-junction diode: D1 and temperature-compensating N-channel MOSFET whose gate is connected to the reference voltage output terminal: N
4. A MOS type reference voltage generating circuit comprising a bandgap reference voltage generating circuit together with 4. 3. The diode-connected N-channel MOSFET: N8 is used in place of the pn junction diode: D1 connected to the third current path (3), and the diode-connected N-channel MOSFET: N8 is used. MOS type reference voltage generation circuit. 4. The diode-connected N-channel MOS
4. The MOS reference voltage generating circuit according to claim 3, further comprising a substrate bias variable circuit (7) for adjusting the substrate bias voltage V _Sub in the FET: N8. 5. A P-channel M between the power supply V _DD and GND.
An OSFET and a diode-connected driving N-channel MOSFET are connected in series in n stages, and the drain of one arbitrarily selected driving N-channel MOSFET is the drain-source voltage correction N-channel MOSFET:
It is connected to the gate of N5, and n is a natural number and n ≦
(Power supply voltage V _DD ) / (Drive N-channel MOSF
5. The MOS type reference voltage generating circuit according to claim 2, further comprising a drive circuit (5) satisfying a threshold voltage V _{T of} ET. 6. A P channel M between the power supply V _DD and GND.
An OSFET and a diode-connected drive N-channel MOSFET are connected in series in l stages, and l is a natural number,
And a drive circuit (9) satisfying l ≦ (power supply voltage V _DD ) / (threshold voltage V _{T of} drive N-channel MOSFET), and the drive N-channel MOSFET constituting the drive circuit (9). The drain of one drive N-channel MOSFET arbitrarily selected from the above is connected as a power supply terminal of the first, second and third current paths (1, 2, 3) constituted by the P-channel MOSFET. In addition, between the power supply terminal and GND,
A P-channel MOSFET and a diode-connected drive N-channel MOSFET are connected in series in n stages, and one drive N-channel MOSF arbitrarily selected from the series-connected drive N-channel MOSFETs.
The drain of ET is connected to the drain-source voltage correction N
Channel MOSFET: connected to the gate of N5, and
4. A drive circuit (5) satisfying n: a natural number, and n ≦ (power supply terminal voltage) / (threshold voltage V _T of drive N-channel MOSFET), characterized in that the drive circuit (5) is provided. 5. The MOS type reference voltage generating circuit according to any one of 4 above. 7. The drain of one of the drive N-channel MOSFETs arbitrarily selected from the drive N-channel MOSFETs forming the drive circuit (5) is connected to the gate, and the first current N-channel MOSFET: N in which the drain of the N-channel MOSFET: N1 in the path (1) is connected to the source
6 and the N-channel M for correcting the drain-source voltage
OSFET: One drive N-channel MO arbitrarily selected from the drive N-channel MOSFETs forming the drive circuit connected to the gate of N5.
The drain of the SFET is connected to the gate, and the gates of the temperature compensating N-channel MOSFETs N3 and N4 are connected to the sources of the N-channel MOSFET: N7.
7. The MOS reference voltage generating circuit according to claim 5, further comprising a start-up circuit (6) using the. 8. A P-channel M between the power supply V _DD and GND.
An OSFET and a diode-connected drive N-channel MOSFET are connected in series in m stages, and m is a natural number,
And a drive circuit (9) satisfying m ≦ (power supply voltage V _DD ) / (threshold voltage V _{T of} drive N-channel MOSFET), which constitutes the drive circuit (9). The drain of one drive N-channel MOSFET arbitrarily selected from the above is connected as a power supply terminal of the first, second and third current paths (1, 2, 3) constituted by the P-channel MOSFET. The MOS type reference voltage generating circuit according to claim 2, 3 or 4, characterized in that. 9. The drain-source voltage correction N-channel MOSFET: N5 has a gate connected to a reference voltage V _REF.
Said output terminal is connected to said output terminal
5. A MOS type reference voltage generating circuit according to any one of 3 and 4. 10. A P-channel MOSFET and a diode-connected drive N-channel MOSFET are connected in series in q stages between the power supply V _DD and GND, and q is a natural number and q ≦ (power supply voltage V _DD ) / 10. The MOS type reference voltage according to claim 2, further comprising a drive circuit (10) satisfying a threshold voltage V _T of a driving N-channel MOSFET. Generator circuit. 11. A P-channel MOSFET and a diode-connected driving N-channel MOSFET are connected in series between the power supplies V _DD and GND in a l-stage, and l is a natural number and l ≦ (power supply voltage V _DD ) / A drive circuit (9) satisfying (threshold voltage V _T of drive N-channel MOSFET), and one drive arbitrarily selected from drive N-channel MOSFETs constituting the drive circuit (9). The drain of the N channel MOSFET for use is connected as a power supply terminal of the first, second and third current paths (1, 2, 3) constituted by the P channel MOSFET, and between the power supply terminal and GND. , P-channel MOSFET and diode-connected N-channel driving MOSFET are connected in series in q stages, and q is a natural number and q ≦ (power source terminal voltage) / any of the claims 2,3,4 or 9, characterized by including a drive circuit (10) which satisfies (threshold voltage _{V T} of the N-channel MOSFET Drive) MO described in crab
S-type reference voltage generation circuit. 12. The drive N-channel MOSFET arbitrarily selected from the drive N-channel MOSFETs forming the drive circuit (10).
N-channel MOSFE in which the drain of is connected to the gate and the drain of the N-channel MOSFET: N1 in the first current path (1) is connected to the source.
T: N6 and the drain of one drive N-channel MOSFET arbitrarily selected from the drive N-channel MOSFETs is connected to the gate,
N-channel MOSFETs for temperature compensation: N-channel MOSFETs in which the gates of N3 and N4 are connected to their sources:
12. The MOS type reference voltage generating circuit according to claim 10, further comprising a startup circuit (6) using N7.