JP2003255883A - Image display device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase average luminance of an image display device by extending the light emitting time per display element. <P>SOLUTION: The period of clock signals CLK3 which are used to synchronize the driving control of an SED panel is made longer than clock signals CLK2 which are synchronized to color burst signals of inputted video signals and is made equal to or less than (vertical synchronization interval/vertical video interval)*(horizontal synchronization interval/horizontal video interval) times. Moreover, driving horizontal synchronization signals VD4 of the panel which are determined based on the signals CLK3 are extended with respect to driving horizontal synchronization signals HD2 of the inputted video signals, the horizontal synchronization interval and the horizontal video interval are extended and the driving time of cold cathode elements is extended. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device for driving a display element such as an electron emitting element such as a cold cathode element or an EL element connected to a row wiring and a column wiring and displaying an image by the display element. It is a thing.

[0002]

2. Description of the Related Art Conventionally, some elements have been known as display elements. For example, it is an electron-emitting device or an electroluminescence device. An electroluminescent element is an element that emits light when a voltage is applied. The electron-emitting device obtains light necessary for displaying by combining with the phosphor, and the electron-emitting device is also one of the display devices. Two types of electron-emitting devices are known, a hot cathode device and a cold cathode device. Among them, the cold cathode device is, for example, a surface conduction type emission device, a field emission type device (hereinafter referred to as FE (Field Emission) type), a metal / insulating layer / metal type emission device (hereinafter referred to as MIM (Metal-Insu)).
lator-Metal) type), etc. are known.

The surface conduction electron-emitting device is, for example, M.
I. Elinson, Radio E-ng. ElectronPhys., 10, 1290, (19
65) and other examples described later are known.

The surface conduction electron-emitting device utilizes a phenomenon in which electron emission occurs when a current is passed through a thin film having a small area formed on a substrate in parallel with the film surface. The surface conduction electron-emitting device includes Sn by Erlinson et al.
In addition to the one using an O ₂ thin film, the one using an Au thin film [G.
Dittmer: “Thin Solid Films”, 9, 317 (1972)] and I
n ₂ O ₃ / SnO ₂ thin film [M. Hartwell and C.
G. Fonstad: IEEE Trans. ED Conf. ", 519 (1975)]
And carbon thin film "Haraki Araki et al .: Vacuum, No. 26
Vol. 1, No. 22, 22 (1983)] and the like are reported.

As a typical example of the device configuration of these surface-conduction type emission devices, FIG. 12 shows a plan view of the device by M. Hartwell et al. In the figure, 3001 is a substrate, and 3004 is a conductive thin film made of metal oxide formed by sputtering. The conductive thin film 3004 is formed in an H-shaped plane shape as illustrated. The conductive thin film 3
The electron emission portion 3005 is formed by performing an energization process called energization forming described below on 004. In the figure, the interval L is 0.5 to 1 [mm], and W is 0.1 [m].
m] is set. For convenience of illustration, the electron emitting portion 3005 is shown in a rectangular shape in the center of the conductive thin film 3004, but this is a schematic one, and the actual position and shape of the electron emitting portion is faithfully expressed. It doesn't mean that.

M. In the above-mentioned surface conduction electron-emitting device including the device by Hartwell et al., It is common to form the electron-emitting portion 3005 by subjecting the conductive thin film 3004 to an energization process called energization forming before the electron emission. there were. That is, the energization forming means a constant DC voltage across the conductive thin film 3004,
Alternatively, for example, a DC voltage that is boosted at a very slow rate of about 1 V / min is applied to conduct electricity to locally destroy, deform, or alter the conductive thin film 3004, and electrons in an electrically high resistance state are applied. That is, the emission portion 3005 is formed. A crack occurs in a part of the conductive thin film 3004 which is locally destroyed, deformed or altered. Conductive thin film 3004 after the energization forming
When an appropriate voltage is applied to, the electrons are emitted near the crack.

An example of the FE type is, for example, WP Dyke &
WWDolan, “Field emission”, Advance in Electron P
hysics, 8, 89 (1956) or CASpindt, “Phys
icalproperties of thin-film field emissioncathodes
with molybdenium cones ”, J. Appl. Phys., 47, 524
8 (1976) is known.

As a typical example of the FE type element structure, FIG. 13 shows a sectional view of the element by the above-mentioned CASpindt et al.
In the figure, 3010 is a substrate, 3011 is an emitter wiring made of a conductive material, 3012 is an emitter cone,
Reference numeral 013 is an insulating layer and 3014 is a gate electrode. In this device, by applying an appropriate voltage between the emitter cone 3012 and the gate electrode 3014, the emitter cone 3
The field emission is caused from the tip of 012.

As another FE type element structure, FIG.
There is also an example in which the emitter and the gate electrode are arranged on the substrate substantially parallel to the plane of the substrate, instead of the laminated structure of No. 3.

As an example of the MIM type, for example, C.I.
A. Mead, “Operation of tunnel-emission Devices, J.
Appl. Phys., 32,646 (1961) and the like are known. MI
FIG. 14 shows a typical example of the M-type element configuration. This figure is a cross-sectional view. In the figure, 3020 is a substrate, and 3021
Is a lower electrode made of metal, 3022 is a thin insulating layer with a thickness of about 10 nm, and 3023 is an upper electrode made of metal with a thickness of about 8 to 30 nm. In the MIM type, the upper electrode 30
Electrons are emitted from the surface of the upper electrode 3023 by applying an appropriate voltage between the upper electrode 3023 and the lower electrode 3021.

The cold cathode device described above can obtain electron emission at a lower temperature than the hot cathode device, and thus does not require a heater for heating. Therefore, the structure is simpler than that of the hot cathode device, and a fine device can be manufactured. Even if a large number of elements are arranged on the substrate with high density, problems such as heat melting of the substrate are unlikely to occur. In addition, the response speed is slow because the hot cathode element operates by heating the heater, and the cold cathode element has an advantage that the response speed is fast. Therefore, research for applying the cold cathode device has been actively conducted.

[0012] For example, the surface conduction electron-emitting device has an advantage that a large number of devices can be formed over a large area because it has a particularly simple structure and is easy to manufacture among cold cathode devices. Therefore, for example, JP-A-64-313 by the present applicant
As disclosed in No. 32, methods for arranging and driving a large number of devices have been investigated.

Regarding the application of the surface conduction electron-emitting device, for example, an image forming apparatus such as an image display apparatus and an image recording apparatus, a charged beam source and the like have been studied. In particular,
As an application to an image display device, for example, as disclosed in US Pat. No. 5,066,883 by the present applicant, JP-A-2-257551 and JP-A-4-28137, a surface conduction electron-emitting device and an electron beam are used. An image display device using a combination of a phosphor that emits light upon irradiation has been studied. An image display device using a combination of a surface conduction electron-emitting device and a phosphor is expected to have better characteristics than other conventional image display devices. For example, it can be said that it is superior in that it does not require a backlight because it is a self-luminous type and that it has a wide viewing angle, even compared with liquid crystal display devices that have become popular in recent years.

A method for driving a large number of FE types is described in, for example, USP 4,904,895 by the present applicant.
Is disclosed in. Further, as an example in which the FE type is applied to an image display device, for example, a flat panel display device reported by R. Meyer et al. Is known. [R. Meyer: “Recent De
velopment on Microtips Display at LETI ”, Tech.Di
gest of 4th Int. Vacuum Microelectronics Conf., Na
gahama, pp. 6-9 (1991)]

An example in which a large number of MIM types are arranged and applied to an image display device is disclosed in, for example, Japanese Patent Laid-Open No. 3-5.
No. 5738.

On the other hand, a CRT (Catode) is used as an image display device.
Ray tube) method is widely known.

In the CRT method, an electromagnetic deflection method is used in which a deflection current is passed through a deflection coil mounted on the CRT and an electron beam is deflected by a generated magnetic field. The electromagnetic deflection coil includes a horizontal deflection coil for deflecting in the horizontal direction and a vertical deflection coil for deflecting in the vertical direction. The horizontal deflection coil obtains a sawtooth current by causing resonance by the capacitance C connected in parallel with the inductance L of the coil. On the other hand, since the vertical deflection coil has a long deflection cycle, it is difficult to obtain a deflection current by resonance as in the horizontal deflection coil. Therefore, as shown in FIG. 15A, the transistors 4102 and 4103 form a push-pull circuit. A sawtooth current is obtained by driving the deflection coil 4100 via a DC blocking capacitor 4101. The vertical deflection coil 4100 is equivalently represented by a series circuit of an inductance L and a resistance R.
By applying a square wave pulse voltage to this, a voltage waveform of 4104 is generated at both ends of the vertical deflection coil 4100,
A sawtooth current 4105 can be obtained. For the above structural reasons, the image display device using the CRT is shown in FIG.
The blanking period T2 is required for the display period T1 of. The blanking period T2 can be shortened by increasing di / dt. However, it is necessary to increase the applied voltage or decrease the inductance L, and it is possible to shorten the calculated value. However, considering the efficiency and the like, it was not very realistic. From such characteristics of the image display device using the CRT, NTSC (National Television System Commi
ttee), PAL (Phase Alternation by Line), HD
For each format such as TV, a time corresponding to a blanking period is prepared in the video signal, and conventionally, this time is an invalid period because there is no video data.

Although some display elements and a CRT type image display device have been described above, in a matrix control type image display device in which a large number of display elements are arranged and driven, NTSC, PAL, HDTV, etc. signal retrace lines are returned. The period was not being used effectively.

[0019]

The line selection (selection in the row direction of the matrix) of the matrix control type image display device can be handled digitally, unlike the electromagnetic deflection of the CRT. Therefore, since the row selection circuit can be configured by a simple switch or the like, the time required for line selection is hardly required, and the retrace line period is often not necessary. On the other hand, since the brightness depends on the average lighting time of the display element, it is necessary to extend the lighting time as much as possible.

The present invention has been made in order to solve the problems of the prior art, and its object is to extend the light emission time per display element and increase the average luminance of the image display device. Especially.

[0021]

In order to achieve the above object, the present invention electrically connects a plurality of row wirings, a plurality of column wirings, any one of the row wirings, and any one of the column wirings. A plurality of display elements to be controlled, a row selection drive circuit that selects and drives one of the row wirings, and a modulation signal that is modulated based on an input video signal is applied to each of the column wirings. A column wiring driving circuit for driving the column wiring, and a signal generation circuit for generating a control signal for determining a driving period of a row selection signal for selecting the row wiring, and having a predetermined vertical synchronization period and vertical video period. An image display device for displaying an image based on an input video signal having a horizontal synchronization period and a horizontal video period, wherein a driving period of the row selection signal determined by a control signal generated by the signal generating circuit is , Screen input To the horizontal video period signal longer than 1 times, an image display device is (vertical synchronization period / vertical image period) * (horizontal synchronizing period / horizontal picture period) times or less.

The driving period of the row selection signal determined by the control signal is (vertical synchronization period / vertical image period) * (horizontal synchronization period / horizontal image period) with respect to the horizontal image period of the input video signal. It may be doubled.

The driving period of the row selection signal determined by the control signal may be (vertical synchronization period / vertical image period) times the horizontal image period of the input video signal.

The cycle of the clock signal serving as the reference of the control signal is 1 of the cycle of the sampling reference clock signal serving as the reference when sampling the input video signal.
It may be longer than twice and (vertical synchronization period / vertical image period) * (horizontal synchronization period / horizontal image period) times or less.

The cycle of the clock signal serving as the reference of the control signal is (vertical synchronization period / vertical image period) * (horizontal synchronization) of the period of the sampling reference clock signal serving as the reference when sampling the input video signal. Period / horizontal image period).

The cycle of the clock signal serving as the reference of the control signal is (vertical synchronization period / vertical video period) times the cycle of the sampling reference clock signal serving as the reference when sampling the input video signal. You may

The signal generating circuit compares the clock generating circuit for generating the clock signal, the counter circuit for counting the clock signal, and the output of the counter circuit with a predetermined value to synchronize the driving of the row wiring. A drive horizontal synchronization signal for outputting the row selection signal, and a row circuit is selected in a cycle of the drive horizontal synchronization signal, and the row wiring is driven according to the row selection signal. Good.

It is preferable that the counter circuit has a function of resetting a count value in response to the input of a vertical synchronizing signal of the input video signal or a signal synchronized with the vertical synchronizing signal.

The clock generation circuit may include a crystal oscillator that oscillates a fixed frequency.

The clock generation circuit compares the phase of the reference signal with the phase of the comparison target signal, a filter for removing a predetermined frequency component from the output signal of the phase comparison circuit, and the voltage of the output signal of the filter. A voltage-controlled oscillation circuit that oscillates and outputs a signal having a frequency corresponding to a value; and a frequency-dividing circuit that frequency-divides the output signal of the voltage-controlled oscillation circuit. A phase synchronization circuit has a PLL circuit input as a comparison target signal, and a clock signal generated by the clock generation circuit is a horizontal synchronization signal or a vertical synchronization signal of a video signal input as the reference signal to the phase comparison circuit. The voltage controlled oscillator circuit may oscillate and output in synchronization with the above.

The clock generation circuit preferably has a function of changing the frequency of the generated clock signal.

The comparison circuit may have a function of comparing with a predetermined value according to the type of the input video signal.

The input video signal is an HDTV (Hi
gh Definition Television), SDTV (Standard def)
inition Television), VGA (Video Graphics Arra)
y) and XGA (Extended Graphics Array).

The modulated signal is a signal modulated by a pulse width modulation method, and the pulse width modulated basic clock signal is an output of the clock generation circuit or a signal obtained by dividing the output of the clock generation circuit. Good.

The modulated signal may be a signal modulated by a pulse amplitude modulation method.

The display device is preferably a surface conduction electron-emitting device.

Further, according to the present invention, a plurality of row wirings, a plurality of column wirings, a plurality of display wirings electrically controlled by the row wirings and the column wirings, and the row wirings. A row selection drive circuit for selecting and driving any of the above, and a column wiring drive circuit for driving the column wiring by applying a modulation signal modulated based on an input video signal to each of the column wirings, A signal generation circuit that generates a control signal that determines a driving period of a row selection signal that selects the row wiring, and has a predetermined vertical synchronization period, vertical video period, horizontal synchronization period, and horizontal video period. A driving method of an image display device for displaying an image based on a video signal, wherein a driving period of the row selection signal determined by a control signal generated by the signal generating circuit is a horizontal video of an input video signal. For the period 1 times longer, a (vertical synchronization period / vertical image period) * driving method (horizontal synchronizing period / horizontal picture period) times or less the image display device is.

The driving period of the row selection signal determined by the control signal generated by the signal generating circuit is (vertical synchronization period / vertical video period) * (horizontal synchronization period) with respect to the horizontal video period of the input video signal. Period / horizontal image period).

The driving period of the row selection signal, which is determined by the control signal generated by the signal generating circuit, is (vertical synchronization period / vertical image period) times the horizontal image period of the input video signal. You may

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on the illustrated embodiments.

(First Embodiment) In the first embodiment, when a modulation circuit using a pulse width modulation method (PWM) is used,
The period of the PWM (pulse width modulation) reference clock and the row selection signal is longer than 1 time the horizontal sync signal and is between (vertical sync period / vertical video period) * (horizontal sync period / horizontal video period) times or less. The following is an example of controlling the value.

FIG. 1 shows an SED (Surface-Conducti) constituting a matrix display device (image display device) according to the present invention.
on Electron-Emitter Display) The block diagram of the drive circuit of the panel is shown.

On the display panel (P2000), 480 *
The 2160 cold cathode devices (P2001) are matrix-wired by vertical 480 row wirings and horizontal 2160 column wirings, and electrons emitted from each surface conduction element (P2001) are supplied by the high-voltage power supply unit (P30). Light is obtained by being accelerated by the applied high voltage and being irradiated on a phosphor (not shown).

The phosphor (not shown) can have various color arrangements depending on the application, but as an example, the color arrangement of RGB vertical stripes is adopted.

In the present embodiment, the horizontal 216 will be described below.
0 (RGB trio) * Shows an application example of displaying a television image equivalent to NTSC on a display panel having a number of pixels of 480 vertical lines, but not limited to NTSC, a high-definition image such as HDTV or an output image of a computer, etc. Image signals having different resolutions and frame rates can be easily dealt with by the almost same configuration.

The NTSC-RGB decoder section (P1) is
It receives an NTSC composite video input and outputs RGB components. In this unit, the sync signal (SYNC) superimposed on the input video signal is separated and output. Similarly, the color burst signal superimposed on the input video signal is separated, and C is synchronized with the color burst signal.
The LK signal (CLK1) is generated and output.

The timing generator (P2) is an NTSC-
To synchronize the analog RGB signal decoded by the RGB decoder unit (P1) with the timing signal necessary for converting into a digital gradation signal for brightness-modulating the display panel (P2000) and the high-voltage power supply unit P30. The horizontal synchronizing signal is generated and the following operations are mainly performed.

Output of a clamp pulse for direct-current regeneration of the RGB analog signal from the NTSC-RGB decoder section (P1) in the analog processing section (P3).

Output of a blanking pulse (BLK pulse) for adding a blanking period to the RGB analog signal from the NTSC-RGB decoder section (P1) in the analog processing section (P3).

Output of a detection pulse for detecting the level of the RGB analog signal in the video detection section (P4).

・ Analog RGB signal to A / D section (P6)
Output of sample pulse (not shown) for converting into digital signal.

PL generated in the timing generation unit (P2) when the CLK1 is input and generated in the timing generation unit (P2)
Free running CLK signal (CL
Output of K2).

CLK2 in the timing generator (P2)
Output of the synchronization signal (SYNC2) generated based on the.

Output of a horizontal synchronizing signal (HD) for synchronizing with the high voltage power source (P30) in a horizontal cycle.

The analog processing unit (P3) is an NTSC-R
It is provided for each output primary color signal from the GB decoder unit (P1) and mainly performs the following operation.

Receiving a clamp pulse from the timing generating section (P2) to perform DC regeneration.

Receive a BLK pulse from the timing generator (P2) and add a blanking period.

NTSC-RGB receiving the gain adjustment signal of the D / A section (P14) which is one of the control outputs of the system control section mainly composed of the MPU (P11)
The amplitude of the primary color signal input from the decoder unit (P1) is controlled.

The NTSC-R receives the offset adjustment signal of the D / A section (P14), which is one of the control outputs of the system control section composed mainly of the MPU (P11).
The black level of the primary color signal input from the GB decoder unit (P1) is controlled.

The video detection section (P4) detects the input video signal level or the video signal level after being controlled by the analog processing section (P3). A pulse is received from the timing generation section (P2), and the detection result is read by the A / D section (P15), which is one of the control inputs of the system control section centered on the MPU (P11).

The detection pulse from the timing generator (P2) is composed of, for example, three kinds of gate pulse, reset pulse and sample & hold (hereinafter referred to as S / H) pulse, and the video detector (P4) is, for example, an integrating circuit. And S / H circuit.

For example, during the effective period of the input video signal by the gate pulse, the video signal is integrated by the integrating circuit and the output of the integrating circuit is sampled by the S / H circuit by the S / H pulse generated in the vertical blanking period. A / D during the same vertical blanking period
After the detection result is read by the section (P15), the reset circuit initializes the integrating circuit and the S / H circuit.

By such an operation, the average video level for each field can be detected.

The LPF (P5) is a pre-filter means placed before the A / D section (P6).

The A / D section (P6) receives the sample pulse (not shown) from the timing generating section (P2) and receives the LP signal.
It is an A / D converter means for quantizing the analog primary color signal that has passed through F (P5) with the required number of gradations.

The inverse γ table (P7) is a gradation characteristic conversion means provided for converting the input video signal into the light emission characteristic of the display panel. When the brightness gradation is expressed by pulse width modulation as in the present embodiment, it often exhibits a linear characteristic that the light emission amount is substantially proportional to the size of the brightness data. On the other hand, the video signal is a TV using a CRT.
Since it is intended for a receiver, γ processing is performed to correct the non-linear light emission characteristic of the CRT. For this reason,
As in this embodiment, a TV with a panel having a linear light emission characteristic
When displaying an image, it is necessary to cancel the effect of the γ processing by a gradation characteristic conversion means such as the inverse γ table (P7).

The system control unit mainly uses the MPU (P
11), serial communication I / F (P16), I / O control unit (P13), D / A unit (P14), A / D unit (P1)
5), data memory (P17), user SW means (P
18).

The system control section uses the user SW
By receiving a user request from the means (P18) and the serial communication I / F (P16) and outputting a corresponding control signal from the I / O control unit (P13) or D / A unit (P14), the request is sent. To be realized.

For example, in the case of the above-mentioned inverse γ processing, the user S
By inputting the W means (P18), the I / O control unit (P1
3) is controlled and the data of the inverse γ table (P7) is switched to change the light emission characteristic to a desired one.

The horizontal 1-line memory means (P10) is
R, G, and B primary color signals are provided, and R, G, and B are simultaneously written by a reset signal which is a control signal from the line memory control unit (P23) and a clock (CLK2), and reading is controlled separately. By doing R
The brightness data input in parallel from the three systems of GB is rearranged in the order according to the panel color arrangement, converted into a serial signal of one system, and output to the field memory (P9).

Field memory write controller (P1
2) has a comparator 1 (P5002), a comparator 2 (P5003), a comparator 3 (P5004), and a comparator 4 (P5005), as shown in FIG.
Write enable and write line reset signals are output. Each comparator can switch the comparison value based on the signal of the timing switching 2 from the MPU (P11), and the optimum control pulse can be created by the input signal of NTSC, HDTV, VGA (PC).

The field memory means (P9) resets the write line output from the field memory write controller (P12) synchronized with the memory write vertical sync signal VD2 (T201) and the memory write horizontal sync signal HD2 (T202) shown in FIG. By controlling the line address in the field memory by the signal (T204), the write enable signal (T203) in FIG. 3 is enabled (L level), that is, in the video period from the 1st line to the 480th line, CLK2. Synchronize and write. In the horizontal blanking period for each horizontal and the vertical blanking period after 480 lines, writing is disabled by disabling the write enable (H level). By this operation, only the video signal data in the video period is stored in the field memory means (P9).

The panel control reference signal generator (P8) as a signal generator has an oscillation frequency of the field memory (P8).
9) Write clock CLK2 longer than 1 time,
(Vertical video period / vertical sync period) * (horizontal video period / horizontal sync period) It has the oscillation circuit (clock generation circuit) (P3000) of FIG. The oscillation output obtained here is input to a counter (counter circuit) (P3001). CLK3 is a read clock of the field memory (P9) and a shift clock of the shift register (P1101).

Further, the counter (P3001) of FIG. 4 is reset by the output VD (T201) of the timing generator (P2), counts by the oscillation output of the oscillator circuit (P3000), and the comparator 1 (P3002 of FIG. 4). ),
Comparator 2 (P3003), comparator 5 (P3006), comparator 6 (P3007), and comparator 7 (P3008) are shown in FIG.
The drive vertical synchronizing signal VD3 (T210) and the drive horizontal synchronizing signal HD3 (T211), the PWM data load signal (T250) and the PWM clock (T252), and the line selection signal are generated. The comparator 3 (P3004) and the comparator 4 (P3005) output the field memory read enable (T212) and the field memory line reset (T213) of FIG. 3 for controlling the reading of the field memory (P9). In addition, the oscillator circuit (P300
0), comparator 1 (P3002), comparator 2 (P300
3), comparator 3 (P3004), comparator 4 (P300
5), comparator 5 (P3006), comparator 6 (P300
7), the comparator 8 (P3008) is an I / O controller (P1
3) is connected to the MPU (P11) via
U (P11) distinguishes the signal from A / D (P15),
Oscillation frequency for each signal timing by switching the oscillation frequency and the comparison value by the signal of the timing switching 1 via the I / O control unit (P13) for each signal format such as HDTV, NTSC, VGA (PC), etc. , Signal timing can be output. Here, the comparator 1 (P3002) to the comparator 8 (P3008) form a comparison circuit. Further, the counter (P3001) may be reset by a signal synchronized with VD (T201).

Y driver control timing generator (P1
9), the X driver control timing generator (P20)
Receiving a signal from the panel control reference signal generating section (P8), it generates a Y driver control signal and an X driver control signal.

The control section (P23) uses the line memory (P1
0) timing control, CLK1, CLK2
The brightness data that receives the HD and VD signals is stored in the line memory (P
10) R, G, B_WRT control signals for writing to and 10) R, G, B_RD control signals for reading the luminance data from the line memory (P10) in the order according to the panel color arrangement.

The waveform T104 of the color sample data string shown in FIG. 6 as an example of one of the RGB colors is composed of 720 data strings in one horizontal period. This data string is line memory (P1
Write to 0). In the next horizontal period, the line memory (P10) for each color is read out and validated at a frequency three times as high as that in the writing, so that 2160 luminance data strings T105 are obtained per horizontal period as shown in FIG.

In the present embodiment, the example in which the color sample data strings are rearranged in the line memory has been described. However, the color sample data strings may be rearranged simultaneously while increasing the brightness in the field memory. The line memory could be reduced.

The shift register (P1101) is a shift clock which synchronizes the luminance data string of 2160 column wiring lines for each horizontal period from the latch means (P22) with the luminance data from the X driver control timing generator (P20). Read by (T107), LD pulse (T108)
(See FIG. 2) The PWM generator section (P110
In 2), 2160 pieces of data for one row are transferred at one time.

The PWM generator section (P1102) provided for each column wiring receives the brightness data from the shift register (P1101), and outputs a pulse proportional to the size of the data for each horizontal cycle as shown by the waveform T110 shown in FIG. Generates a pulse signal with a width.

The switch means (P1104) is composed of a transistor or the like, and includes a PWM generator section (P110).
2) Apply the voltage to the column wiring during the period when the output from
The column wiring is grounded while the output from the WM generator section (P1102) is invalid. FIG. 6 shows a column wiring drive waveform (T1
11) shows an example. Here, the shift register (P11
01), the PWM generator section (P1102) and the switch means (P1104) form a column wiring drive circuit.

The Y shift register section (P1002) is
A line enable pulse for scanning a row wiring is received for each row wiring in response to a horizontal period shift clock from the driver control timing generator (P19) and a vertical period trigger signal for giving a row scanning start trigger. The data is sequentially output to the driver unit (P1003).

The output section for driving each row wiring is, for example, transistor means (P1006), FET means (P1004).
Composed of.

The pre-driver unit (P1003) is for driving this output unit with good response. The FET means (P1004) is a switch means that conducts when a row is selected, and the -V from the constant voltage regulator section (P1005) is selected when the row is selected.
The ss potential is applied to the row wiring. Transistor means (P1
006) is a switch means which is turned on when the non-row is selected, and Vus from the constant voltage regulator unit (P1006) when the non-row is selected
An o potential is applied to the row wiring. Here, a row wiring drive circuit is configured by the Y shift register section (P1002), the pre-driver section (P1003) and the FET means (P1004).

In the present embodiment, the drive vertical synchronizing signal VD of FIG. 5 which is an output from the panel control reference signal generating section (P8).
3 (T210), drive horizontal synchronization signal HD3 (T21
1), field memory read enable signal (T21
2), field memory line reset signal (T21
3), the PWM load signal (T250) and the PWM clock (T252), the drive vertical synchronizing signal VD3 (T21)
0) becomes the same cycle as the vertical synchronizing signal VD2 (T201) which is the reference of the write timing of the field memory (P9), and the counter (P3001) of the field memory read timing generating section is controlled by the output VD of the timing generating section (P2). Reset and drive horizontal sync signal HD3
(T211), field memory read enable signal (T212), field memory line reset signal (T213), PWM load signal (T250), PWM
By multiplying the cycle of the clock (T252) by (vertical sync period / vertical video period) * (horizontal sync period / horizontal video period) for the purpose of deleting the vertical blanking period and the horizontal blanking period, the field memory (P9 ) And the shift register (P1101), if the row selection period (effective period of one line) is originally the first line selection signal (T20
6) Second line selection signal (T207), third line selection signal (T208), fourth line selection signal (T209)
...... becomes the first line selection signal (T21
5) Second line selection signal (T216), third line selection signal (T217), fourth line selection signal (T218)
The effective period of one line is extended by allocating the vertical blanking period and the horizontal blanking period to each horizontal period so that.

As described above, in this embodiment, the display panel is driven line by line. Therefore, by performing the processing for extending the effective period of one line as described above, the driving time of each cold cathode element is extended, whereby the amount of electrons received by the phosphor (not shown) is increased and the brightness is increased. it can.

(Example 1-1) Example 1-1 will be described as a more specific example of the first embodiment.

In Example 1-1, the NTSC signal of 240 lines in the vertical video period and 263 lines in the vertical synchronization period is set to 1
When a video signal that is sampled with a clock of 3.5 MHz and converted into a digital signal with a horizontal video period of 768 dots and a horizontal synchronization period of 857 dots is input, the cycle of the control signal for driving the panel is An example of controlling the horizontal video period to be (vertical sync period / vertical video period) * (horizontal sync period / horizontal video period) times will be described with reference to FIG.

The NTSC vertical synchronization period indicated by T301 corresponds to approximately 16.6 mS and 263 lines. T30
The vertical video period shown in 2 corresponds to about 15 mS, 240 lines. The cycle of the vertical synchronizing signal (T303) which is the control signal output from the panel control reference signal generating unit (P8) as the signal generator is equal to the vertical synchronizing period of NTSC shown at T301.

On the other hand, the NTSC horizontal synchronizing period indicated by T310 corresponds to about 63.5 μS, 857 dots. T
The horizontal image period shown in 311 is about 57.2 μS, 768.
Corresponds to a dot.

Here, the frequency of the clock (CLK3) of the panel control signal generator (P8) of the first embodiment is set to NTSC.
1 / ((vertical sync period / vertical video period) * (horizontal sync period / horizontal video period)) times 13.5 MHz, that is,

[Equation 1] By doing so, the output of the counter (P3001) of the first embodiment is set to the comparator 5 (P3006) and the comparator 7 (P300).
8) counted 768,

[Equation 2] And an extended horizontal synchronizing signal (T312) is obtained. This controls the row selection signal and the LD pulse necessary for driving the panel of the first embodiment, and also 11.12 MH
By performing PWM (pulse width modulation) with the clock of z, the video period can be allocated to the vertical blanking period in T302 and the horizontal blanking period in T311 to obtain a video signal without blanking (T313). .
As a result, by increasing the image period, the emission time of the electron source including a plurality of cold cathode elements can be extended and the brightness can be increased.

In this embodiment, the clock (CLK3) of the panel control signal generator P8 of the first embodiment is 1 / ((vertical sync period / vertical video period) * (horizontal sync period / horizontal) of 13.5 MHz obtained by sampling NTSC. Although the calculation example in the case of multiplying the video period)) is described, this value is a value that maximizes the brightness, and the clock (CLK3) of the panel control signal generation unit P8 is lower than 13.5 MHz, 11.12.
If the frequency is higher than MHz, the increase in brightness can be realized.

(Example 1-2) Another example 1-2 of the first embodiment will be described.

In Example 1-2, the NTSC signal of 240 lines in the vertical video period and 263 lines in the vertical synchronization period is set to 1
When a video signal that is sampled with a clock of 3.5 MHz and converted into a digital signal with a horizontal video period of 768 dots and a horizontal synchronization period of 857 dots is input, the cycle of the control signal for driving the panel is An example of controlling the horizontal video period to be twice the vertical synchronization period / vertical video period will be described with reference to FIG.

The vertical synchronizing period of NTSC indicated by T401 corresponds to about 16.6 mS and 263 lines. T40
The vertical video period shown in 2 corresponds to about 15 mS, 240 lines. The period of the vertical synchronizing signal (T403) which is the control signal output from the panel control reference signal generating unit (S8) as the signal generator is equal to the vertical synchronizing period of NTSC indicated by T401.

On the other hand, the NTSC horizontal synchronization period indicated by T410 corresponds to about 63.5 μS, 857 dots. T
The NTSC video period indicated by 411 is about 57.2 μS, 7
This corresponds to 68 dots.

Here, the frequency of the clock (CLK3) of the panel control signal generator (P8) of the first embodiment is set to NTSC.
1 / (vertical synchronization period / vertical video period) times 13.5 MHz, that is,

[Equation 3] By doing so, the output of the counter (P3001) of the first embodiment is counted by the comparator 5 (P3006) by 857,

[Equation 4] And an extended horizontal synchronizing signal (T412) is obtained. Similarly, the output of the counter (P3001) is compared with the comparator 7
(P3008) counted 768,

[Equation 5] And an extended horizontal video period shown at T413 is obtained. This controls the row selection signal and the LD pulse necessary for driving the panel of Embodiment 1, and 12.319.
By performing PWM (pulse width modulation) with a clock of MHz, it is possible to allocate a video period to the vertical blanking period in T402 and obtain a video signal (T413) having only a horizontal blanking period. As a result, the light emission time of the cold cathode electron source is extended by increasing the image period, and the brightness can be increased.

(Second Embodiment) In the second embodiment, the amplitude modulation using the PLL is performed according to the entire block diagram of FIG. 9, the block diagram of the PLL (Phase lock loop) circuit of FIG. 10, and the timing diagram of FIG. A method of controlling the driving period of the signal to increase the average luminance will be described.

Since the detailed functions of the respective parts in FIG. 9 are almost the same as those in FIG. 1, the same components are designated by the same reference numerals, and the description thereof will be omitted. Only the different parts will be described here.

First, the panel control reference signal generator (P21) of FIG. 9 will be described with reference to FIG. The panel control signal generator (P21) as a signal generator receives the vertical synchronizing signal (reference signal) VD from the timing generator (P2) and outputs it from the comparator 3 (P4006) of FIG. The vertical synchronization signal (comparison target signal) VD4 is compared by a phase comparator (phase comparison circuit) (P4000), and the phase difference signal is converted into a DC voltage by the filter unit (P4001). Oscillator part (voltage controlled oscillator circuit) (P4
002) is a voltage-controlled oscillator whose output frequency can be changed by DC voltage control,
The oscillation frequency changes depending on the C voltage input. The output from the oscillator section (P4002) is the counter section (P40
03) and the comparator 3 (P
4006) outputs the drive vertical synchronizing signal VD4. That is, the panel control signal generator (P
8) constitutes a PLL circuit. Since such a loop structure is provided, the comparator 1 (P4004) to the comparator 6
The output of (P4009) and CLK4 are synchronized with the input VD. The output of the oscillator unit (P4002) is used as CLK4 as a synchronous clock for reading control of the field memory. In addition, the oscillator (P40
02) is input to the counter (P4003), and the count output of the counter section is used as the comparator 1 (P4004), the comparator 2 (P4005), the comparator 3 (P4006), the comparator 4 (P4007), and the comparator 5 (P4008), the comparator 6 (P4009) decodes it, and the comparator 1 (P400
4) is a field memory read enable signal, comparator 2 (P4005) is a field memory read line reset signal, comparator 3 (P4006) is a field memory vertical reset signal, and comparator 4 (P4007) is a field memory horizontal signal. Reset signal, comparator 5 (P4
008) outputs a PHM (Pulse Height Modulation) load signal, and the comparator 6 (P4009) outputs a PHM row selection signal. Here, the frequency division circuit is configured by the counter unit (P4003) and the comparator 3 (P4006), and the phase comparator (P4000) and the filter unit (P400).
1), the oscillator section (P4002) and the frequency dividing circuit constitute a clock generating circuit.

The PHM generator section (P1105)
8-bit data from the shift register (P1101) is loaded by the PHM load signal, and while the PHM enable signal is enabled (L), a pulse having an amplitude corresponding to the value of the 8-bit data is output. Here, the shift register (P1101) and the PHM generator section (P110)
5) and the switch means (P1104) form a column wiring drive circuit. In addition, the panel control signal generator (P
21) may receive the horizontal synchronizing signal HD from the timing generator (P2) as a reference signal.

Next, the relationship between the signals will be described with reference to FIG.

T201 to T205 are outputs of the field memory write control unit (P12), and are CLK2, HD, and V which are outputs of the timing generation unit (P2), respectively.
It is synchronized with D.

The field memory (P9) is VD2 (T2
01) is reset vertically and the line reset signal (T2
04), while the line address is incremented, the write enable signal (T203) is L while CLK2
The video signal from the line memory (P10) is written in synchronization with (T205). The drive vertical signal VD4 shown at T510 is an output of the comparator 3 (P4006) of the panel control reference signal generator (P21) and is used by the Y driver timing generator.

In this embodiment, the drive vertical synchronizing signal VD4 (T510) and the drive horizontal synchronizing signal HD3 (T51) shown in FIG. 10, which are outputs from the panel control reference signal generator (P21), are output.
1), field memory read enable signal (T51
2), field memory line reset signal (T51
3), among the PHM load signal and the row selection signal, the drive vertical synchronization signal VD4 is output from the timing generation unit (P2) so that it has the same cycle as VD2 (T201) which is the reference of the write timing of the field memory (P9). VD and the drive vertical synchronizing signal VD4 are supplied to the phase comparator (P4
000), and the drive horizontal synchronizing signal HD3 (T51
1), field memory read enable signal (T51
2), field memory line reset signal (T51
3), the period of the PHM load signal and the row selection signal is multiplied by (vertical synchronization period / vertical video period) of CLK2 for the purpose of eliminating the vertical blanking period.
9) and the shift register (P1101), if the row selection period (effective period of one line) is originally intended, the first line selection signal (T206) and the second line selection signal (T206)
207) The third line selection signal (T208), the fourth line selection signal (T209), ..., The first line enable signal (T515), the second line enable signal (T516), the first line PHM output (T51
7) The effective period of one line is extended by allocating the vertical blanking period to each horizontal synchronization period so that the second line PHM output (T518) is output.

As described above, in this embodiment, the display panel is driven line by line. Therefore, by performing the processing for extending the effective period of one line as described above, the driving time of each cold cathode element is extended, whereby the amount of electrons received by the phosphor (not shown) is increased and the brightness is increased. it can.

Example 2 Example 2 will be described as a more specific example of the second embodiment.

For example, when the vertical video period is 480 lines, the vertical synchronization period is 525 lines, and the horizontal synchronization period is 768 clocks, the decode value of the comparator 3 (P4006) that outputs VD4 (T510) of the second embodiment is 480. * 7
Oscillator by setting to 68 (P4002)
Output CLK4 has a frequency that is (480/525) times the frequency of the clock CLK2 output by the timing generator (P2). As a result, the enable signal (LE) of each line of the PHM can increase the row selection time during the horizontal period as in the case of T515 and T516, as compared with the conventional selection signal of each selection line of T206 and T207. As a result, the row selection time of the PHM output is increased, so that the driving time of each cold cathode element is extended, which increases the amount of electrons received by the phosphor (not shown), thereby increasing the brightness.

In the above embodiments, an example in which an electron-emitting device, particularly a surface conduction-type emitting device is used as a display device has been described, but a field emission type or MIM type electron-emitting device can also be used. An electroluminescent element can also be preferably used.

[0110]

According to the present invention, since the horizontal blanking period and the vertical blanking period, which have been ineffective until now, can be used as the display period, the driving time of each display element is extended, and thus the image display device The brightness can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of a matrix display device using a cold cathode device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a field memory write timing generation unit.

FIG. 3 is a timing diagram of a field memory write / read control signal.

FIG. 4 is a block diagram of a field memory read timing generation unit.

FIG. 5 shows P for a field memory write control signal.
It is a timing diagram of a WM control signal.

6 is a timing diagram of the display device shown in FIG. 1. FIG.

FIG. 7 shows the clock of the panel control signal generator P8 as 13.
5MHz 1 / ((vertical sync period / vertical video period) *
(Vertical synchronization period / horizontal video period)) FIG.

FIG. 8 shows the clock of the panel control signal generator P8 as 13.
It is a timing diagram when it is 1 / (vertical synchronization period / vertical video period) of 5 MHz.

FIG. 9 is a block diagram of a matrix display device using a cold cathode device for controlling memory reading using a PLL according to a second embodiment of the present invention.

FIG. 10 is a block diagram of a PLL unit.

FIG. 11 is a timing diagram in the case of controlling reading using a PLL.

FIG. 12 is a diagram showing an example of a conventionally known surface conduction electron-emitting device.

FIG. 13 is a diagram showing an example of a conventionally known FE type element.

FIG. 14 is a diagram showing an example of a conventionally known MIM type element.

FIG. 15 is a diagram showing an example of a vertical deflection circuit and a drive waveform for a conventionally known CRT.

[Explanation of symbols] P8 Panel control reference signal generator P11 MPU P19 Y driver control timing generator P20 X driver control timing generator P21 Panel control reference signal generator (PLL part) P1001 shift register P1002 Y shift register P1003 pre-driver P1004 Switch means that conducts when row is selected P1006 Switch that conducts when delinquent is selected P1102 PWM generator section P1104 Switch composed of transistors etc. P1105 PHM generator section P2000 display panel P2001 Cold cathode device P2002 Row wiring P2003 column wiring P3000 oscillator circuit P3001 counter circuit P3002-8 Comparator 1-7 P4000 phase comparator P4001 Low pass filter P4002 oscillator circuit P4003 counter circuit P4004-9 Comparators 1-6

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 642 G09G 3/20 642D H04N 5/66 H04N 5/66 B

Claims (19)

[Claims] 1. A plurality of row wirings, a plurality of column wirings, a plurality of display elements electrically controlled by the row wirings and the column wirings, and any of the row wirings. A row selection drive circuit for selecting and driving, a column wiring drive circuit for driving a column wiring by applying a modulation signal modulated based on an input video signal to each of the column wirings, and the row wiring A signal generation circuit for generating a control signal for determining a drive period of a row selection signal to be selected, and a predetermined vertical sync period, vertical video period, horizontal sync period and horizontal video period An image display device that displays an image based on a driving period of the row selection signal, which is determined by a control signal generated by the signal generation circuit, is more than one time the horizontal image period of an input video signal. Long, ( Synchronization period /
An image display device having a vertical video period) * (horizontal synchronization period / horizontal video period) times or less. 2. The drive period of the row selection signal determined by the control signal is (vertical synchronization period / vertical image period) * (horizontal synchronization period / horizontal image) with respect to the horizontal image period of the input video signal. The image display device according to claim 1, wherein the image display device has a period of time. 3. The driving period of the row selection signal determined by the control signal is (vertical synchronization period / vertical image period) times the horizontal image period of the input video signal. Image display device. 4. A cycle of a clock signal serving as a reference of the control signal is longer than one time of a cycle of a sampling reference clock signal serving as a reference when sampling the input video signal, and the vertical synchronizing period / vertical The image display device according to claim 1, wherein the image period is * (horizontal synchronization period / horizontal image period) times or less. 5. A cycle of a clock signal serving as a reference of the control signal is (vertical synchronization period / vertical video period) * (of a period of a sampling reference clock signal serving as a reference when sampling the input video signal. The image display device according to claim 2, wherein the image display device has a length of (horizontal synchronization period / horizontal video period) times. 6. A cycle of a clock signal which is a reference of the control signal is (vertical synchronization period / vertical image period) times a cycle of a sampling reference clock signal which is a reference when sampling the input video signal. The image display device according to claim 3. 7. The signal generation circuit compares a clock generation circuit that generates the clock signal, a counter circuit that counts the clock signal, an output of the counter circuit with a predetermined value, and a row wiring driving synchronization. A driving horizontal synchronization signal for obtaining the above and a row selection signal are output, a row wiring is selected in a cycle of the driving horizontal synchronization signal, and the row wiring is driven according to the row selection signal. Four
7. The image display device according to any one of 6 to 6. 8. The image display according to claim 7, wherein the counter circuit has a function of resetting a count value in response to the input of a vertical synchronizing signal of the input video signal or a signal synchronized with the vertical synchronizing signal. apparatus. 9. The image display device according to claim 7, wherein the clock generation circuit includes a crystal oscillator that oscillates a fixed frequency. 10. A phase comparison circuit in which the clock generation circuit compares phases of a reference signal and a comparison target signal, a filter for removing a predetermined frequency component from an output signal of the phase comparison circuit, and an output signal of the filter. A voltage-controlled oscillation circuit that oscillates / outputs a signal having a frequency corresponding to the voltage value of, and a frequency-dividing circuit that frequency-divides the output signal of the voltage-controlled oscillation circuit. To the phase comparison circuit as a comparison target signal, and the clock signal generated by the clock generation circuit is a horizontal synchronization signal or a vertical sync signal of the video signal input to the phase comparison circuit as the reference signal. 8. The signal which is oscillated and output by the voltage controlled oscillation circuit in synchronization with a synchronization signal.
The image display device according to. 11. The image display device according to claim 7, wherein the clock generation circuit has a function of changing a frequency of a generated clock signal. 12. The comparison circuit has a function of comparing with a predetermined value according to the type of an input video signal.
The image display device according to any one of 1 to 11. 13. The input video signal is an HDTV.
(High Definition Television), SDTV (Standard
definition television), VGA (Video Graphics Arr)
13. The image display device according to claim 12, wherein the image signal is a video signal according to any one of ay) and XGA (Extended Graphics Array). 14. The modulated signal is a signal modulated by a pulse width modulation method, and the pulse width modulated basic clock signal is an output of the clock generation circuit or a signal obtained by dividing the output of the clock generation circuit. Item 14. The image display device according to any one of items 1 to 13. 15. The image display device according to claim 1, wherein the modulation signal is a signal modulated by a pulse amplitude modulation method. 16. The image display device according to claim 1, wherein the display element is a surface conduction electron-emitting device. 17. A plurality of row wirings, a plurality of column wirings, a plurality of display elements electrically controlled by the row wirings and the column wirings, and any one of the row wirings. A row selection drive circuit for selecting and driving, a column wiring drive circuit for driving a column wiring by applying a modulation signal modulated based on an input video signal to each of the column wirings, and the row wiring A signal generation circuit for generating a control signal for determining a drive period of a row selection signal to be selected, and a predetermined vertical synchronization period, a vertical video period, a horizontal synchronization period, and an input video signal having a horizontal video period. A driving method of an image display device which displays an image based on a driving period of the row selection signal determined by a control signal generated by the signal generating circuit, with respect to a horizontal video period of an input video signal, 1x Long, (vertical synchronization period /
Vertical image period) * (horizontal synchronization period / horizontal image period) times less than or equal to the driving method of the image display device. 18. The driving period of the row selection signal determined by the control signal generated by the signal generating circuit is (vertical synchronization period / vertical image period) * (with respect to the horizontal video period of the input video signal. 18. The method for driving an image display device according to claim 17, wherein the horizontal display period is equal to the horizontal synchronization period / horizontal video period. 19. The driving period of the row selection signal determined by the control signal generated by the signal generating circuit is (vertical synchronization period / vertical image period) times the horizontal image period of the input video signal. The driving method of the image display device according to claim 17.